DE102004046543A1 - Wortleitungssegment-Aktivierungsverfahren und zugehöriger Halbleiterspeicherbaustein - Google Patents

Wortleitungssegment-Aktivierungsverfahren und zugehöriger Halbleiterspeicherbaustein Download PDF

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Publication number
DE102004046543A1
DE102004046543A1 DE102004046543A DE102004046543A DE102004046543A1 DE 102004046543 A1 DE102004046543 A1 DE 102004046543A1 DE 102004046543 A DE102004046543 A DE 102004046543A DE 102004046543 A DE102004046543 A DE 102004046543A DE 102004046543 A1 DE102004046543 A1 DE 102004046543A1
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DE
Germany
Prior art keywords
word line
level
semiconductor memory
row
command decoder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE102004046543A
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English (en)
Inventor
Min-Sang Park
Yu-Lim Lee
Seong-Jin Jang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE102004046543A1 publication Critical patent/DE102004046543A1/de
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

Die Erfindung bezieht sich auf ein Wortleitungssegment-Aktivierungsverfahren für einen Halbleiterspeicherbaustein und auf einen zugehörigen Halbleiterspeicherbaustein. DOLLAR A Erfindungsgemäß ist eine selektive Wortleitungssegmentaktivierung vorgesehen, bei der ein erstes Segment (WL<0_1>) einer Wortleitung (WL<0>) aktiviert wird, welches von einer zugeführten Zeilenadresse und einem Befehl ausgewählt wird, während ein zweites Segment (WL<0_2>) der Wortleitung nicht aktiviert wird, welches von der Zeilenadresse ausgewählt wird. DOLLAR A Verwendung z. B. für Halbleiterspeicherbausteine vom DRAM-Typ.
DE102004046543A 2003-09-26 2004-09-21 Wortleitungssegment-Aktivierungsverfahren und zugehöriger Halbleiterspeicherbaustein Withdrawn DE102004046543A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020030066984A KR100614640B1 (ko) 2003-09-26 2003-09-26 워드라인 부분활성화 커맨드를 갖는 반도체메모리장치

Publications (1)

Publication Number Publication Date
DE102004046543A1 true DE102004046543A1 (de) 2005-04-28

Family

ID=34374198

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102004046543A Withdrawn DE102004046543A1 (de) 2003-09-26 2004-09-21 Wortleitungssegment-Aktivierungsverfahren und zugehöriger Halbleiterspeicherbaustein

Country Status (5)

Country Link
US (1) US7187615B2 (de)
JP (1) JP4594015B2 (de)
KR (1) KR100614640B1 (de)
CN (1) CN100568384C (de)
DE (1) DE102004046543A1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7793037B2 (en) * 2005-05-31 2010-09-07 Intel Corporation Partial page scheme for memory technologies
JP4769548B2 (ja) 2005-11-04 2011-09-07 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体記憶装置
US7697364B2 (en) * 2005-12-01 2010-04-13 Broadcom Corporation Memory architecture having multiple partial wordline drivers and contacted and feed-through bitlines
KR100704039B1 (ko) 2006-01-20 2007-04-04 삼성전자주식회사 디코딩 신호가 워드라인 방향으로 버싱되는 반도체 메모리장치
TWI417894B (zh) * 2007-03-21 2013-12-01 Ibm 於動態隨機存取記憶體架構之定址期間實施省電之結構及方法
KR101311713B1 (ko) 2007-07-31 2013-09-26 삼성전자주식회사 메모리 코어, 이를 포함하는 반도체 메모리 장치
US8437215B2 (en) * 2011-01-20 2013-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Memory with word-line segment access
US9214219B2 (en) 2011-08-30 2015-12-15 Rambus Inc. Distributed sub-page selection
KR102133573B1 (ko) 2013-02-26 2020-07-21 삼성전자주식회사 반도체 메모리 및 반도체 메모리를 포함하는 메모리 시스템
US9601183B1 (en) 2016-04-14 2017-03-21 Micron Technology, Inc. Apparatuses and methods for controlling wordlines and sense amplifiers
KR102550685B1 (ko) * 2016-07-25 2023-07-04 에스케이하이닉스 주식회사 반도체장치
US20180188988A1 (en) * 2017-01-04 2018-07-05 Qualcomm Incorporated Partial page access in a low power memory system

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4695981A (en) 1984-12-04 1987-09-22 Hewlett-Packard Company Integrated circuit memory cell array using a segmented word line
KR940001159A (ko) * 1992-06-19 1994-01-10 김광호 비멀티플렉시드 어드레스 메모리 장치
JP3908338B2 (ja) * 1997-06-30 2007-04-25 富士通株式会社 半導体記憶装置
US5978304A (en) * 1998-06-30 1999-11-02 Lsi Logic Corporation Hierarchical, adaptable-configuration dynamic random access memory
KR100316713B1 (ko) * 1999-06-26 2001-12-12 윤종용 반도체 메모리 장치 및 이에 적합한 구동신호 발생기
KR100399034B1 (ko) * 2000-05-02 2003-09-22 한국과학기술원 효율적 메모리 셀 어레이 관리 방법
JP2002269982A (ja) * 2001-03-07 2002-09-20 Toshiba Corp 半導体メモリ
KR100443910B1 (ko) * 2001-12-17 2004-08-09 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 메모리 셀 억세스 방법

Also Published As

Publication number Publication date
CN100568384C (zh) 2009-12-09
KR20050030468A (ko) 2005-03-30
JP2005108408A (ja) 2005-04-21
US20050068840A1 (en) 2005-03-31
US7187615B2 (en) 2007-03-06
KR100614640B1 (ko) 2006-08-22
JP4594015B2 (ja) 2010-12-08
CN1627443A (zh) 2005-06-15

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R016 Response to examination communication
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee

Effective date: 20150401