WO2007025816A3 - Speicheranordnung und betriebsverfahren dafür - Google Patents

Speicheranordnung und betriebsverfahren dafür Download PDF

Info

Publication number
WO2007025816A3
WO2007025816A3 PCT/EP2006/064768 EP2006064768W WO2007025816A3 WO 2007025816 A3 WO2007025816 A3 WO 2007025816A3 EP 2006064768 W EP2006064768 W EP 2006064768W WO 2007025816 A3 WO2007025816 A3 WO 2007025816A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory arrangement
memory
data
error
data memory
Prior art date
Application number
PCT/EP2006/064768
Other languages
English (en)
French (fr)
Other versions
WO2007025816A2 (de
Inventor
Thomas Kottke
Yorck Collani
Markus Ferch
Original Assignee
Bosch Gmbh Robert
Thomas Kottke
Yorck Collani
Markus Ferch
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bosch Gmbh Robert, Thomas Kottke, Yorck Collani, Markus Ferch filed Critical Bosch Gmbh Robert
Priority to US11/989,383 priority Critical patent/US20090327838A1/en
Priority to JP2008528446A priority patent/JP4917604B2/ja
Priority to EP06778041A priority patent/EP1924916A2/de
Publication of WO2007025816A2 publication Critical patent/WO2007025816A2/de
Publication of WO2007025816A3 publication Critical patent/WO2007025816A3/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/16—Protection against loss of memory contents
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

Eine Speicheranordnung umfasst einen beschreibbaren Datenspeicher (102) sowie Mittel zum Erkennen (103) eines Fehlers in einem aus dem Datenspeicher (102) gelesenen Datenwort, zum Korrigieren (101) des Fehlers und zum Speichern (101) des korrigierten Datenworts an eine neue Adresse in einem freien Bereich des Datenspeichers (102).
PCT/EP2006/064768 2005-08-30 2006-07-28 Speicheranordnung und betriebsverfahren dafür WO2007025816A2 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US11/989,383 US20090327838A1 (en) 2005-08-30 2006-07-28 Memory system and operating method for it
JP2008528446A JP4917604B2 (ja) 2005-08-30 2006-07-28 記憶装置構成およびその駆動方法
EP06778041A EP1924916A2 (de) 2005-08-30 2006-07-28 Speicheranordnung und betriebsverfahren dafür

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102005040916A DE102005040916A1 (de) 2005-08-30 2005-08-30 Speicheranordnung und Betriebsverfahren dafür
DE102005040916.4 2005-08-30

Publications (2)

Publication Number Publication Date
WO2007025816A2 WO2007025816A2 (de) 2007-03-08
WO2007025816A3 true WO2007025816A3 (de) 2007-05-24

Family

ID=37708307

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2006/064768 WO2007025816A2 (de) 2005-08-30 2006-07-28 Speicheranordnung und betriebsverfahren dafür

Country Status (8)

Country Link
US (1) US20090327838A1 (de)
EP (1) EP1924916A2 (de)
JP (1) JP4917604B2 (de)
KR (1) KR20080037060A (de)
CN (1) CN101253485A (de)
DE (1) DE102005040916A1 (de)
RU (1) RU2008111995A (de)
WO (1) WO2007025816A2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2413638B1 (de) * 2007-09-14 2015-10-07 BlackBerry Limited System und Verfahren für diskontinuierliche Empfangssteuerungsstartzeit
JP5813450B2 (ja) * 2011-10-17 2015-11-17 日立オートモティブシステムズ株式会社 電子制御装置
CN103514058B (zh) * 2012-06-29 2016-06-15 华为技术有限公司 一种数据失效的处理方法、设备及系统
JP6102515B2 (ja) * 2013-05-24 2017-03-29 富士通株式会社 情報処理装置、制御回路、制御プログラム、および制御方法
FR3025035B1 (fr) * 2014-08-22 2016-09-09 Jtekt Europe Sas Calculateur pour vehicule, tel qu’un calculateur de direction assistee, pourvu d’un enregistreur d’evenements integre
RU2682843C1 (ru) * 2015-03-10 2019-03-21 Тосиба Мемори Корпорейшн Устройство памяти и система памяти
US9772899B2 (en) * 2015-05-04 2017-09-26 Texas Instruments Incorporated Error correction code management of write-once memory codes
US11481273B2 (en) * 2020-08-17 2022-10-25 Micron Technology, Inc. Partitioned memory having error detection capability

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0708403A2 (de) * 1994-10-17 1996-04-24 International Business Machines Corporation Datenspeicherungsbibliotheken
US5719808A (en) * 1989-04-13 1998-02-17 Sandisk Corporation Flash EEPROM system
US6119245A (en) * 1997-08-06 2000-09-12 Oki Electric Industry Co., Ltd. Semiconductor storage device and method of controlling it
EP1096379A1 (de) * 1999-11-01 2001-05-02 Koninklijke Philips Electronics N.V. Datenschaltung mit einem nichtflüchtigen Speicher und mit einer fehlerkorrigierenden Schaltung
US20030206460A1 (en) * 1999-09-17 2003-11-06 Kunihiro Katayama Storage device counting error correction

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2830308B2 (ja) * 1990-02-26 1998-12-02 日本電気株式会社 情報処理装置
JPH08234928A (ja) * 1995-02-22 1996-09-13 Matsushita Electric Ind Co Ltd 情報記憶制御装置
JP2002109895A (ja) * 1996-02-29 2002-04-12 Hitachi Ltd 半導体記憶装置
JP4059472B2 (ja) * 2001-08-09 2008-03-12 株式会社ルネサステクノロジ メモリカード及びメモリコントローラ
JP4213053B2 (ja) * 2004-01-29 2009-01-21 Ｔｄｋ株式会社 メモリコントローラ及びメモリコントローラを備えるフラッシュメモリシステム、並びに、フラッシュメモリの制御方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5719808A (en) * 1989-04-13 1998-02-17 Sandisk Corporation Flash EEPROM system
EP0708403A2 (de) * 1994-10-17 1996-04-24 International Business Machines Corporation Datenspeicherungsbibliotheken
US6119245A (en) * 1997-08-06 2000-09-12 Oki Electric Industry Co., Ltd. Semiconductor storage device and method of controlling it
US20030206460A1 (en) * 1999-09-17 2003-11-06 Kunihiro Katayama Storage device counting error correction
EP1096379A1 (de) * 1999-11-01 2001-05-02 Koninklijke Philips Electronics N.V. Datenschaltung mit einem nichtflüchtigen Speicher und mit einer fehlerkorrigierenden Schaltung

Also Published As

Publication number Publication date
JP2009506445A (ja) 2009-02-12
KR20080037060A (ko) 2008-04-29
RU2008111995A (ru) 2009-12-10
DE102005040916A1 (de) 2007-03-08
EP1924916A2 (de) 2008-05-28
WO2007025816A2 (de) 2007-03-08
US20090327838A1 (en) 2009-12-31
JP4917604B2 (ja) 2012-04-18
CN101253485A (zh) 2008-08-27

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