DE10138585A1 - Speicherzelle - Google Patents

Speicherzelle

Info

Publication number
DE10138585A1
DE10138585A1 DE10138585A DE10138585A DE10138585A1 DE 10138585 A1 DE10138585 A1 DE 10138585A1 DE 10138585 A DE10138585 A DE 10138585A DE 10138585 A DE10138585 A DE 10138585A DE 10138585 A1 DE10138585 A1 DE 10138585A1
Authority
DE
Germany
Prior art keywords
drain
source
control gate
memory cell
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE10138585A
Other languages
German (de)
English (en)
Inventor
Franz Hofmann
Josef Willer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE10138585A priority Critical patent/DE10138585A1/de
Priority to JP2003522178A priority patent/JP4481004B2/ja
Priority to EP02767055A priority patent/EP1415349A2/de
Priority to PCT/DE2002/002759 priority patent/WO2003017374A2/de
Priority to CNA028154541A priority patent/CN1539170A/zh
Priority to KR1020047001792A priority patent/KR100679775B1/ko
Priority to TW091117675A priority patent/TW556320B/zh
Publication of DE10138585A1 publication Critical patent/DE10138585A1/de
Priority to US10/779,557 priority patent/US6998672B2/en
Ceased legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/69IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/691IGFETs having charge trapping gate insulators, e.g. MNOS transistors having more than two programming levels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0413Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors

Landscapes

  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
DE10138585A 2001-08-06 2001-08-06 Speicherzelle Ceased DE10138585A1 (de)

Priority Applications (8)

Application Number Priority Date Filing Date Title
DE10138585A DE10138585A1 (de) 2001-08-06 2001-08-06 Speicherzelle
JP2003522178A JP4481004B2 (ja) 2001-08-06 2002-07-26 メモリーセルおよびメモリーセルに書込みを行う方法
EP02767055A EP1415349A2 (de) 2001-08-06 2002-07-26 Speicherzelle
PCT/DE2002/002759 WO2003017374A2 (de) 2001-08-06 2002-07-26 Speicherzelle
CNA028154541A CN1539170A (zh) 2001-08-06 2002-07-26 记忆胞元
KR1020047001792A KR100679775B1 (ko) 2001-08-06 2002-07-26 메모리 셀 및 그 프로그래밍 방법
TW091117675A TW556320B (en) 2001-08-06 2002-08-06 Memory cell
US10/779,557 US6998672B2 (en) 2001-08-06 2004-02-06 Memory cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10138585A DE10138585A1 (de) 2001-08-06 2001-08-06 Speicherzelle

Publications (1)

Publication Number Publication Date
DE10138585A1 true DE10138585A1 (de) 2003-03-06

Family

ID=7694577

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10138585A Ceased DE10138585A1 (de) 2001-08-06 2001-08-06 Speicherzelle

Country Status (8)

Country Link
US (1) US6998672B2 (enExample)
EP (1) EP1415349A2 (enExample)
JP (1) JP4481004B2 (enExample)
KR (1) KR100679775B1 (enExample)
CN (1) CN1539170A (enExample)
DE (1) DE10138585A1 (enExample)
TW (1) TW556320B (enExample)
WO (1) WO2003017374A2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7184315B2 (en) * 2003-11-04 2007-02-27 Micron Technology, Inc. NROM flash memory with self-aligned structural charge separation
US7202523B2 (en) 2003-11-17 2007-04-10 Micron Technology, Inc. NROM flash memory devices on ultrathin silicon
JP2008053270A (ja) * 2006-08-22 2008-03-06 Nec Electronics Corp 半導体記憶装置、及びその製造方法
KR100846393B1 (ko) * 2007-03-30 2008-07-15 주식회사 하이닉스반도체 반도체 소자의 트랜지스터 및 그 제조 방법

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001156188A (ja) * 1999-03-08 2001-06-08 Toshiba Corp 半導体記憶装置およびその製造方法
DE10036911A1 (de) * 2000-07-28 2002-02-14 Infineon Technologies Ag Multi-Bit-Speicherzelle und Verfahren zur Herstellung

Family Cites Families (22)

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Publication number Priority date Publication date Assignee Title
JPS6418270A (en) * 1987-07-13 1989-01-23 Oki Electric Ind Co Ltd Semiconductor memory device
US5219774A (en) * 1988-05-17 1993-06-15 Xicor, Inc. Deposited tunneling oxide
US5270559A (en) * 1990-10-15 1993-12-14 California Institute Of Technology Method and apparatus for making highly accurate potential well adjustments in CCD's
US5284784A (en) * 1991-10-02 1994-02-08 National Semiconductor Corporation Buried bit-line source-side injection flash memory cell
JPH0613627A (ja) * 1991-10-08 1994-01-21 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
US5910912A (en) * 1992-10-30 1999-06-08 International Business Machines Corporation Flash EEPROM with dual-sidewall gate
US6057575A (en) * 1996-03-18 2000-05-02 Integrated Memory Technologies, Inc. Scalable flash EEPROM memory cell, method of manufacturing and operation thereof
US5963806A (en) * 1996-12-09 1999-10-05 Mosel Vitelic, Inc. Method of forming memory cell with built-in erasure feature
JP3264365B2 (ja) * 1997-03-28 2002-03-11 ローム株式会社 不揮発性記憶素子
US5900657A (en) * 1997-05-19 1999-05-04 National Semiconductor Corp. MOS switch that reduces clock feed through in a switched capacitor circuit
US6281545B1 (en) * 1997-11-20 2001-08-28 Taiwan Semiconductor Manufacturing Company Multi-level, split-gate, flash memory cell
US6091101A (en) * 1998-03-30 2000-07-18 Worldwide Semiconductor Manufacturing Corporation Multi-level flash memory using triple well
US5991204A (en) * 1998-04-15 1999-11-23 Chang; Ming-Bing Flash eeprom device employing polysilicon sidewall spacer as an erase gate
US6043530A (en) * 1998-04-15 2000-03-28 Chang; Ming-Bing Flash EEPROM device employing polysilicon sidewall spacer as an erase gate
US6093945A (en) * 1998-07-09 2000-07-25 Windbond Electronics Corp. Split gate flash memory with minimum over-erase problem
US6107139A (en) * 1998-07-17 2000-08-22 Worldwide Semiconductor Manufacturing Corporation Method for making a mushroom shaped DRAM capacitor
KR100297720B1 (ko) * 1998-10-19 2001-08-07 윤종용 플래쉬메모리셀및그제조방법
US6313500B1 (en) * 1999-01-12 2001-11-06 Agere Systems Guardian Corp. Split gate memory cell
US6228695B1 (en) * 1999-05-27 2001-05-08 Taiwan Semiconductor Manufacturing Company Method to fabricate split-gate with self-aligned source and self-aligned floating gate to control gate
US6388293B1 (en) * 1999-10-12 2002-05-14 Halo Lsi Design & Device Technology, Inc. Nonvolatile memory cell, operating method of the same and nonvolatile memory array
JP2001148434A (ja) * 1999-10-12 2001-05-29 New Heiro:Kk 不揮発性メモリセルおよびその使用方法、製造方法ならびに不揮発性メモリアレイ
US6504207B1 (en) * 2000-06-30 2003-01-07 International Business Machines Corporation Method to create EEPROM memory structures integrated with high performance logic and NVRAM, and operating conditions for the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001156188A (ja) * 1999-03-08 2001-06-08 Toshiba Corp 半導体記憶装置およびその製造方法
US6335554B1 (en) * 1999-03-08 2002-01-01 Kabushiki Kaisha Toshiba Semiconductor Memory
DE10036911A1 (de) * 2000-07-28 2002-02-14 Infineon Technologies Ag Multi-Bit-Speicherzelle und Verfahren zur Herstellung

Also Published As

Publication number Publication date
JP2004538662A (ja) 2004-12-24
KR20040023718A (ko) 2004-03-18
WO2003017374A3 (de) 2003-05-30
JP4481004B2 (ja) 2010-06-16
WO2003017374A2 (de) 2003-02-27
US20040183125A1 (en) 2004-09-23
EP1415349A2 (de) 2004-05-06
US6998672B2 (en) 2006-02-14
KR100679775B1 (ko) 2007-02-06
TW556320B (en) 2003-10-01
CN1539170A (zh) 2004-10-20

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8131 Rejection