JP4481004B2 - メモリーセルおよびメモリーセルに書込みを行う方法 - Google Patents

メモリーセルおよびメモリーセルに書込みを行う方法 Download PDF

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Publication number
JP4481004B2
JP4481004B2 JP2003522178A JP2003522178A JP4481004B2 JP 4481004 B2 JP4481004 B2 JP 4481004B2 JP 2003522178 A JP2003522178 A JP 2003522178A JP 2003522178 A JP2003522178 A JP 2003522178A JP 4481004 B2 JP4481004 B2 JP 4481004B2
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JP
Japan
Prior art keywords
source
drain
control gate
gate
region
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Expired - Fee Related
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JP2003522178A
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English (en)
Japanese (ja)
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JP2004538662A (ja
JP2004538662A5 (enExample
Inventor
ホフマン，フランツ
ヴィラー，ヨーゼフ
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Infineon Technologies AG
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Infineon Technologies AG
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Publication of JP2004538662A5 publication Critical patent/JP2004538662A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/691—IGFETs having charge trapping gate insulators, e.g. MNOS transistors having more than two programming levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors

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  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
JP2003522178A 2001-08-06 2002-07-26 メモリーセルおよびメモリーセルに書込みを行う方法 Expired - Fee Related JP4481004B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10138585A DE10138585A1 (de) 2001-08-06 2001-08-06 Speicherzelle
PCT/DE2002/002759 WO2003017374A2 (de) 2001-08-06 2002-07-26 Speicherzelle

Publications (3)

Publication Number Publication Date
JP2004538662A JP2004538662A (ja) 2004-12-24
JP2004538662A5 JP2004538662A5 (enExample) 2008-02-07
JP4481004B2 true JP4481004B2 (ja) 2010-06-16

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ID=7694577

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003522178A Expired - Fee Related JP4481004B2 (ja) 2001-08-06 2002-07-26 メモリーセルおよびメモリーセルに書込みを行う方法

Country Status (8)

Country Link
US (1) US6998672B2 (enExample)
EP (1) EP1415349A2 (enExample)
JP (1) JP4481004B2 (enExample)
KR (1) KR100679775B1 (enExample)
CN (1) CN1539170A (enExample)
DE (1) DE10138585A1 (enExample)
TW (1) TW556320B (enExample)
WO (1) WO2003017374A2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7184315B2 (en) * 2003-11-04 2007-02-27 Micron Technology, Inc. NROM flash memory with self-aligned structural charge separation
US7202523B2 (en) 2003-11-17 2007-04-10 Micron Technology, Inc. NROM flash memory devices on ultrathin silicon
JP2008053270A (ja) * 2006-08-22 2008-03-06 Nec Electronics Corp 半導体記憶装置、及びその製造方法
KR100846393B1 (ko) * 2007-03-30 2008-07-15 주식회사 하이닉스반도체 반도체 소자의 트랜지스터 및 그 제조 방법

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6418270A (en) * 1987-07-13 1989-01-23 Oki Electric Ind Co Ltd Semiconductor memory device
US5219774A (en) * 1988-05-17 1993-06-15 Xicor, Inc. Deposited tunneling oxide
US5270559A (en) * 1990-10-15 1993-12-14 California Institute Of Technology Method and apparatus for making highly accurate potential well adjustments in CCD's
US5284784A (en) * 1991-10-02 1994-02-08 National Semiconductor Corporation Buried bit-line source-side injection flash memory cell
JPH0613627A (ja) * 1991-10-08 1994-01-21 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
US5910912A (en) * 1992-10-30 1999-06-08 International Business Machines Corporation Flash EEPROM with dual-sidewall gate
US6057575A (en) * 1996-03-18 2000-05-02 Integrated Memory Technologies, Inc. Scalable flash EEPROM memory cell, method of manufacturing and operation thereof
US5963806A (en) * 1996-12-09 1999-10-05 Mosel Vitelic, Inc. Method of forming memory cell with built-in erasure feature
JP3264365B2 (ja) * 1997-03-28 2002-03-11 ローム株式会社 不揮発性記憶素子
US5900657A (en) * 1997-05-19 1999-05-04 National Semiconductor Corp. MOS switch that reduces clock feed through in a switched capacitor circuit
US6281545B1 (en) * 1997-11-20 2001-08-28 Taiwan Semiconductor Manufacturing Company Multi-level, split-gate, flash memory cell
US6091101A (en) * 1998-03-30 2000-07-18 Worldwide Semiconductor Manufacturing Corporation Multi-level flash memory using triple well
US5991204A (en) * 1998-04-15 1999-11-23 Chang; Ming-Bing Flash eeprom device employing polysilicon sidewall spacer as an erase gate
US6043530A (en) * 1998-04-15 2000-03-28 Chang; Ming-Bing Flash EEPROM device employing polysilicon sidewall spacer as an erase gate
US6093945A (en) * 1998-07-09 2000-07-25 Windbond Electronics Corp. Split gate flash memory with minimum over-erase problem
US6107139A (en) * 1998-07-17 2000-08-22 Worldwide Semiconductor Manufacturing Corporation Method for making a mushroom shaped DRAM capacitor
KR100297720B1 (ko) * 1998-10-19 2001-08-07 윤종용 플래쉬메모리셀및그제조방법
US6313500B1 (en) * 1999-01-12 2001-11-06 Agere Systems Guardian Corp. Split gate memory cell
JP3973819B2 (ja) * 1999-03-08 2007-09-12 株式会社東芝 半導体記憶装置およびその製造方法
US6228695B1 (en) * 1999-05-27 2001-05-08 Taiwan Semiconductor Manufacturing Company Method to fabricate split-gate with self-aligned source and self-aligned floating gate to control gate
US6388293B1 (en) * 1999-10-12 2002-05-14 Halo Lsi Design & Device Technology, Inc. Nonvolatile memory cell, operating method of the same and nonvolatile memory array
JP2001148434A (ja) * 1999-10-12 2001-05-29 New Heiro:Kk 不揮発性メモリセルおよびその使用方法、製造方法ならびに不揮発性メモリアレイ
US6504207B1 (en) * 2000-06-30 2003-01-07 International Business Machines Corporation Method to create EEPROM memory structures integrated with high performance logic and NVRAM, and operating conditions for the same
DE10036911C2 (de) * 2000-07-28 2002-06-06 Infineon Technologies Ag Verfahren zur Herstellung einer Multi-Bit-Speicherzelle

Also Published As

Publication number Publication date
JP2004538662A (ja) 2004-12-24
KR20040023718A (ko) 2004-03-18
WO2003017374A3 (de) 2003-05-30
DE10138585A1 (de) 2003-03-06
WO2003017374A2 (de) 2003-02-27
US20040183125A1 (en) 2004-09-23
EP1415349A2 (de) 2004-05-06
US6998672B2 (en) 2006-02-14
KR100679775B1 (ko) 2007-02-06
TW556320B (en) 2003-10-01
CN1539170A (zh) 2004-10-20

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