CS304290A2 - Microprocessor stopping and blocking circuits - Google Patents

Microprocessor stopping and blocking circuits Download PDF

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Publication number
CS304290A2
CS304290A2 CS903042A CS304290A CS304290A2 CS 304290 A2 CS304290 A2 CS 304290A2 CS 903042 A CS903042 A CS 903042A CS 304290 A CS304290 A CS 304290A CS 304290 A2 CS304290 A2 CS 304290A2
Authority
CS
Czechoslovakia
Prior art keywords
bus
microprocessor
signal
cpu
active
Prior art date
Application number
CS903042A
Other languages
Czech (cs)
English (en)
Inventor
Ralph Murray Begun
Patrick Maurice Bland
Mark Edward Dean
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of CS304290A2 publication Critical patent/CS304290A2/cs

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/285—Halt processor DMA
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
  • Debugging And Monitoring (AREA)
  • Microcomputers (AREA)
CS903042A 1989-06-19 1990-06-19 Microprocessor stopping and blocking circuits CS304290A2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/367,828 US5170481A (en) 1989-06-19 1989-06-19 Microprocessor hold and lock circuitry

Publications (1)

Publication Number Publication Date
CS304290A2 true CS304290A2 (en) 1991-11-12

Family

ID=23448790

Family Applications (1)

Application Number Title Priority Date Filing Date
CS903042A CS304290A2 (en) 1989-06-19 1990-06-19 Microprocessor stopping and blocking circuits

Country Status (10)

Country Link
US (1) US5170481A (hu)
EP (1) EP0404413B1 (hu)
JP (1) JPH0664562B2 (hu)
BR (1) BR9002876A (hu)
CS (1) CS304290A2 (hu)
DE (2) DE4018481A1 (hu)
HU (1) HUT57923A (hu)
PE (1) PE8691A1 (hu)
PL (1) PL164259B1 (hu)
RU (1) RU2067314C1 (hu)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1241318B (it) * 1990-11-19 1994-01-10 Olivetti & Co Spa Dispositivo di indirizzamento di memoria
JPH04271453A (ja) * 1991-02-27 1992-09-28 Toshiba Corp 複合電子計算機
TW234178B (hu) * 1991-05-28 1994-11-11 Ibm
CA2067599A1 (en) * 1991-06-10 1992-12-11 Bruce Alan Smith Personal computer with riser connector for alternate master
US5325535A (en) * 1991-06-21 1994-06-28 Compaq Computer Corp. Lock signal extension and interruption apparatus
US5430860A (en) * 1991-09-17 1995-07-04 International Business Machines Inc. Mechanism for efficiently releasing memory lock, after allowing completion of current atomic sequence
EP0537899B1 (en) * 1991-09-27 1999-12-15 Sun Microsystems, Inc. Bus arbitration architecture incorporating deadlock detection and masking
US5239631A (en) * 1991-10-15 1993-08-24 International Business Machines Corporation Cpu bus allocation control
US5473761A (en) * 1991-12-17 1995-12-05 Dell Usa, L.P. Controller for receiving transfer requests for noncontiguous sectors and reading those sectors as a continuous block by interspersing no operation requests between transfer requests
US5577214A (en) * 1992-05-18 1996-11-19 Opti, Inc. Programmable hold delay
JPH0660015A (ja) * 1992-06-08 1994-03-04 Mitsubishi Electric Corp 情報処理装置
US5553248A (en) * 1992-10-02 1996-09-03 Compaq Computer Corporation System for awarding the highest priority to a microprocessor releasing a system bus after aborting a locked cycle upon detecting a locked retry signal
US5553310A (en) * 1992-10-02 1996-09-03 Compaq Computer Corporation Split transactions and pipelined arbitration of microprocessors in multiprocessing computer systems
US5426740A (en) * 1994-01-14 1995-06-20 Ast Research, Inc. Signaling protocol for concurrent bus access in a multiprocessor system
US5533204A (en) * 1994-04-18 1996-07-02 Compaq Computer Corporation Split transaction protocol for the peripheral component interconnect bus
US5758170A (en) * 1995-03-20 1998-05-26 Dell Usa, L.P. System for preventing corruption during CPU reset
US5892954A (en) * 1995-07-07 1999-04-06 Sun Microsystems, Inc. Method and apparatus for refreshing file locks to minimize conflicting accesses to data files
JPH10134008A (ja) * 1996-11-05 1998-05-22 Mitsubishi Electric Corp 半導体装置およびコンピュータシステム
US6633938B1 (en) * 2000-10-06 2003-10-14 Broadcom Corporation Independent reset of arbiters and agents to allow for delayed agent reset
KR100767335B1 (ko) * 2006-12-13 2007-10-17 이노필터 주식회사 도로 매립형 발광표지장치
US9043401B2 (en) * 2009-10-08 2015-05-26 Ebay Inc. Systems and methods to process a request received at an application program interface

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4547849A (en) * 1981-12-09 1985-10-15 Glenn Louie Interface between a microprocessor and a coprocessor
US4719567A (en) * 1982-04-29 1988-01-12 Motorola, Inc. Method and apparatus for limiting bus utilization
JPS6019269A (ja) * 1983-07-13 1985-01-31 Nec Corp 高速デ−タ転送方式
US4611297A (en) * 1983-08-18 1986-09-09 Pitney Bowes Inc. Bus grant circuit
JPS6191752A (ja) * 1984-10-11 1986-05-09 Nec Corp マイクロコンピユ−タ
US4779089A (en) * 1985-11-27 1988-10-18 Tektronix, Inc. Bus arbitration controller
US4787032A (en) * 1986-09-08 1988-11-22 Compaq Computer Corporation Priority arbitration circuit for processor access
US4987529A (en) * 1988-08-11 1991-01-22 Ast Research, Inc. Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters

Also Published As

Publication number Publication date
PL285685A1 (en) 1991-03-11
US5170481A (en) 1992-12-08
BR9002876A (pt) 1991-08-20
DE4018481C2 (hu) 1991-08-08
HU903891D0 (en) 1990-11-28
JPH0330045A (ja) 1991-02-08
DE69030688D1 (de) 1997-06-19
JPH0664562B2 (ja) 1994-08-22
EP0404413A2 (en) 1990-12-27
DE4018481A1 (de) 1990-12-20
EP0404413A3 (en) 1992-04-01
DE69030688T2 (de) 1997-11-13
EP0404413B1 (en) 1997-05-14
PL164259B1 (pl) 1994-07-29
PE8691A1 (es) 1991-03-22
RU2067314C1 (ru) 1996-09-27
HUT57923A (en) 1991-12-30

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