CN210575913U - Sealing cover balance filling packaging structure for sorting flip chip - Google Patents

Sealing cover balance filling packaging structure for sorting flip chip Download PDF

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Publication number
CN210575913U
CN210575913U CN201921850773.3U CN201921850773U CN210575913U CN 210575913 U CN210575913 U CN 210575913U CN 201921850773 U CN201921850773 U CN 201921850773U CN 210575913 U CN210575913 U CN 210575913U
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China
Prior art keywords
flip chip
metal cover
substrate
heat
silicon
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Active
Application number
CN201921850773.3U
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Chinese (zh)
Inventor
阳芳芳
陆海琴
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Taiji Semiconductor Suzhou Co ltd
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Taiji Semiconductor Suzhou Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The utility model relates to a sealing cover balance filling packaging structure of a sorting flip chip, which comprises a substrate, a flip chip, a silicon gasket and a metal cover, wherein the metal cover is welded on the substrate, and the flip chip is positioned in the metal cover; filling glue is arranged between the flip chip and the substrate, and silicon gaskets are arranged on the left side and the right side of the back surface of the flip chip; the upper side and the lower side of the silicon gasket are adhered to the flip chip of the metal cover box through the heat conduction adhesive layer; the scheme adopts a structure that upper and lower layers of heat-conducting interface adhesive and left and right silicon gaskets are combined, so that the minimum heat-radiating contact area is ensured, the left and right balance is ensured without position deviation when the metal cover is pasted, and finally, the packaging of a sealing cover product with excellent heat radiation is realized; the heat dissipation coefficient of the heat conduction interface adhesive is 3.4W/Mk, and the heat dissipation coefficient of the silicon gasket is 149W/mK, so that the heat can be quickly transferred from the thin sorting flip chip to the metal cover, and the individual pursuit of a customer on the packaging type can be met.

Description

Sealing cover balance filling packaging structure for sorting flip chip
Technical Field
The utility model relates to a packaging structure is filled to sorting flip-chip's closing cap equilibrium belongs to integrated circuit flip-chip packaging technology field.
Background
When a chip is flip-chip bonded on a substrate or other carrier plates, underfill (underfill) is generally embedded between chip bumps (bump), and the bottom end of a metal cover (Lid) is strongly connected to the substrate or other carrier plates through an adhesive (adhesive) for supporting; the top end of the cavity of the metal cover is communicated to the back surface (non-electrical property surface) of the chip through interface heat dissipation material (TIM glue) to realize heat conduction, and then the metal cover is subjected to ball planting and cutting forming.
When the thickness of the sorting flip chip is less than 500 micrometers and the depth of the cavity of the conventional metal cover is higher than 800 micrometers, the heat dissipation glue with the normal brush interface can not completely fill up the minimum clearance space of about 300 micrometers or even larger, and high-efficiency heat dissipation is realized; therefore, only plastic package (EMC) FCBGA package can be adopted, and the individual requirements of customers on the package form cannot be met; particularly, the metal covers share the die and are uniform in size so as to ensure the minimum cost.
SUMMERY OF THE UTILITY MODEL
The utility model aims at overcoming the not enough of prior art and providing a packaging structure is filled to sorting flip-chip's closing cap equilibrium.
In order to achieve the above purpose, the utility model adopts the technical scheme that: a seal cover balanced filling packaging structure of a sorting flip chip comprises a substrate, a flip chip, a silicon gasket and a metal cover, wherein a frame of the metal cover is welded on the substrate through a welding agent, and the flip chip is positioned in the metal cover; the front surface of the flip chip is provided with a plurality of bumps, filling glue is arranged between the flip chip and the substrate, and the left side and the right side of the back surface of the flip chip are both provided with silicon gaskets; the silicon gasket is adhered to the back of the flip chip through the lower heat conduction adhesive layer on the lower side of the silicon gasket, and the upper side of the silicon gasket is adhered to the metal cover through the upper heat conduction adhesive layer.
Preferably, the filling glue fills gaps between the flip chip and the substrate and gaps between the bumps.
Preferably, the lower heat-conducting adhesive layer and the upper heat-conducting adhesive layer are formed by coating interface heat-dissipation glue.
Preferably, a solder ball is soldered to the bottom of the substrate.
Because of above-mentioned technical scheme's application, compared with the prior art, the utility model have the following advantage:
the scheme adopts a structure that upper and lower layers of heat-conducting interface adhesive and left and right silicon gaskets are combined, so that the minimum heat-radiating contact area is ensured, the left and right balance is ensured without position deviation when the metal cover is pasted, and finally, the packaging of a sealing cover product with excellent heat radiation is realized; the heat dissipation coefficient of the heat conduction interface adhesive is 3.4W/Mk, and the heat dissipation coefficient of the silicon gasket is 149W/mK, so that the heat can be quickly transferred from the thin sorting flip chip to the metal cover, and the individual pursuit of a customer on the packaging type can be met.
Drawings
The technical scheme of the utility model is further explained by combining the attached drawings as follows:
fig. 1 is a schematic diagram of a cap balanced filling package structure for a sorting flip chip according to the present invention;
FIG. 2 is a schematic view of a first step of the process of the present invention;
FIG. 3 is a schematic diagram of a second step of the process of the present invention;
FIG. 4 is a schematic diagram of a third step of the process of the present invention;
FIG. 5 is a fourth schematic view of the process of the present invention;
FIG. 6 is a schematic diagram of a fifth step of the process of the present invention;
FIG. 7 is a sixth schematic view of the process of the present invention;
FIG. 8 is a seventh schematic view of the process of the present invention;
FIG. 9 is an eighth schematic view of the process of the present invention;
fig. 10 is a ninth schematic view of the process of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
As shown in fig. 1, the package structure for balanced filling of a cap of a sorting flip chip according to the present invention comprises a substrate 11, a flip chip 12 and a metal cap 7, wherein a solder ball 9 is soldered on the bottom of the substrate 11, a frame of the metal cap 7 is soldered on the substrate 11 by a solder 6, and the flip chip 12 is located in the metal cap 7; the front surface of the flip chip 12 is provided with a plurality of bumps, filling adhesive 2 is arranged between the flip chip 12 and the substrate 11, and the filling adhesive 2 fills gaps between the flip chip 12 and the substrate 11 and gaps between the bumps; all be provided with silicon gasket 4 on the left and right sides at the flip chip 12 back, silicon gasket 4 pastes at flip chip 12's back through lower heat conduction adhesive linkage 3 of its downside, and silicon gasket 4's upside is through last heat conduction adhesive linkage 5 and the adhesion of metal covering 7, and lower heat conduction adhesive linkage 3 and last heat conduction adhesive linkage 5 are glued by the interface heat dissipation of point-coating and are formed.
This kind of encapsulation lid equilibrium of letter sorting flip chip fills packaging structure mainly for realizing the heat from the quick transmission of slim letter sorting flip chip to metal covering, guarantees minimum heat dissipation area of contact to it has no offset to guarantee to control balanced when metal covering pastes, finally realizes the good encapsulation product encapsulation of heat dissipation.
As shown in fig. 2-10, the process of the package structure is as follows:
the first step is as follows: flip chip bonding;
the thin sorting chip is inversely arranged on the substrate or other carrier plates, and 100% corresponding connection of signals is realized.
The second step is that: filling the bottom of the chip;
the underfill material is applied to all gaps between the thin-type chip sorter and the substrate or other carrier plates by siphoning, and is cured to enhance the connection firmness between the chip bumps and the substrate pads.
The third step: dispensing interface heat dissipation glue for the first time;
and uniformly spot-coating the interface heat dissipation adhesive on two short edges of the back surface of the flip chip to ensure the close adhesive dispensing width and the same adhesive dispensing amount, and then feeding the flip chip into an oven for curing to form lower heat conduction adhesive layers on two sides.
The fourth step: pasting a silicon gasket and baking;
and the silicon gasket is adhered to the two short edges on the back surface of the flip chip through the lower heat-conducting adhesive layer, so that the two sides are ensured to have the same pressing height.
The fifth step: spreading interface heat dissipation glue for the second time;
and respectively coating interface heat dissipation glue on the silicon gaskets on the left side and the right side, ensuring the close glue dispensing width and the same glue dispensing amount, and forming an upper heat conduction bonding layer.
And a sixth step: spot-coating a welding agent;
and spot-coating the welding agent on the annular cover pasting area of the substrate or other carrier plates to ensure uniform BLT and consistent welding width.
The seventh step: sticking a metal cover;
and aligning the metal cover to an annular cover pasting area, namely a welding agent spot coating area, of the substrate or other carrier plates, and controlling the displacement and the pressing height.
Eighth step: fully curing;
the semi-finished product after the metal cover pressing is put into an oven 81, and a pressing block 82 is filled, and then the whole is baked to be fully cured.
The ninth step: planting balls;
the solder balls are soldered on ball pads (ball pads) of the substrate or other carrier boards, so that the chip signal units are effectively communicated with the solder balls through the substrate.
The tenth step: cutting the sheet;
the entire sheet product is cut into individual units using a cutter.
The above is only a specific application example of the present invention, and does not constitute any limitation to the protection scope of the present invention. All the technical solutions formed by equivalent transformation or equivalent replacement fall within the protection scope of the present invention.

Claims (4)

1. The utility model provides a packaging structure is filled to screening flip-chip's closing cap equilibrium which characterized in that: the flip chip packaging structure comprises a substrate (11), a flip chip (12), a silicon gasket (4) and a metal cover (7), wherein the frame of the metal cover (7) is welded on the substrate (11) through a welding agent (6), and the flip chip (12) is positioned in the metal cover (7); the front surface of the flip chip (12) is provided with a plurality of bumps, filling glue (2) is arranged between the flip chip (12) and the substrate (11), and silicon gaskets (4) are arranged on the left side and the right side of the back surface of the flip chip (12); the silicon gasket (4) is adhered to the back surface of the flip chip (12) through the lower heat conduction adhesive layer (3) on the lower side of the silicon gasket, and the upper side of the silicon gasket (4) is adhered to the metal cover (7) through the upper heat conduction adhesive layer (5).
2. The cap balanced fill package structure for sorting flip chips of claim 1, wherein: the filling glue (2) fills gaps between the flip chip (12) and the substrate (11) and gaps between the bumps.
3. The cap balanced fill package structure for sorting flip chips of claim 1, wherein: the lower heat-conducting bonding layer (3) and the upper heat-conducting bonding layer (5) are formed by coating interface heat dissipation glue.
4. The cap balanced fill package structure for sorting flip chips of claim 1, wherein: the bottom of the substrate (11) is welded with a solder ball (9).
CN201921850773.3U 2019-10-31 2019-10-31 Sealing cover balance filling packaging structure for sorting flip chip Active CN210575913U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201921850773.3U CN210575913U (en) 2019-10-31 2019-10-31 Sealing cover balance filling packaging structure for sorting flip chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201921850773.3U CN210575913U (en) 2019-10-31 2019-10-31 Sealing cover balance filling packaging structure for sorting flip chip

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110767617A (en) * 2019-10-31 2020-02-07 太极半导体（苏州）有限公司 Sealing cover balanced filling packaging structure and process for sorting flip chip

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110767617A (en) * 2019-10-31 2020-02-07 太极半导体（苏州）有限公司 Sealing cover balanced filling packaging structure and process for sorting flip chip

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