CN110676231A - FCBGA packaging structure and manufacturing method thereof - Google Patents

FCBGA packaging structure and manufacturing method thereof Download PDF

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Publication number
CN110676231A
CN110676231A CN201910806767.6A CN201910806767A CN110676231A CN 110676231 A CN110676231 A CN 110676231A CN 201910806767 A CN201910806767 A CN 201910806767A CN 110676231 A CN110676231 A CN 110676231A
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China
Prior art keywords
chip
substrate
glue
edge
heat dissipation
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Pending
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CN201910806767.6A
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Chinese (zh)
Inventor
徐晨
林耀剑
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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Priority to CN201910806767.6A priority Critical patent/CN110676231A/en
Publication of CN110676231A publication Critical patent/CN110676231A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83194—Lateral distribution of the layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The invention relates to an FCBGA (Flexible printed Circuit Board) packaging structure and a manufacturing method thereof, wherein the packaging structure comprises a substrate (1), a chip (2) is arranged on the substrate (1) in an inverted mode, a front part area of the chip (2) is connected with the substrate (1) through edge glue (3), a front metal lug of the chip (2) is connected with the substrate (1), bottom filling glue (4) is filled in an area between the periphery of the front metal lug of the chip and the substrate (1), a heat dissipation cover (7) is arranged on the back surface of the chip (2), the heat dissipation cover (7) is connected with the substrate (1) and the chip (2) through heat conduction glue (5), and metal balls (8) are arranged on the back surface of the substrate (1). The front part of the chip is fixed by the edge adhesive, so that the influence of warping degree on the chip area can be relieved, and the risk of cracks of the underfill adhesive at the edge and the corner of the chip is reduced.

Description

FCBGA packaging structure and manufacturing method thereof
Technical Field
The invention relates to an FCBGA packaging structure and a manufacturing method thereof, and belongs to the technical field of semiconductor packaging.
Background
The heat conducting glue is mainly used for forming a heat transfer channel between the chip and the heat radiating cover, and the heat conducting performance of the heat conducting glue is determined by the material characteristics and the coverage rate of the heat conducting glue. Generally, the higher the thermal conductivity of the thermal conductive paste is, the better the coverage rate is, and the more excellent the heat dissipation performance of the package is. In subsequent process and reliability experiments, under the influence of the constant change of the warping degree of the substrate and the chip, the heat conducting glue at the edge is easy to be layered with the chip or the heat dissipation cover, and has great influence on the coverage rate of the heat conducting glue.
The underfill is mainly used for relieving stress, protecting solder balls, preventing the solder balls from being broken with a substrate, and adjusting parameters such as Tg (glass transition temperature), CET (center of temperature), Young modulus and the like of the underfill to achieve the target. With the increase of the size of the packaging body, cracks are easy to appear at the edge and the corner of the chip under the influence of stress, so that the underfill which completely meets the requirements is difficult to find, and the reliability of the packaging body is influenced.
Disclosure of Invention
The invention aims to solve the technical problem of providing an FCBGA packaging structure and a manufacturing method thereof aiming at the prior art, wherein a front part area of a chip is fixed by edge glue, so that the influence of warping degree on the chip area can be relieved, and the risk of cracks on the edge or corner of the chip caused by underfill is reduced.
The technical scheme adopted by the invention for solving the problems is as follows: the utility model provides a FCBGA packaging structure, it includes the base plate, the flip-chip has the chip on the base plate, the positive partial region of chip is glued through the edge and is connected with the base plate, the positive metal convex block of chip is connected with the base plate, the regional packing around the positive metal convex block of chip and between the base plate has the underfill, the chip back is provided with the heat dissipation lid, be connected through the heat conduction glue between heat dissipation lid and the chip.
Preferably, four corners or partial edges of the front surface of the chip are connected with the substrate through edge glue.
Preferably, a groove is formed in the corresponding area of the edge of the back face of the chip, facing the chip, of the heat dissipation cover, and heat conduction glue is embedded in the groove.
A method of making an FCBGA package structure, the method comprising the steps of:
taking a substrate, inversely installing a chip on the substrate, and electrically connecting the chip with the substrate through a metal bump;
secondly, edge glue is arranged on partial area of the front surface of the chip, and then baking and curing are carried out;
filling underfill between the front surface of the chip and the surface of the substrate;
coating a layer of heat-conducting glue on the back surface of the chip and the surface of the substrate part;
bonding a heat dissipation cover on the back surface of the chip, wherein the heat dissipation cover is fixed on the back surface of the chip and the surface of the substrate part through heat conduction glue;
and step six, planting balls on the back of the substrate to complete the subsequent process to obtain the FCBGA packaging structure.
Preferably, the edge of the front surface of the chip in the second step is not continuously glued with the edge at multiple points.
Preferably, the heat dissipation cover in the fifth step is provided with a groove in a corresponding area of the edge of the back of the chip, and the heat-conducting glue is embedded into the groove when the heat dissipation cover is bonded.
Preferably, the thixotropic index of the edge gum in step two is > 3.
Preferably, the thermal expansion coefficient of the edge glue is between that of the chip and the underfill.
Compared with the prior art, the invention has the advantages that:
1. according to the invention, the front part of the chip is fixed by the edge glue, the edge glue has higher thixotropy, Young modulus, glass transition temperature and smaller thermal expansion coefficient, and the higher thixotropy ensures that the glue can not spread to the periphery after the glue dispensing is finished; the relatively high Young modulus can effectively reduce the deformation of the packaging body; the higher glass transition temperature can reduce the warping degree of the whole package; the thermal expansion coefficient between the chip and the underfill can make the thermal expansion coefficient buffer between the chip and the underfill, and share the stress applied to the bottom of the chip, so that the risk of cracks on the edge or corner of the chip caused by the underfill is reduced;
2. according to the invention, the groove structure is added on the edge of the radiating cover, so that the local glue amount can be increased, the binding force between the heat-conducting glue in the edge area and the chip and the radiating cover is improved, the coverage rate of the heat-conducting glue is kept, and the radiating performance of the packaging body is improved.
Drawings
FIG. 1 is a schematic diagram of an FCBGA package structure of the present invention.
Fig. 2 is a top view of one embodiment of fig. 1.
Fig. 3 is a top view of another embodiment of fig. 1.
Fig. 4 to 9 are schematic views illustrating the process flow of a method for manufacturing an FCBGA package structure according to the present invention.
Wherein:
substrate 1
Chip 2
Edge glue 3
Underfill 4
Heat-conducting glue 5
Groove 6
Heat radiation cover 7
And a metal ball 8.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
Referring to fig. 1, the FCBGA package structure of the present invention includes a substrate 1, a chip 2 is flip-chip mounted on the substrate 1, a front portion of the chip 2 is connected to the substrate 1 through an edge glue 3, a front metal bump of the chip 2 is connected to the substrate 1, an underfill glue 4 is filled in a region between the periphery of the front metal bump of the chip and the substrate 1, a heat dissipation cover 7 is disposed on the back of the chip 2, the heat dissipation cover 7 is connected to the substrate 1 and the chip 2 through a thermal conductive glue 5, and a metal ball 8 is disposed on the back of the substrate 1;
the heat dissipation cover 7 is provided with a groove 6 in the corresponding area of the back edge of the chip 2 facing to one side of the chip, and the heat conduction glue 5 is embedded in the groove 6.
Referring to fig. 2, the edge glue 3 is disposed at four corners of the front surface of the chip 2, and is distributed in a dot shape.
Referring to fig. 3, the edge glue 3 is disposed on a portion of the edge of the front surface of the chip 2, and is distributed in a stripe shape.
The manufacturing method comprises the following steps:
step one, referring to fig. 4, a substrate is taken, a chip is inversely arranged on the substrate, and the chip is electrically connected with the substrate through a metal bump;
step two, referring to fig. 5, edge glue is applied to partial areas on the front surface of the chip, and then baking and curing are carried out;
the edge adhesive has higher thixotropy, Young modulus, glass transition temperature and smaller thermal expansion coefficient, the thixotropic index of the edge adhesive is more than 3, and the thermal expansion coefficient of the edge adhesive is between that of the chip and the underfill;
step three, referring to fig. 6, filling underfill between the front surface of the chip and the surface of the substrate;
step four, referring to fig. 7, coating a layer of heat-conducting glue on the back surface of the chip and the surface of the substrate part;
step five, referring to fig. 8, a heat dissipation cover is bonded on the back surface of the chip, and the heat dissipation cover is fixed on the back surface of the chip and the surface of the substrate part through heat conduction glue;
the heat dissipation cover is provided with a groove in a corresponding area of the edge of the back of the chip, and heat conduction glue is embedded into the groove when the heat dissipation cover is bonded;
and step six, referring to fig. 9, implanting balls on the back surface of the substrate, and completing the subsequent process to obtain the FCBGA package structure.
In addition, the present invention also includes other embodiments, and any technical solutions formed by equivalent transformation or equivalent replacement should fall within the protection scope of the claims of the present invention.

Claims (7)

1. An FCBGA package structure, comprising: the novel LED packaging structure comprises a substrate (1), a chip (2) is inversely installed on the substrate (1), the front part of the chip (2) is connected with the substrate (1) through edge glue (3), the front metal lug of the chip (2) is connected with the substrate (1), the area between the periphery of the front metal lug of the chip and the substrate (1) is filled with underfill glue (4), a heat dissipation cover (7) is arranged on the back of the chip (2), the heat dissipation cover (7) is connected with the substrate (1) and the chip (2) through heat conduction glue (5), and a metal ball (8) is arranged on the back of the substrate (1).
2. The FCBGA package structure of claim 1, wherein: the edge glue (3) is arranged at four corners of the front surface of the chip (2) and distributed in a dot shape.
3. The FCBGA package structure of claim 1, wherein: the edge glue (3) is arranged on part of the edge of the front surface of the chip (2) and is distributed in a strip shape.
4. The FCBGA package structure of claim 1, wherein: the heat dissipation cover (7) is provided with a groove (6) in the corresponding area of the edge of the back face of the chip (2), and heat conduction glue (5) is embedded in the groove (6).
5. A manufacturing method of an FCBGA packaging structure is characterized by comprising the following steps:
taking a substrate, inversely installing a chip on the substrate, and electrically connecting the chip with the substrate through a metal bump;
secondly, edge glue is applied to multiple points or continuous corner areas on the edge of the front surface of the chip, and then baking and curing are carried out;
filling underfill between the front surface of the chip and the surface of the substrate;
coating a layer of heat-conducting glue on the back surface of the chip and the surface of the substrate part;
bonding a heat dissipation cover on the back surface of the chip, wherein the heat dissipation cover is fixed on the back surface of the chip and the surface of the substrate part through heat conduction glue;
and step six, planting balls on the back of the substrate to complete the subsequent process to obtain the FCBGA packaging structure.
6. The method of claim 3, wherein the step of forming the FCBGA package structure further comprises: and the thixotropic index of the edge glue in the second step is more than 3.
7. The method of claim 3, wherein the step of forming the FCBGA package structure further comprises: the thermal expansion coefficient of the edge glue is between that of the chip and the underfill.
CN201910806767.6A 2019-08-29 2019-08-29 FCBGA packaging structure and manufacturing method thereof Pending CN110676231A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111446219A (en) * 2020-03-31 2020-07-24 上海兆芯集成电路有限公司 Chip package
CN113206068A (en) * 2020-05-28 2021-08-03 台湾积体电路制造股份有限公司 Semiconductor package and method of manufacturing the same

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Publication number Priority date Publication date Assignee Title
US7256503B2 (en) * 2006-02-27 2007-08-14 International Business Machines Corporation Chip underfill in flip-chip technologies
US20120119353A1 (en) * 2009-08-11 2012-05-17 International Business Machines Corporation Underfill method and chip package
CN103594385A (en) * 2012-08-15 2014-02-19 台湾积体电路制造股份有限公司 Method to control underfill fillet width
US20140306337A1 (en) * 2013-04-12 2014-10-16 Maxim Integrated Products, Inc. Semiconductor device having a buffer material and stiffener
US20180358280A1 (en) * 2017-06-08 2018-12-13 Xilinx, Inc. Methods and apparatus for thermal interface material (tim) bond line thickness (blt) reduction and tim adhesion enhancement for efficient thermal management

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7256503B2 (en) * 2006-02-27 2007-08-14 International Business Machines Corporation Chip underfill in flip-chip technologies
US20120119353A1 (en) * 2009-08-11 2012-05-17 International Business Machines Corporation Underfill method and chip package
CN103594385A (en) * 2012-08-15 2014-02-19 台湾积体电路制造股份有限公司 Method to control underfill fillet width
US20140306337A1 (en) * 2013-04-12 2014-10-16 Maxim Integrated Products, Inc. Semiconductor device having a buffer material and stiffener
US20180358280A1 (en) * 2017-06-08 2018-12-13 Xilinx, Inc. Methods and apparatus for thermal interface material (tim) bond line thickness (blt) reduction and tim adhesion enhancement for efficient thermal management

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111446219A (en) * 2020-03-31 2020-07-24 上海兆芯集成电路有限公司 Chip package
CN111446218A (en) * 2020-03-31 2020-07-24 上海兆芯集成电路有限公司 Chip package
CN113206068A (en) * 2020-05-28 2021-08-03 台湾积体电路制造股份有限公司 Semiconductor package and method of manufacturing the same
TWI751695B (en) * 2020-05-28 2022-01-01 台灣積體電路製造股份有限公司 Semiconductor package and manufacturing method thereof
US11502015B2 (en) 2020-05-28 2022-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof

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