CN210575914U - Double-deck heat dissipation packaging structure of closing cap of sorting flip chip - Google Patents
Double-deck heat dissipation packaging structure of closing cap of sorting flip chip Download PDFInfo
- Publication number
- CN210575914U CN210575914U CN201921853376.1U CN201921853376U CN210575914U CN 210575914 U CN210575914 U CN 210575914U CN 201921853376 U CN201921853376 U CN 201921853376U CN 210575914 U CN210575914 U CN 210575914U
- Authority
- CN
- China
- Prior art keywords
- heat dissipation
- flip chip
- interface heat
- layer
- dissipation glue
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model relates to a sealing cover double-layer heat dissipation packaging structure of a sorting flip chip, which comprises a substrate, a flip chip and a metal cover, wherein the metal cover is welded on the substrate, and the flip chip is positioned in the metal cover; filling glue is arranged between the flip chip and the substrate, a first interface heat dissipation glue layer and a second interface heat dissipation glue layer are arranged between the flip chip and the metal cover, the first interface heat dissipation glue layer is arranged on the back face of the flip chip, the second interface heat dissipation glue layer is arranged on the first interface heat dissipation glue layer, and the second interface heat dissipation glue layer is adhered to the metal cover; according to the scheme, a double-layer interface heat dissipation glue layer is formed between the flip chip and the metal cover in a mode of repeatedly spot-coating and repeatedly curing the interface heat dissipation glue; the device realizes the rapid transfer of heat from the thin sorting flip chip to the metal cover, meets the individual pursuit of a customer on the packaging type, and is suitable for larger gaps between the chip and the metal cover and higher heat dissipation requirements.
Description
Technical Field
The utility model relates to a double-deck heat dissipation packaging structure of closing cap of sorting flip chip belongs to integrated circuit flip chip packaging technology field.
Background
When a chip is flip-chip bonded on a substrate or other carrier plates, underfill (underfill) is generally embedded between chip bumps (bump), and the bottom end of a metal cover (Lid) is strongly connected to the substrate or other carrier plates through an adhesive (adhesive) for supporting; the top end of the cavity of the metal cover is communicated to the back surface (non-electrical property surface) of the chip through interface heat dissipation material (TIM glue) to realize heat conduction, and then the metal cover is subjected to ball planting and cutting forming.
When the thickness of the sorting flip chip is less than 550 micrometers and the depth of the cavity of the conventional metal cover is higher than 800 micrometers, the heat dissipation glue with the normal brush interface can not completely fill up the minimum clearance space of about 300 micrometers or even larger, and high-efficiency heat dissipation is realized; therefore, only plastic package (EMC) FCBGA package can be adopted, and the individual requirements of customers on the package form cannot be met; particularly, the metal covers share the die and are uniform in size so as to ensure the minimum cost.
SUMMERY OF THE UTILITY MODEL
The utility model aims at overcoming the not enough of prior art and providing a double-deck heat dissipation packaging structure of closing cap of sorting flip chip.
In order to achieve the above purpose, the utility model adopts the technical scheme that: a double-layer heat dissipation packaging structure of a sealing cover of a sorting flip chip comprises a substrate, the flip chip and a metal cover, wherein a frame of the metal cover is welded on the substrate through a welding agent, and the flip chip is positioned in the metal cover; the front surface of the flip chip is provided with a plurality of bumps, and filling adhesive is arranged between the flip chip and the substrate; a first interface heat dissipation adhesive layer and a second interface heat dissipation adhesive layer are arranged between the flip chip and the metal cover, the first interface heat dissipation adhesive layer is arranged on the back face of the flip chip, the second interface heat dissipation adhesive layer is arranged on the first interface heat dissipation adhesive layer, and the second interface heat dissipation adhesive layer is adhered to the metal cover.
Preferably, the filling glue fills gaps between the flip chip and the substrate and gaps between the bumps.
Preferably, a solder ball is soldered to the bottom of the substrate.
Preferably, the first interface heat dissipation adhesive layer is formed by spot-coating the interface heat dissipation adhesive on the back surface of the flip chip, and the second interface heat dissipation adhesive layer is formed by spot-coating the interface heat dissipation adhesive on the upper surface of the first interface heat dissipation adhesive layer after semi-curing.
Preferably, the gluing tracks of the first interface heat dissipation glue layer and the second interface heat dissipation glue layer are both in a shape of a circle, and the gluing area of the second interface heat dissipation glue layer is smaller than that of the first interface heat dissipation glue layer.
Because of above-mentioned technical scheme's application, compared with the prior art, the utility model have the following advantage:
according to the scheme, a double-layer interface heat dissipation glue layer is formed between the flip chip and the metal cover in a mode of repeatedly spot-coating and repeatedly curing the interface heat dissipation glue; the device realizes the rapid transfer of heat from the thin sorting flip chip to the metal cover, meets the individual pursuit of a customer on the packaging type, and is suitable for larger gaps between the chip and the metal cover and higher heat dissipation requirements.
Drawings
The technical scheme of the utility model is further explained by combining the attached drawings as follows:
fig. 1 is a schematic diagram of a double-layer heat dissipation package structure of a cap of a sorting flip chip.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
As shown in fig. 1, the present invention relates to a package structure with double heat dissipation layers for a cap of a sorting flip chip, which comprises a substrate 11, a flip chip 12 and a metal cap 7, wherein a solder ball 9 is welded on the bottom of the substrate 11, a frame of the metal cap 7 is welded on the substrate 11 by a solder 6, and the flip chip 12 is located in the metal cap 7; the front surface of the flip chip 12 is provided with a plurality of bumps, filling adhesive 2 is arranged between the flip chip 12 and the substrate 11, and the filling adhesive 2 fills gaps between the flip chip 12 and the substrate 11 and gaps between the bumps; be provided with first interface heat dissipation glue film 3 and second interface heat dissipation glue film 4 between flip chip 12 and the metal covering 7, first interface heat dissipation glue film 3 sets up at flip chip 12's the back, and second interface heat dissipation glue film 4 sets up on first interface heat dissipation glue film 3, and second interface heat dissipation glue film 4 and metal covering 7 adhesion.
The first interface heat dissipation glue layer 3 is formed by point coating interface heat dissipation glue on the back of the flip chip 12, the second interface heat dissipation glue layer 4 is formed by point coating interface heat dissipation glue on the upper surface of the semi-solidified first interface heat dissipation glue layer 3, and the thicknesses of the two interface heat dissipation glue layers are the same as much as possible; the gluing tracks of the first interface heat dissipation glue layer 3 and the second interface heat dissipation glue layer 4 are both in a shape of a circle, and the gluing area of the second interface heat dissipation glue layer 4 is smaller than that of the first interface heat dissipation glue layer 3.
The sealing cover double-layer heat dissipation packaging structure of the sorting flip chip mainly aims at realizing the rapid transfer of heat from the thin sorting flip chip to the metal cover; the heat dissipation requirements of deeper and higher metal covers can also be met.
The processing process of the packaging structure is as follows:
the first step is as follows: flip chip bonding;
the thin sorting chip is inversely arranged on the substrate or other carrier plates, and 100% corresponding connection of signals is realized.
The second step is that: filling the bottom of the chip;
the underfill material is applied to fill the entire gap between the thin-type chip sorter and the substrate or other carrier by siphoning, and cured to enhance the bonding strength between the chip bumps (Bump) and the substrate pads.
The third step: spreading interface heat dissipation glue;
the interface heat dissipation glue is spot-coated on the back of the thin sorting chip, the spot-coating area of the interface heat dissipation glue is controlled, the periphery of the chip cannot overflow, the glue coating track is preferably shaped in a circle to ensure the maximum coverage of the first spot-coating and the optimal glue layer flatness.
Among them, the interface heat dissipation adhesive must consider high viscosity, high heat dissipation, low elongation material.
The fourth step: semi-curing;
and (4) putting the semi-finished product coated with the interface heat dissipation glue into an oven, and setting the temperature and time conditions for semi-curing.
The fifth step: secondary point coating of interface heat dissipation glue;
and (3) secondly dispensing the interface heat dissipation glue on the semi-solidified heat dissipation glue, and similarly, paying attention to control the dispensing area of the interface heat dissipation glue to be smaller than the first dispensing range, wherein the gluing track is preferably shaped in a reverse mode to ensure that the flatness of the dispensed glue layer is optimal, and the second dispensing track can be completely performed along the first dispensing track.
And a sixth step: spot-coating a welding agent;
and spot-coating the welding agent on the annular cover pasting area of the substrate or other carrier plates to ensure uniform BLT and consistent welding width.
The seventh step: sticking a metal cover;
and aligning the metal cover to an annular cover pasting area, namely a welding agent spot coating area, of the substrate or other carrier plates, and controlling the displacement and the pressing height.
Eighth step: fully curing;
and putting the semi-finished product subjected to the metal cover pressing into a baking oven, filling a pressing block, and baking to completely cure the whole product.
The ninth step: planting balls;
the solder balls are soldered on ball pads (ball pads) of the substrate or other carrier boards, so that the chip signal units are effectively communicated with the solder balls through the substrate.
The tenth step: cutting the sheet;
the entire sheet product is cut into individual units using a cutter.
The above is only a specific application example of the present invention, and does not constitute any limitation to the protection scope of the present invention. All the technical solutions formed by equivalent transformation or equivalent replacement fall within the protection scope of the present invention.
Claims (5)
1. A double-deck heat dissipation packaging structure of closing cap of sorting flip chip, include the base plate (11), flip chip (12) and metal covering (7), the frame of the metal covering (7) is welded on the base plate (11) through the welding agent (6), the flip chip (12) is located in metal covering (7); the front surface of the flip chip (12) is provided with a plurality of bumps, and filling glue (2) is arranged between the flip chip (12) and the substrate (11); the method is characterized in that: be provided with first interface heat dissipation glue film (3) and second interface heat dissipation glue film (4) between flip chip (12) and metal covering (7), first interface heat dissipation glue film (3) set up at the back of flip chip (12), and second interface heat dissipation glue film (4) set up on first interface heat dissipation glue film (3), second interface heat dissipation glue film (4) and metal covering (7) adhesion.
2. The cover double-layer heat dissipation packaging structure for sorting flip chips of claim 1, wherein: the filling glue (2) fills gaps between the flip chip (12) and the substrate (11) and gaps between the bumps.
3. The cover double-layer heat dissipation packaging structure for sorting flip chips of claim 1, wherein: the bottom of the substrate (11) is welded with a solder ball (9).
4. The cover double-layer heat dissipation packaging structure for sorting flip chips of claim 1, wherein: the first interface heat dissipation glue layer (3) is formed by point coating of interface heat dissipation glue on the back of the flip chip (12), and the second interface heat dissipation glue layer (4) is formed by point coating of interface heat dissipation glue on the upper surface of the semi-solidified first interface heat dissipation glue layer (3).
5. The cover double-layer heat dissipation packaging structure for sorting flip chips of claim 1, wherein: the gluing tracks of the first interface heat dissipation glue layer (3) and the second interface heat dissipation glue layer (4) are both in a shape of Chinese character 'hui', and the gluing area of the second interface heat dissipation glue layer (4) is smaller than that of the first interface heat dissipation glue layer (3).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921853376.1U CN210575914U (en) | 2019-10-31 | 2019-10-31 | Double-deck heat dissipation packaging structure of closing cap of sorting flip chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921853376.1U CN210575914U (en) | 2019-10-31 | 2019-10-31 | Double-deck heat dissipation packaging structure of closing cap of sorting flip chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210575914U true CN210575914U (en) | 2020-05-19 |
Family
ID=70662220
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921853376.1U Active CN210575914U (en) | 2019-10-31 | 2019-10-31 | Double-deck heat dissipation packaging structure of closing cap of sorting flip chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210575914U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112185916A (en) * | 2020-09-29 | 2021-01-05 | 西安微电子技术研究所 | Double-channel air tightness packaging structure of flip chip and technology thereof |
| CN116504646A (en) * | 2023-06-21 | 2023-07-28 | 青岛泰睿思微电子有限公司 | Multi-chip arrangement packaging structure and method |
-
2019
- 2019-10-31 CN CN201921853376.1U patent/CN210575914U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112185916A (en) * | 2020-09-29 | 2021-01-05 | 西安微电子技术研究所 | Double-channel air tightness packaging structure of flip chip and technology thereof |
| CN116504646A (en) * | 2023-06-21 | 2023-07-28 | 青岛泰睿思微电子有限公司 | Multi-chip arrangement packaging structure and method |
| CN116504646B (en) * | 2023-06-21 | 2023-12-15 | 青岛泰睿思微电子有限公司 | Multi-chip arrangement packaging structure and method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN210575914U (en) | Double-deck heat dissipation packaging structure of closing cap of sorting flip chip | |
| CN100421251C (en) | Semiconductor device and its producing method | |
| CN103109361B (en) | Primer fill method in a kind of semiconductor packages and equipment | |
| CN105762084B (en) | Packaging method and packaging device of flip chip | |
| CN104465595A (en) | CSP type MEMS packaging piece based on customized lead frame and production method | |
| CN103022021A (en) | Semiconductor device and manufacturing method thereof | |
| CN105895539B (en) | Flip-chip encapsulates intermediate structure and flip-chip packaged structure and flip-chip packaged method | |
| CN101114622A (en) | Flip-chip type semiconductor packaging structure and chip bearing member | |
| US20030137046A1 (en) | Semiconductor device, method of fabricating the same, and printing mask | |
| CN110767616A (en) | Sealing cover high-heat-conductivity packaging structure for sorting flip chip and packaging process thereof | |
| CN210575913U (en) | Sealing cover balance filling packaging structure for sorting flip chip | |
| CN110676231A (en) | FCBGA packaging structure and manufacturing method thereof | |
| CN210224006U (en) | Packaging structure of multi-chip | |
| CN207868224U (en) | A kind of more glasss of LED COB display screen modules | |
| CN211265452U (en) | High heat conduction packaging structure of closing cap of sorting flip chip | |
| CN102194707B (en) | Method for manufacturing semiconductor structure | |
| CN106842480A (en) | Sealing module and its processing method | |
| CN110767617A (en) | Sealing cover balanced filling packaging structure and process for sorting flip chip | |
| CN205723615U (en) | A kind of packaging system based on NCSP encapsulation technology | |
| CN115084074A (en) | IC packaging lead frame structure and chip bonding method thereof | |
| CN114823573A (en) | Heat dissipation type packaging structure and forming method thereof | |
| CN209880652U (en) | LED structure of white wall of vertical reflection of light | |
| CN110212073A (en) | Single side CSP and its manufacturing method | |
| TWI353642B (en) | Method for forming a die attach layer during semic | |
| CN207183249U (en) | A kind of encapsulating structure of silicon hole memory chip and copper base |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |