CN116504646A - Multi-chip arrangement packaging structure and method - Google Patents
Multi-chip arrangement packaging structure and method Download PDFInfo
- Publication number
- CN116504646A CN116504646A CN202310735561.5A CN202310735561A CN116504646A CN 116504646 A CN116504646 A CN 116504646A CN 202310735561 A CN202310735561 A CN 202310735561A CN 116504646 A CN116504646 A CN 116504646A
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- copper
- chip
- layer
- substrate
- adhesive layer
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 49
- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000010949 copper Substances 0.000 claims abstract description 95
- 229910052802 copper Inorganic materials 0.000 claims abstract description 95
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 93
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000003292 glue Substances 0.000 claims abstract description 24
- 230000017525 heat dissipation Effects 0.000 claims abstract description 10
- 238000007789 sealing Methods 0.000 claims abstract description 10
- 229910000679 solder Inorganic materials 0.000 claims abstract description 10
- 239000011248 coating agent Substances 0.000 claims abstract description 7
- 238000000576 coating method Methods 0.000 claims abstract description 7
- 239000012790 adhesive layer Substances 0.000 claims description 40
- 239000010410 layer Substances 0.000 claims description 37
- 238000005498 polishing Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 230000005540 biological transmission Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 7
- 239000011295 pitch Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention relates to a multi-chip arrangement packaging structure and a method, wherein the method comprises the following steps: providing a copper plate; planting a plurality of copper columns on the provided copper plate; providing a substrate and connecting the copper column on the substrate; carrying out plastic package on the copper column between the substrate and the copper plate to form a plastic package layer for coating the copper column; removing the copper plate by using a grinding process to expose the copper columns; providing a plurality of chips, and mounting the provided chips on the copper columns; dispensing heat dissipation glue on the chip to form a heat dissipation glue layer; coating insulating glue on the side part of the chip to form an insulating glue layer which is positioned on the corresponding plastic sealing layer and is adhered to the chip; and (5) planting solder balls on the back surface of the substrate, thereby completing packaging. The packaging method of the invention arranges a plurality of chips on the copper column, can effectively reduce the volume of the product, and has the advantages of short production lead time, low manufacturing cost, low power consumption, high data transmission rate, small occupied space and the like.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a multi-chip arrangement packaging structure and a multi-chip arrangement packaging method.
Background
The flip chip packaging structure is only suitable for the situation that the Bump pitch is larger than 60um, and for the situation that the Bump pitch is smaller than 60um, the traditional packaging mode can only adopt a TCB (Thermal Compression Bonding) packaging mode, but the TCB packaging mode has the problems of poor yield and high cost. Therefore, it is desirable to provide a new packaging method to accommodate the situation where the bump pitch is smaller than 60um.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, provides a multi-chip arrangement packaging structure and a multi-chip arrangement packaging method, and solves the problems that the existing flip chip packaging structure cannot be suitable for bump pitches smaller than 60um and the problems of poor yield and high cost of TCB packaging.
The technical scheme for achieving the purpose is as follows:
the invention provides a multi-chip arrangement packaging method, which comprises the following steps:
providing a copper plate;
planting a plurality of copper columns on the provided copper plate;
providing a substrate and connecting the copper column on the substrate;
carrying out plastic packaging on the copper column between the substrate and the copper plate to form a plastic packaging layer for coating the copper column;
removing the copper plate by using a grinding process to expose the copper pillars;
providing a plurality of chips, and mounting the provided chips on the copper columns;
dispensing heat dissipation glue on the chip to form a heat dissipation glue layer;
coating insulating glue on the side part of the chip to form an insulating glue layer which is positioned on the corresponding plastic sealing layer and is attached to the chip;
and (5) planting solder balls on the back surface of the substrate, thereby completing packaging.
The packaging method of the invention arranges a plurality of chips on the copper column, can effectively reduce the volume of the product, can realize packaging chips with different specifications and different sizes such as DRAM, flash memory, SRAM and the like in a single module, stacks 2 to 8 chips on the basis of low cost by adopting a hybrid technology, and has the advantages of short production lead time, low manufacturing cost, low power consumption, high data transmission rate, small occupied space and the like.
The invention further improves the multi-chip arrangement packaging method by providing a radiating fin, and the radiating fin is covered on the insulating adhesive layer and the radiating adhesive layer and is adhered and fixed with the insulating adhesive layer and the radiating adhesive layer.
The invention further improves the multi-chip arrangement packaging method, wherein the provided radiating fin comprises a top plate covered on the insulating glue layer and the radiating glue layer and four side plates connected with the top plate;
when the radiating fins are arranged, the radiating fins are covered and buckled on the insulating adhesive layer and the radiating adhesive layer, and the four side plates of the radiating fins are attached to the side parts corresponding to the insulating adhesive layer and the plastic sealing layer.
The invention further improves the multi-chip arrangement packaging method, wherein when copper columns are planted on the copper plate, the distance between two adjacent copper columns is smaller than 60um.
A further improvement of the multi-chip arrangement packaging method of the present invention is that after the chips are mounted, the chips are wire bonded.
The invention also provides a multi-chip arrangement packaging structure, which comprises:
a substrate;
the copper columns are connected to the substrate, and copper plates capable of being removed through grinding are connected to the tops of the copper columns;
a plastic package layer which is formed between the substrate and the copper plate and wraps the copper column;
a plurality of chips mounted on the copper pillars exposed by polishing the copper plate;
a heat dissipation adhesive layer arranged on the chip;
the insulating adhesive layer is arranged on the side part of the chip and positioned above the corresponding plastic sealing layer;
and the solder balls are arranged on the back surface of the substrate.
The multi-chip arrangement packaging structure is further improved by further comprising a radiating fin which is covered on the insulating adhesive layer.
The multi-chip arrangement packaging structure is further improved in that the radiating fin comprises a top plate and four side plates, wherein the top plate is covered on the insulating adhesive layer and the radiating adhesive layer, the four side plates are vertically connected with the top plate, and the four side plates are attached to the side parts corresponding to the insulating adhesive layer and the plastic sealing layer.
The multi-chip arrangement packaging structure is further improved in that the distance between two adjacent copper columns is smaller than 60um.
The multi-chip arrangement package structure of the present invention is further improved by further comprising bonding wires connected to the chips.
Drawings
Fig. 1 is a schematic structural diagram of a copper plate in the multi-chip arrangement package structure and method of the present invention.
Fig. 2 is a schematic structural view of a copper pillar implanted on a copper plate in the multi-chip arrangement packaging method of the present invention.
Fig. 3 is a schematic structural diagram of a connection between a copper pillar and a substrate in the multi-chip arrangement packaging method of the present invention.
Fig. 4 is a schematic structural diagram of a copper pillar in a multi-chip arrangement packaging method according to the present invention.
Fig. 5 is a schematic structural diagram of the multi-chip arrangement packaging method according to the present invention after polishing to remove the copper plate.
Fig. 6 is a schematic structural diagram of a mounted chip in the multi-chip arrangement packaging method of the present invention.
Fig. 7 is a schematic structural diagram of a heat sink disposed in the multi-chip arrangement packaging method of the present invention.
Fig. 8 is a schematic structural diagram of a method for mounting solder balls on a substrate in the multi-chip arrangement packaging method of the present invention.
Reference numerals illustrate:
21-copper plate; 22-copper columns; 23-a substrate; solder ball-231; 24-plastic sealing layer; 25-chip; 26-a heat radiation adhesive layer; 27-heat sink; 28-an insulating adhesive layer.
Detailed Description
The invention will be further described with reference to the drawings and the specific examples.
Referring to fig. 8, the present invention provides a multi-chip arrangement package structure and method for solving the problems of poor yield and high cost of the conventional TCB package method. According to the invention, the copper columns with the spacing smaller than 60um are planted on the copper plate, the volume of the electronic product is effectively reduced by utilizing the chip arrangement mode, and a plurality of chips are packaged together, so that the method has the advantages of short production lead time, low manufacturing cost, low power consumption, high data transmission rate, small occupied space and the like. The multi-chip arrangement package structure and method of the present invention will be described with reference to the accompanying drawings.
Referring to fig. 8, a cross-sectional view of a multi-chip arrangement package structure of the present invention is shown. The multi-chip arrangement package structure of the present invention will be described with reference to fig. 8.
As shown in fig. 8, the multi-chip arrangement package structure of the present invention includes a substrate 23, copper pillars 22, copper plates 21, a plastic layer 24, a chip 25, a heat dissipation adhesive layer 26, an insulation adhesive layer 28, and solder balls 231; the copper pillars 22 are plural and connected between the substrate 23 and the copper plate 21, and preferably, as shown in fig. 1 and 2, the copper pillars 22 are planted on the copper plate 21, and as shown in fig. 3, the other ends of the copper pillars 22 are connected with the substrate 23, and the copper plate 21 can be removed by post polishing. As shown in fig. 4, a molding layer 24 is formed between the substrate 23 and the copper plate 21 and surrounds the copper pillars 22, and the molding layer 24 is preferably formed of an insulating paste. The plurality of chips 25 are mounted on the copper pillars 22 exposed after the copper plate 21 is polished and removed, and as shown in fig. 5 and 6, the copper plate 21 is polished and removed to expose the copper pillars, and then the plurality of chips 25 are mounted on the copper pillars 22 in an aligned manner. Referring to fig. 7, the heat dissipation adhesive layer 26 is disposed on the chip 25, and the insulating adhesive layer 28 is disposed on a side portion of the chip 25 and on the corresponding plastic layer 24; the solder balls 231 are provided on the back surface of the substrate 23.
Further, as shown in fig. 7 and 8, a heat sink 27 is further included overlying the insulating adhesive layer 28.
Still further, the heat sink 27 includes a top plate covering the insulating adhesive layer 28 and the heat sink adhesive layer 26, and four side plates vertically connected to the top plate, and the four side plates are attached to the corresponding side portions of the insulating adhesive layer 28 and the plastic layer 24.
Still further, the spacing between two adjacent copper pillars 22 is less than 60um.
Still further, a bonding wire connected to the chip 25 is included.
The chip arrangement packaging structure of the invention mainly refers to the stack of a plurality of memory chips, and the package contains a memory subsystem, so that chips with different specifications and different sizes such as DRAM, flash memory and SRAM can be packaged in a single module, and 2 to 8 chips are stacked on a low-cost substrate by adopting a hybrid technology, and the chip arrangement packaging structure has the advantages of short production lead time, low manufacturing cost, low power consumption, high data transmission rate, small occupied space and the like.
The invention also provides a multi-chip arrangement packaging method, and the packaging method is described below.
As shown in fig. 1 to 8, the packaging method of the present invention includes the steps of:
providing a copper plate 21;
a plurality of copper posts 22 are planted on the copper plate 21;
providing a substrate 23, and connecting the copper pillars 22 to the substrate 23;
the copper column 22 between the substrate 23 and the copper plate 21 is subjected to plastic packaging to form a plastic packaging layer 24 which coats the copper column 22;
removing the copper plate 21 by a grinding process to expose the copper pillars 22;
providing a plurality of chips 25, and mounting the provided chips 25 on the copper pillars 22;
dispensing a heat-dissipating adhesive on the chip 25 to form a heat-dissipating adhesive layer 26;
coating insulating glue on the side part of the chip 25 to form an insulating glue layer 28 which is positioned above the corresponding plastic layer 24 and is attached to the chip 25;
solder balls 231 are implanted on the back surface of the substrate 23, thereby completing the package.
When the chip 25 is mounted, the chip 25 is placed on the corresponding copper pillar 22 and the plastic layer 24, and the pins on the chip 25 are electrically connected with the corresponding copper pillar 22.
Further, the method further comprises the following steps: the heat sink 27 is provided, and the heat sink 27 is covered on the insulating adhesive layer 28 and the heat sink adhesive layer 26 and is adhered and fixed with the insulating adhesive layer 28 and the heat sink adhesive layer 26.
Still further, the heat sink 27 is provided to include a top plate overlying the insulating glue layer 28 and the heat sink glue layer 26 and four side plates connected to the top plate;
when the radiating fins 27 are arranged, the radiating fins 27 are covered and buckled on the insulating adhesive layer 28 and the radiating adhesive layer 26, so that the four side plates of the radiating fins 27 are attached to the corresponding side parts of the insulating adhesive layer and the plastic sealing layer.
Further, when the copper pillars 22 are planted on the copper plate 21, the distance between two adjacent copper pillars 22 is smaller than 60um.
Still further, after the chip 25 is mounted, the chip 25 is wire-bonded.
The present invention has been described in detail with reference to the embodiments of the drawings, and those skilled in the art can make various modifications to the invention based on the above description. Accordingly, certain details of the illustrated embodiments are not to be taken as limiting the invention, which is defined by the appended claims.
Claims (10)
1. A multi-chip arrangement packaging method is characterized by comprising the following steps:
providing a copper plate;
planting a plurality of copper columns on the provided copper plate;
providing a substrate and connecting the copper column on the substrate;
carrying out plastic packaging on the copper column between the substrate and the copper plate to form a plastic packaging layer for coating the copper column;
removing the copper plate by using a grinding process to expose the copper pillars;
providing a plurality of chips, and mounting the provided chips on the copper columns;
dispensing heat dissipation glue on the chip to form a heat dissipation glue layer;
coating insulating glue on the side part of the chip to form an insulating glue layer which is positioned on the corresponding plastic sealing layer and is attached to the chip;
and (5) planting solder balls on the back surface of the substrate, thereby completing packaging.
2. The multi-chip arrangement package method of claim 1, further comprising:
and providing a radiating fin, and covering the radiating fin on the insulating adhesive layer and the radiating adhesive layer, and adhering and fixing the radiating fin and the insulating adhesive layer and the radiating adhesive layer.
3. The multi-chip arrangement package method of claim 2 wherein the heat sink provided includes a top plate overlying the insulating glue layer and the heat sink glue layer and four side plates connected to the top plate;
when the radiating fins are arranged, the radiating fins are covered and buckled on the insulating adhesive layer and the radiating adhesive layer, and the four side plates of the radiating fins are attached to the side parts corresponding to the insulating adhesive layer and the plastic sealing layer.
4. The multi-chip arrangement package method of claim 1, wherein when copper pillars are planted on the copper plate, a spacing between two adjacent copper pillars is smaller than 60um.
5. The multi-chip arrangement package method of claim 1, wherein after the chips are mounted, wire bonding is performed on the chips.
6. A multi-chip arrangement package structure, comprising:
a substrate;
the copper columns are connected to the substrate, and copper plates capable of being removed through grinding are connected to the tops of the copper columns;
a plastic package layer which is formed between the substrate and the copper plate and wraps the copper column;
a plurality of chips mounted on the copper pillars exposed by polishing the copper plate;
a heat dissipation adhesive layer arranged on the chip;
the insulating adhesive layer is arranged on the side part of the chip and positioned above the corresponding plastic sealing layer;
and the solder balls are arranged on the back surface of the substrate.
7. The multi-chip arrangement package structure of claim 6 further comprising a heat sink overlying the insulating glue layer.
8. The multi-chip arrangement package structure of claim 7, wherein the heat sink comprises a top plate covering the insulating glue layer and the heat sink glue layer, and four side plates vertically connected to the top plate, and the four side plates are attached to the corresponding side portions of the insulating glue layer and the plastic layer.
9. The multi-chip arrangement package of claim 8 wherein a spacing between two adjacent copper pillars is less than 60um.
10. The multi-chip arrangement package structure of claim 6, further comprising bond wires connected to the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310735561.5A CN116504646B (en) | 2023-06-21 | 2023-06-21 | Multi-chip arrangement packaging structure and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310735561.5A CN116504646B (en) | 2023-06-21 | 2023-06-21 | Multi-chip arrangement packaging structure and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116504646A true CN116504646A (en) | 2023-07-28 |
| CN116504646B CN116504646B (en) | 2023-12-15 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310735561.5A Active CN116504646B (en) | 2023-06-21 | 2023-06-21 | Multi-chip arrangement packaging structure and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116504646B (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5543585A (en) * | 1994-02-02 | 1996-08-06 | International Business Machines Corporation | Direct chip attachment (DCA) with electrically conductive adhesives |
| US20080099925A1 (en) * | 2006-10-31 | 2008-05-01 | Qimonda Ag | Solder pillar bumping and a method of making the same |
| US20130196504A1 (en) * | 2010-11-26 | 2013-08-01 | Tanaka Kikinzoku Kogyo K.K. | Transfer substrate for forming metal wiring and method for forming metal wiring using said transfer substrate |
| US20190189541A1 (en) * | 2017-12-20 | 2019-06-20 | Hefei SMAT Technology Co., LTD | Chip packaging structure and manufacturing method thereof |
| US20200105642A1 (en) * | 2018-09-28 | 2020-04-02 | Xilinx, Inc. | Stacked silicon package assembly having thermal management |
| CN210575914U (en) * | 2019-10-31 | 2020-05-19 | 太极半导体（苏州）有限公司 | Double-deck heat dissipation packaging structure of closing cap of sorting flip chip |
| CN114023711A (en) * | 2021-11-01 | 2022-02-08 | 上海白泽芯半导体科技有限公司 | Chip packaging structure with high copper column |
| KR20220018842A (en) * | 2020-08-07 | 2022-02-15 | 서울과학기술대학교 산학협력단 | Forming Method of Cu to Cu Flip Chip Interconnection and Cu to Cu Flip Chip Interconnection Thereby |
| CN114464541A (en) * | 2021-12-31 | 2022-05-10 | 通富微电子股份有限公司 | Fan-out type packaging method |
| CN217444385U (en) * | 2022-08-16 | 2022-09-16 | 江苏芯德半导体科技有限公司 | Chip packaging structure |
| CN115249664A (en) * | 2022-06-21 | 2022-10-28 | 星科金朋半导体（江阴）有限公司 | Elastic heat dissipation cover plate for chip packaging, packaging structure and packaging method |
-
2023
- 2023-06-21 CN CN202310735561.5A patent/CN116504646B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5543585A (en) * | 1994-02-02 | 1996-08-06 | International Business Machines Corporation | Direct chip attachment (DCA) with electrically conductive adhesives |
| US20080099925A1 (en) * | 2006-10-31 | 2008-05-01 | Qimonda Ag | Solder pillar bumping and a method of making the same |
| US20130196504A1 (en) * | 2010-11-26 | 2013-08-01 | Tanaka Kikinzoku Kogyo K.K. | Transfer substrate for forming metal wiring and method for forming metal wiring using said transfer substrate |
| US20190189541A1 (en) * | 2017-12-20 | 2019-06-20 | Hefei SMAT Technology Co., LTD | Chip packaging structure and manufacturing method thereof |
| US20200105642A1 (en) * | 2018-09-28 | 2020-04-02 | Xilinx, Inc. | Stacked silicon package assembly having thermal management |
| CN210575914U (en) * | 2019-10-31 | 2020-05-19 | 太极半导体（苏州）有限公司 | Double-deck heat dissipation packaging structure of closing cap of sorting flip chip |
| KR20220018842A (en) * | 2020-08-07 | 2022-02-15 | 서울과학기술대학교 산학협력단 | Forming Method of Cu to Cu Flip Chip Interconnection and Cu to Cu Flip Chip Interconnection Thereby |
| CN114023711A (en) * | 2021-11-01 | 2022-02-08 | 上海白泽芯半导体科技有限公司 | Chip packaging structure with high copper column |
| CN114464541A (en) * | 2021-12-31 | 2022-05-10 | 通富微电子股份有限公司 | Fan-out type packaging method |
| CN115249664A (en) * | 2022-06-21 | 2022-10-28 | 星科金朋半导体（江阴）有限公司 | Elastic heat dissipation cover plate for chip packaging, packaging structure and packaging method |
| CN217444385U (en) * | 2022-08-16 | 2022-09-16 | 江苏芯德半导体科技有限公司 | Chip packaging structure |
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| Publication number | Publication date |
|---|---|
| CN116504646B (en) | 2023-12-15 |
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