CN210224006U - Packaging structure of multi-chip - Google Patents
Packaging structure of multi-chip Download PDFInfo
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- CN210224006U CN210224006U CN201921098926.3U CN201921098926U CN210224006U CN 210224006 U CN210224006 U CN 210224006U CN 201921098926 U CN201921098926 U CN 201921098926U CN 210224006 U CN210224006 U CN 210224006U
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 62
- 239000005022 packaging material Substances 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims description 54
- 239000000758 substrate Substances 0.000 claims description 49
- 230000017525 heat dissipation Effects 0.000 claims description 41
- 229910000679 solder Inorganic materials 0.000 claims description 29
- 239000003292 glue Substances 0.000 claims description 12
- 239000000853 adhesive Substances 0.000 claims description 9
- 230000001070 adhesive effect Effects 0.000 claims description 9
- 150000001875 compounds Chemical class 0.000 claims description 5
- 238000000465 moulding Methods 0.000 claims description 5
- 238000005538 encapsulation Methods 0.000 claims 1
- 238000012536 packaging technology Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 23
- 238000000034 method Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000003698 laser cutting Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 239000006185 dispersion Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001746 injection moulding Methods 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- -1 wherein Chemical compound 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The utility model discloses a packaging structure of multicore piece belongs to semiconductor chip packaging technology field. The fan-out chip packaging unit is characterized in that two or more chips (1) are arranged, only capillary gaps (2) are reserved among the chips (1), capillary plugging parts (3) are arranged on the upper surfaces of the rewiring layers (6) among the chips (1), the capillary plugging parts (3) completely fill the lower parts of the capillary gaps (2), and the plastic packaging material (4) is tightly connected with the capillary plugging parts (3) or the underfill I (5) is in a concave groove at the capillary gaps (2). The utility model provides a solve the packaging structure of the multicore piece of chip fracture, product warpage scheduling problem, improved the yield of product.
Description
Technical Field
The utility model relates to a packaging structure of multicore piece belongs to semiconductor package technical field.
Background
Driven by the small, light and thin electronic products, the market has higher and higher requirements on the functions of a single chip, and when the functions of the chip cannot meet the requirements of customers, a design company needs to redesign the chip, so that the design cost is high, the period is long, continuous optimization is needed, and the method is obviously inconsistent with the information and electronic process which is developed rapidly. Therefore, a multi-chip packaging method is developed. Fan-out (Fan-out) wafer packaging is used as a novel packaging technology, and when the Fan-out wafer packaging is applied to multi-chip packaging, the requirement of a customer on high performance of a product is met, and the aim of miniaturization of an integrated circuit is fulfilled. However, this packaging method also has a certain disadvantage, because the chips are spread flat, in order to achieve the purpose of product miniaturization, the chip spacing needs to be as small as possible, and when the distance between two chips is close enough, the filling adhesive at the bottom of the chip can "climb" to the space between the two chips due to the capillary effect, because the thermal expansion coefficient of the filling adhesive at the bottom is large, the chip can be squeezed by the thermally expanded adhesive in the subsequent process, the problems of chip cracking and product warping occur, and these problems seriously affect the yield of the product.
Disclosure of Invention
An object of the utility model is to overcome the not enough of existence among the prior art, provide a solve the chip fracture that appears in the packaging process and the packaging structure of the multicore piece of product warpage scheduling problem.
The purpose of the utility model is realized like this:
the utility model provides a multi-chip packaging structure, which comprises a fan-out chip packaging unit, a substrate and solder balls, wherein the fan-out chip packaging unit is arranged on the upper surface of the substrate, the solder balls are arranged on the lower surface of the substrate,
the fan-out chip packaging unit is characterized in that two or more chips arranged on the fan-out chip packaging unit are tiled and distributed and are abutted against each other, only capillary gaps are reserved among the chips, the width range of the capillary gaps is 50-300 micrometers, the front surfaces of the chips are inversely arranged on the upper surface of a rewiring layer through metal bumps I, capillary plugging parts are arranged on the upper surfaces of the rewiring layer among the chips, the capillary plugging parts completely fill the lower parts of the capillary gaps, the transverse length of the capillary plugging parts is not less than that of the capillary gaps, the height of the capillary plugging parts is greater than the distance between the lower surfaces of the chips and the upper surface of the rewiring layer, and underfill I is arranged between the chips and;
the fan-out chip packaging unit is fixedly connected with the upper surface of the substrate through the metal bump II; and an underfill II is arranged between the fan-out chip packaging unit and the substrate.
Optionally, the capillary blocking member is ⊥ -shaped in longitudinal section.
Optionally, the wire-bonding pad further comprises a dispensing channel rough surface, the dispensing channel rough surface is arranged on the upper surface of the rewiring layer and covered by the capillary plugging component, and a roughened pattern of the dispensing channel rough surface is in a dot shape or a linear shape.
The utility model also provides a multi-chip packaging structure, which comprises a fan-out chip packaging unit, a substrate and solder balls, wherein the fan-out chip packaging unit is arranged on the upper surface of the substrate, the solder balls are arranged on the lower surface of the substrate,
the fan-out chip packaging unit is characterized in that two or more chips arranged in the fan-out chip packaging unit are distributed in a tiled mode and are close to each other, only capillary gaps are reserved among the chips, the width range of the capillary gaps is 50-300 micrometers, the front faces of the chips are inversely arranged on the upper surface of a rewiring layer through metal bumps I, underfill I is arranged between the chips and the rewiring layer, and the underfill I is in a concave groove at the capillary gaps;
the fan-out chip packaging unit is fixedly connected with the upper surface of the substrate through the metal bumps II; and an underfill II is arranged between the fan-out chip packaging unit and the substrate.
Optionally, the groove is filled with a heat dissipation glue or a molding compound.
Optionally, the chip package structure further comprises a heat dissipation cover, wherein the heat dissipation cover is arranged on the upper surface of the substrate, the heat dissipation cover is in a cap shape and comprises a cap edge and a raised roof, the top space of the heat dissipation cover accommodates the chip fan-out unit, and the back of the chip is connected with the top of the heat dissipation cover through heat dissipation glue; the brim of the heat dissipation cover is fixedly connected with the upper surface of the substrate through an adhesive.
Optionally, the heat dissipation cover is provided with an inner groove on the back surface of the chip.
Optionally, the bottom of the inner groove is arc-shaped, rectangular, trapezoidal or stepped.
Optionally, the coefficient of thermal expansion of the molding compound is much smaller than that of the underfill i.
Advantageous effects
(1) The utility model provides a packaging structure of multicore piece, it sets up capillary shutoff part after, makes the underfill can not "climb" to the capillary clearance in the middle of the two chips, and fills this capillary clearance by the plastic envelope material, because the coefficient of thermal expansion of plastic envelope material is less, so can show and improve phenomenons such as chip fracture and product warpage, improves the yield of product.
(2) The utility model discloses an underfill I is concave type slot design in capillary clearance department, and other low thermal expansion coefficient, the material of low modulus such as plastic-sealed material or heat dissipation glue are filled to concave type slot intussuseption, because the thermal expansion coefficient of plastic-sealed material is a lot less than the thermal expansion coefficient of underfill I, and the cooperation heat dissipation lid promotes the heat dispersion of chip, also can show phenomenons such as the fracture of improving the chip and the warpage of fan-out type chip package unit.
Drawings
Fig. 1 is a schematic cross-sectional view of a first embodiment of a multi-chip package structure according to the present invention;
fig. 2 is a schematic cross-sectional view of a second embodiment of a multi-chip package structure according to the present invention;
FIG. 3 is an enlarged view of a portion of FIG. 2;
fig. 4 is a schematic cross-sectional view of a third embodiment of a multi-chip package structure according to the present invention;
fig. 5 is a schematic cross-sectional view of a fourth embodiment of a multi-chip package structure according to the present invention;
fig. 6 to 9 are partial sectional views of the heat dissipating cover 11 of fig. 5 rotated by 180 degrees;
wherein the content of the first and second substances,
Metal bump I3
Underfill I5
Rewiring layer 6
Metal bump II 7
Underfill II 8
Adhesive 10
A capillary stop 14.
Detailed Description
The following describes in detail embodiments of the present invention with reference to the accompanying drawings. Spatially relative terms (such as "below …", "below", "lower", "above …", "upper", and the like) may be used for ease of illustration to describe one element or component's relationship to another element or component as illustrated in the figures. Spatially relative terms may also encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Example one
The utility model relates to a multi-chip packaging structure, as shown in fig. 1, it includes fan-out type chip package unit, base plate 12 and solder ball 13 thereof, wherein, fan-out type chip package unit sets up the upper surface at base plate 12, solder ball 13 sets up the lower surface at base plate 12. chip 1 that fan-out type chip package unit set up is two or more, the tiling distributes, and hug closely each other, chip 1 forms the capillary clearance 2 that the width scope is 50-300 microns each other, chip 1's front is installed in the upper surface of rewiring layer 6 upside down through its metal lug I3 under it, the upper and lower both ends of metal lug I3 all are equipped with the solder, its upper end is connected with chip 1's front pad, its lower extreme is connected with rewiring layer 6's upper surface pad, chip 1 sets up capillary shutoff part 2 in rewiring layer 6's upper surface each other, its material is mainly resin and silica, wherein, silica accounts for 50-90%, and has extremely low mobility before not solidifying, shutoff part 2 can fill the lower part of capillary clearance 2 completely, after the solidification, the section of shutoff part 14 is ⊥, its horizontal length is greater than the horizontal capillary clearance of the horizontal, the capillary clearance is greater than the capillary clearance of the horizontal point form again, the capillary clearance of the wiring layer 6 again, the capillary clearance is not set up again, the capillary clearance is not more than the capillary clearance, the capillary clearance.
Set up underfill I5 between chip 1 and rewiring layer 6, its material is underfill, and underfill I5 has further consolidated the connection between chip 1 and rewiring layer 6. Due to the presence of the capillary stop 2, the underfill i 5 cannot enter the capillary gap 2 between the chips 1. The plastic package material 4 covers all the chips 1 on the rewiring metal layer 6, and the plastic package material 4 fills the capillary gap 2 downwards under the action of vacuum negative pressure and injection molding pressure in the plastic package process so as to be tightly connected with the capillary plugging part 14. The lower surface of the fan-out chip packaging unit, namely the lower surface of the rewiring layer 6, is provided with a metal bump II 7, and the fan-out chip packaging unit is fixedly connected with the upper surface of the substrate 12 through the metal bump II 7. And the upper end and the lower end of the metal lug II 7 are respectively provided with solder, the upper end of the metal lug II is connected with a lower surface bonding pad of the chip fan-out unit, and the lower end of the metal lug II is connected with an upper surface bonding pad of the substrate 12. And the underfill II 8 is arranged between the metal bump II 7 and the upper surface of the substrate 12, so that the connection strength of the chip fan-out unit and the substrate 12 is further enhanced. The lower surface of the substrate 12 is provided with solder balls 13.
The utility model discloses a set up capillary shutoff part 14, underfill I5 can not "climb" to the capillary clearance 2 in the middle of the chip 1, and fill this capillary clearance 2 by plastic package material 4, because the coefficient of thermal expansion of plastic package material 4 is little a lot than underfill I5's coefficient of thermal expansion (the coefficient of thermal expansion of plastic package material 4 is 5-10 ppm/° C, underfill I5's coefficient of thermal expansion is 30-50ppm/° C), so can show phenomenons such as the fracture of improving chip 1 and fan-out type chip package unit's warpage.
Example two
The utility model relates to a packaging structure of multicore piece, as shown in FIG. 2 and FIG. 3, it includes fan-out type chip package unit, base plate 12 and solder ball 13, and wherein, fan-out type chip package unit sets up the upper surface at base plate 12, solder ball 13 sets up the lower surface at base plate 12. The fan-out chip packaging unit is provided with two or more chips 1 which are distributed in a tiled mode and are close to each other, and the chips 1 form a capillary gap 2 with the width ranging from 50 microns to 300 microns. The front surface of the chip 1 is flip-chip mounted on the upper surface of the redistribution layer 6 through the metal bump i 3 thereunder. The upper end and the lower end of the metal lug I3 are both provided with solder, the upper end of the metal lug I3 is connected with a front surface bonding pad of the chip 1, and the lower end of the metal lug I3 is connected with an upper surface bonding pad of the rewiring layer 6.
Set up underfill I5 between chip 1 and rewiring layer 6, its material is underfill, and underfill I5 has further consolidated the connection between chip 1 and rewiring layer 6. By means of laser cutting, the underfill i 5 is in the form of a concave groove at the capillary gap 2, as shown in fig. 3.
The plastic package material 4 covers all the chips 1 on the rewiring metal layer 6, and exposes the back surfaces of the chips 1 and the concave grooves. The lower surface of the fan-out chip packaging unit, namely the lower surface of the rewiring layer 6, is provided with a metal bump II 7, and the fan-out chip packaging unit is fixedly connected with the upper surface of the substrate 12 through the metal bump II 7. And the upper end and the lower end of the metal lug II 7 are respectively provided with solder, the upper end of the metal lug II is connected with a lower surface bonding pad of the chip fan-out unit, and the lower end of the metal lug II is connected with an upper surface bonding pad of the substrate 12. And the underfill II 8 is arranged between the metal bump II 7 and the upper surface of the substrate 12, so that the connection strength of the chip fan-out unit and the substrate 12 is further enhanced. The lower surface of the substrate 12 is provided with solder balls 13.
EXAMPLE III
The utility model relates to a packaging structure of multicore piece, as shown in FIG. 2 and FIG. 3, it includes fan-out type chip package unit, base plate 12 and solder ball 13, and wherein, fan-out type chip package unit sets up the upper surface at base plate 12, solder ball 13 sets up the lower surface at base plate 12. The fan-out chip packaging unit is provided with two or more chips 1 which are distributed in a tiled mode and are close to each other, and the chips 1 form a capillary gap 2 with the width ranging from 50 microns to 300 microns. The front surface of the chip 1 is flip-chip mounted on the upper surface of the redistribution layer 6 through the metal bump i 3 thereunder. The upper end and the lower end of the metal lug I3 are both provided with solder, the upper end of the metal lug I3 is connected with a front surface bonding pad of the chip 1, and the lower end of the metal lug I3 is connected with an upper surface bonding pad of the rewiring layer 6.
Set up underfill I5 between chip 1 and rewiring layer 6, its material is underfill, and underfill I5 has further consolidated the connection between chip 1 and rewiring layer 6. By means of laser cutting, the underfill i 5 is in the form of a concave groove at the capillary gap 2, as shown in fig. 3.
The plastic package material 4 covers all the chips 1 on the rewiring metal layer 6, and exposes the back surfaces of the chips 1 and the concave grooves. The lower surface of the fan-out chip packaging unit, namely the lower surface of the rewiring layer 6, is provided with a metal bump II 7, and the fan-out chip packaging unit is fixedly connected with the upper surface of the substrate 12 through the metal bump II 7. And the upper end and the lower end of the metal lug II 7 are respectively provided with solder, the upper end of the metal lug II is connected with a lower surface bonding pad of the chip fan-out unit, and the lower end of the metal lug II is connected with an upper surface bonding pad of the substrate 12. And the underfill II 8 is arranged between the metal bump II 7 and the upper surface of the substrate 12, so that the connection strength of the chip fan-out unit and the substrate 12 is further enhanced. The lower surface of the substrate 12 is provided with solder balls 13.
The upper surface of the substrate 12 may be further provided with a heat dissipation cover 11, and the heat dissipation cover 11 is in a cap shape and includes a brim and a raised roof. The cap top space of the heat dissipation cover 11 accommodates the fan-out chip packaging unit, and the back of the chip 1 is connected with the cap top of the heat dissipation cover 11 through heat dissipation glue 9, wherein the heat dissipation glue only covers the surfaces of the chip and the plastic packaging material, and no heat dissipation glue is arranged in the groove; the brim of the heat-radiating cover 11 is fixedly attached to the upper surface of the substrate 12 by an adhesive 10, as shown in fig. 4.
Example four
The utility model relates to a packaging structure of multicore piece, as shown in FIG. 2 and FIG. 3, it includes fan-out type chip package unit, base plate 12 and solder ball 13, and wherein, fan-out type chip package unit sets up the upper surface at base plate 12, solder ball 13 sets up the lower surface at base plate 12. The fan-out chip packaging unit is provided with two or more chips 1 which are distributed in a tiled mode and are close to each other, and the chips 1 form a capillary gap 2 with the width ranging from 50 microns to 300 microns. The front surface of the chip 1 is flip-chip mounted on the upper surface of the redistribution layer 6 through the metal bump i 3 thereunder. The upper end and the lower end of the metal lug I3 are both provided with solder, the upper end of the metal lug I3 is connected with a front surface bonding pad of the chip 1, and the lower end of the metal lug I3 is connected with an upper surface bonding pad of the rewiring layer 6.
Set up underfill I5 between chip 1 and rewiring layer 6, its material is underfill, and underfill I5 has further consolidated the connection between chip 1 and rewiring layer 6. By means of laser cutting, the underfill i 5 is in the form of a concave groove at the capillary gap 2, as shown in fig. 3.
The molding compound 4 covers all the chips 1 on the rewiring metal layer 6 and exposes the back surfaces of the chips 1. And in the plastic packaging process, the plastic packaging material 4 is downwards filled into the concave groove under the action of vacuum negative pressure and injection molding pressure, so that the plastic packaging material is tightly connected with the underfill I5. The lower surface of the fan-out chip packaging unit, namely the lower surface of the rewiring layer 6, is provided with a metal bump II 7, and the fan-out chip packaging unit is fixedly connected with the upper surface of the substrate 12 through the metal bump II 7. And the upper end and the lower end of the metal lug II 7 are respectively provided with solder, the upper end of the metal lug II is connected with a lower surface bonding pad of the chip fan-out unit, and the lower end of the metal lug II is connected with an upper surface bonding pad of the substrate 12. And the underfill II 8 is arranged between the metal bump II 7 and the upper surface of the substrate 12, so that the connection strength of the chip fan-out unit and the substrate 12 is further enhanced. The lower surface of the substrate 12 is provided with solder balls 13.
The upper surface of the substrate 12 may be further provided with a heat dissipation cover 11, and the heat dissipation cover 11 is in a cap shape and includes a brim and a raised roof. The cap top space of the heat dissipation cover 11 accommodates the fan-out chip package unit, and the back of the chip 1 is connected with the cap top of the heat dissipation cover 11 through the heat dissipation glue 9, and the concave groove can also be filled with the heat dissipation glue or other materials with low thermal expansion coefficient and low modulus. The brim of the heat-radiating cover 11 is fixedly attached to the upper surface of the substrate 12 by an adhesive 10, as shown in fig. 5.
The heat dissipation cover 11 has an inner groove formed in the back surface of the chip 1, and the bottom of the inner groove is arc-shaped, rectangular, trapezoidal or stepped, as shown in fig. 6 to 9, which is a partial cross-sectional view of the heat dissipation cover 11 rotated by 180 degrees, so that the contact area between the heat dissipation glue 9 and the heat dissipation cover 11 can be effectively increased, and the heat dissipation performance of the chip 1 can be improved.
The utility model discloses an underfill I5 is concave type slot design in 2 departments of capillary gap, other low thermal expansion coefficient such as plastic-sealed material 4 or heat dissipation glue are filled to concave type slot, the material of low modulus, because the thermal expansion coefficient of plastic-sealed material 4 is a lot less than underfill I5's thermal expansion coefficient (plastic-sealed material 4's thermal expansion coefficient is 5-10 ppm/° C, underfill I5's thermal expansion coefficient is 30-50ppm/° C), and the cooperation cooling cap, promote chip 1's heat dispersion, the homoenergetic is showing phenomenons such as the fracture of improving chip 1 and fan-out type chip package unit's warpage.
The above-mentioned embodiments further describe the objects, technical solutions and advantages of the present invention in detail, it should be understood that the above-mentioned embodiments are only specific embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A multi-chip packaging structure comprises a fan-out chip packaging unit, a substrate (12) and solder balls (13) thereof, wherein the fan-out chip packaging unit is arranged on the upper surface of the substrate (12), the solder balls (13) are arranged on the lower surface of the substrate (12),
the fan-out chip packaging unit is characterized in that two or more chips (1) arranged in the fan-out chip packaging unit are distributed in a tiled mode and are abutted against each other, only capillary gaps (2) are reserved among the chips (1), the width range of the capillary gaps (2) is 50-300 micrometers, the front surfaces of the chips (1) are inversely installed on the upper surface of a rewiring layer (6) through metal bumps I (3), capillary plugging parts (14) are arranged on the upper surface of the rewiring layer (6) among the chips (1), the capillary plugging parts (14) completely fill the lower parts of the capillary gaps (2), the transverse length of the capillary plugging parts is not smaller than that of the capillary gaps (2), the height of the capillary plugging parts is larger than the distance between the lower surface of the chips (1) and the upper surface of the rewiring layer (6), and underfill I (5) is arranged between the chips (1) and the rewiring layer (6);
the fan-out chip packaging structure is characterized by further comprising a plastic packaging material (4), wherein the plastic packaging material (4) covers all chips (1) on the rewiring layer (6) and fills the capillary gaps (2), the plastic packaging material (4) is tightly connected with the capillary plugging parts (14), metal bumps II (7) are arranged on the lower surface of the fan-out chip packaging unit, namely the lower surface of the rewiring layer (6), and the fan-out chip packaging unit is fixedly connected with the upper surface of the substrate (12) through the metal bumps II (7); and an underfill II (8) is arranged between the fan-out type chip packaging unit and the substrate (12).
2. Packaging according to claim 1, characterized in that the capillary plug (14) is ⊥ -shaped in longitudinal section.
3. The package structure according to claim 1, further comprising a dispensing track rough surface, wherein the dispensing track rough surface is disposed on the upper surface of the redistribution layer (6) and covered by the capillary plugging member (14), and the roughened pattern is in a dot or line shape.
4. A multi-chip packaging structure comprises a fan-out chip packaging unit, a substrate (12) and solder balls (13) thereof, wherein the fan-out chip packaging unit is arranged on the upper surface of the substrate (12), the solder balls (13) are arranged on the lower surface of the substrate (12),
the fan-out chip packaging unit is characterized in that two or more chips (1) arranged in the fan-out chip packaging unit are distributed in a tiled mode and are abutted against each other, only capillary gaps (2) are reserved among the chips (1), the width range of the capillary gaps (2) is 50-300 micrometers, the front surfaces of the chips (1) are inversely arranged on the upper surface of a rewiring layer (6) through metal bumps I (3), underfill I (5) is arranged between the chips (1) and the rewiring layer (6), and the underfill I (5) is in a concave groove at the capillary gaps (2);
the packaging structure is characterized by further comprising a plastic packaging material (4), wherein the plastic packaging material (4) covers all the chips (1) on the rewiring layer (6) and exposes the back surfaces of the chips (1), the lower surface of the fan-out chip packaging unit, namely the lower surface of the rewiring layer (6), is provided with a metal bump II (7), and the fan-out chip packaging unit is fixedly connected with the upper surface of the substrate (12) through the metal bump II (7); and an underfill II (8) is arranged between the fan-out type chip packaging unit and the substrate (12).
5. The package structure according to claim 4, wherein the trench is filled with a heat dissipation glue (9) or a molding compound (4).
6. The package structure according to claim 1 or 4, further comprising a heat dissipation cover (11), wherein the heat dissipation cover (11) is disposed on the upper surface of the substrate (12), the heat dissipation cover (11) is in a cap shape and comprises a brim and a raised roof, and a top cap space of the heat dissipation cover (11) accommodates the chip fan-out unit and connects the back surface of the chip (1) with the top cap of the heat dissipation cover (11) through a heat dissipation adhesive (9); the brim of the heat dissipation cover (11) is fixedly connected with the upper surface of the substrate (12) through an adhesive (10).
7. The package structure according to claim 6, wherein the heat dissipation cover (11) is provided with an inner recess on the back side of the chip (1).
8. The package structure of claim 7, wherein the bottom of the inner recess is curved, rectangular, trapezoidal, or stepped.
9. The encapsulation structure according to claim 1 or 4, characterized in that the coefficient of thermal expansion of the molding compound (4) is much smaller than the coefficient of thermal expansion of the underfill I (5).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921098926.3U CN210224006U (en) | 2019-07-15 | 2019-07-15 | Packaging structure of multi-chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921098926.3U CN210224006U (en) | 2019-07-15 | 2019-07-15 | Packaging structure of multi-chip |
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| Publication Number | Publication Date |
|---|---|
| CN210224006U true CN210224006U (en) | 2020-03-31 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201921098926.3U Withdrawn - After Issue CN210224006U (en) | 2019-07-15 | 2019-07-15 | Packaging structure of multi-chip |
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| CN (1) | CN210224006U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110349945A (en) * | 2019-07-15 | 2019-10-18 | 星科金朋半导体（江阴）有限公司 | A kind of encapsulating structure and its packaging method of multi-chip |
| CN114823550A (en) * | 2022-06-27 | 2022-07-29 | 北京升宇科技有限公司 | Chip packaging structure and packaging method suitable for batch production |
-
2019
- 2019-07-15 CN CN201921098926.3U patent/CN210224006U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110349945A (en) * | 2019-07-15 | 2019-10-18 | 星科金朋半导体（江阴）有限公司 | A kind of encapsulating structure and its packaging method of multi-chip |
| CN110349945B (en) * | 2019-07-15 | 2024-05-24 | 星科金朋半导体（江阴）有限公司 | Multi-chip packaging structure and packaging method thereof |
| CN114823550A (en) * | 2022-06-27 | 2022-07-29 | 北京升宇科技有限公司 | Chip packaging structure and packaging method suitable for batch production |
| CN114823550B (en) * | 2022-06-27 | 2022-11-11 | 北京升宇科技有限公司 | Chip packaging structure and packaging method suitable for batch production |
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