JP2012109328A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2012109328A
JP2012109328A JP2010255522A JP2010255522A JP2012109328A JP 2012109328 A JP2012109328 A JP 2012109328A JP 2010255522 A JP2010255522 A JP 2010255522A JP 2010255522 A JP2010255522 A JP 2010255522A JP 2012109328 A JP2012109328 A JP 2012109328A
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semiconductor chip
semiconductor device
die pad
chip
recess
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Kimihito Kuwabara
公仁 桑原
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Panasonic Corp
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Panasonic Corp
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that efficiently releases heat from a semiconductor chip to a die pad.SOLUTION: A semiconductor device comprises a lead frame 102 including a die pad 121, and a semiconductor chip 101 bonded onto a chip mounting region of the die pad 121 by a die-bonding material 132. The chip mounting region is a recess 124 including first portions 124a fitted onto the semiconductor chip 101 with a space and second portions 124b with a larger space between the wall surfaces of the recess 124 and the side surfaces of the semiconductor chip 101 than the space of the first portions 124a. The die-bonding material 132 fills the space between the side surfaces of the semiconductor chip 101 and the wall surfaces of the recess 124.

Description

本発明は、半導体装置に関し、特にリードフレームを用いた半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device using a lead frame.

従来の半導体装置は、半導体チップを金属製のダイパッドに接合し、半導体チップの電極端子とリードとを金属ワイヤを用いて接続した構造となっている。半導体チップをダイパッドにダイボンド材を用いて接合することにより、半導体チップから発生する熱を、ダイパッドを介して放熱することが可能となる。   A conventional semiconductor device has a structure in which a semiconductor chip is bonded to a metal die pad, and electrode terminals and leads of the semiconductor chip are connected using a metal wire. By bonding the semiconductor chip to the die pad using a die bond material, it is possible to dissipate heat generated from the semiconductor chip through the die pad.

近年、半導体チップの高集積化に伴い、半導体チップの発熱量が増大している。一般に、半導体チップは、その底面がダイボンド材を介してダイパッドと接合されている。このため、半導体チップにおいて発生する熱は、その底面からダイパッドに伝わり、放熱される。一方、半導体チップの微細化も進められており、半導体チップの底面積は小さくなる傾向にある。このため、半導体チップの底面からダイパッドへ放熱することが次第に困難となってきている。   In recent years, the amount of heat generated by a semiconductor chip is increasing with the high integration of the semiconductor chip. Generally, the bottom surface of a semiconductor chip is bonded to a die pad via a die bond material. For this reason, the heat generated in the semiconductor chip is transferred from the bottom surface to the die pad and radiated. On the other hand, miniaturization of semiconductor chips has been promoted, and the bottom area of the semiconductor chips tends to be small. For this reason, it has become increasingly difficult to dissipate heat from the bottom surface of the semiconductor chip to the die pad.

半導体チップからダイパッドへ効率良く放熱するために、半導体チップの底面からだけでなく、側面からもダイパッドへ熱を伝えられるようにすることが考えられる。具体的には、ダイパッドに凹部を設け、この凹部に半導体チップをはめ込むことが考えられる。例えば、特許文献１にはダイパッドに浅い凹部を有するリードフレームが開示されている。しかし、この凹部は半導体チップの位置決め用であり、その深さは半導体チップの厚さの５分の１程度である。また、半導体チップの側面と凹部の壁面とは接合されていない。このため、半導体チップからダイパッドへの熱の伝達にはほとんど寄与しない。   In order to efficiently dissipate heat from the semiconductor chip to the die pad, it may be possible to transfer heat to the die pad not only from the bottom surface of the semiconductor chip but also from the side surface. Specifically, it is conceivable to provide a recess in the die pad and fit a semiconductor chip in the recess. For example, Patent Document 1 discloses a lead frame having a shallow recess in a die pad. However, this recess is for positioning the semiconductor chip, and its depth is about one fifth of the thickness of the semiconductor chip. Further, the side surface of the semiconductor chip and the wall surface of the recess are not joined. For this reason, it hardly contributes to the transfer of heat from the semiconductor chip to the die pad.

また、特許文献２には、半導体チップを取り囲むような側壁部を有する深皿形状のダイパッドを有するリードフレームが開示されている。しかし、このリードフレームは半導体チップの吸湿を低減することを目的としており、半導体チップの側面と凹部の側壁との間には封止樹脂が充填されている。このため、半導体チップの側面からダイパッドへの熱の伝達効率は非常に低い。   Patent Document 2 discloses a lead frame having a deep dish-shaped die pad having a side wall portion surrounding a semiconductor chip. However, this lead frame is intended to reduce moisture absorption of the semiconductor chip, and a sealing resin is filled between the side surface of the semiconductor chip and the side wall of the recess. For this reason, the heat transfer efficiency from the side surface of the semiconductor chip to the die pad is very low.

特許文献３には、上部が広がった傾斜した壁面を有する凹部の底面に半導体チップを接合した例が開示されている。この場合には、半導体チップが発光ダイオードであり、凹部は発光ダイオードからの光を効率良く外部に取り出すために設けられている。このため、半導体チップの側面と凹部の壁面との間隔が大きく、さらに半導体チップの側面と凹部の壁面との間には樹脂又はガラス等が充填されている。従って、半導体チップの側面からの放熱にはほとんど寄与しない。   Patent Document 3 discloses an example in which a semiconductor chip is bonded to the bottom surface of a recess having an inclined wall surface with an upper portion spread. In this case, the semiconductor chip is a light emitting diode, and the recess is provided in order to efficiently extract light from the light emitting diode to the outside. For this reason, the distance between the side surface of the semiconductor chip and the wall surface of the recess is large, and the space between the side surface of the semiconductor chip and the wall surface of the recess is filled with resin or glass. Therefore, it hardly contributes to heat radiation from the side surface of the semiconductor chip.

特許文献４には、凹部内に半導体チップを配置し、半導体チップの側面と凹部の壁面との間に伝熱性物質を充填した半導体装置が開示されている。   Patent Document 4 discloses a semiconductor device in which a semiconductor chip is disposed in a recess, and a heat transfer material is filled between a side surface of the semiconductor chip and a wall surface of the recess.

特開平５−４７８１０号公報JP-A-5-47810 特開平５−２９５２９号公報Japanese Patent Laid-Open No. 5-29529 特開２００１−３６１４５号公報JP 2001-36145 A 実開平５−７３９６４号公報Japanese Utility Model Publication No. 5-73964

しかしながら、前記従来の半導体装置には、以下のような問題がある。半導体チップの底面及び側面と、凹部の底面及び壁面との間に充填する伝熱性物質には、フィラーを混合したペースト状のダイボンド材又はフィルム状のダイボンド材等を使用する必要がある。これらのダイボンド材の熱伝導率は、０．２Ｗ／ｍ・Ｋ〜数Ｗ／ｍ・Ｋ程度でしかない。これは半導体チップの基板であるシリコン（約１４８Ｗ／ｍ・Ｋ）及びダイパッドである銅合金（約２００Ｗ／ｍ・Ｋ〜３６０Ｗ／ｍ・Ｋ）と比べて、桁違いに低い。また、金属はんだ（数十Ｗ／ｍ・Ｋ）と比べても非常に低い。さらに、伝熱性物質を半導体チップと凹部との間に均一に充填するためには、半導体チップと凹部との間に十分な隙間を確保しなければならない。このため、半導体チップからダイパッドへの十分な熱の伝達ができないという問題がある。   However, the conventional semiconductor device has the following problems. It is necessary to use a paste-like die-bonding material or a film-like die-bonding material in which a filler is mixed as the heat transfer material filled between the bottom surface and side surface of the semiconductor chip and the bottom surface and wall surface of the recess. The thermal conductivity of these die bond materials is only about 0.2 W / m · K to several W / m · K. This is an order of magnitude lower than silicon (about 148 W / m · K) which is a substrate of a semiconductor chip and copper alloy (about 200 W / m · K to 360 W / m · K) which is a die pad. Moreover, it is very low compared with metal solder (several tens of W / m · K). Furthermore, in order to uniformly fill the heat conductive material between the semiconductor chip and the recess, a sufficient gap must be ensured between the semiconductor chip and the recess. For this reason, there is a problem that sufficient heat cannot be transferred from the semiconductor chip to the die pad.

本発明は、前記の問題を解決し、半導体チップからダイパッドへ効率良く放熱する半導体装置を実現できるようにすることを目的とする。   An object of the present invention is to solve the above problems and to realize a semiconductor device that efficiently dissipates heat from a semiconductor chip to a die pad.

前記の目的を達成するため、本発明は半導体装置を、ダイパッドに形成された余剰のダイボンド材を流し込む部分を有する凹部にダイボンド材を介して半導体チップを接合する構成とする。   In order to achieve the above object, according to the present invention, a semiconductor device is configured such that a semiconductor chip is bonded to a recess having a portion into which an excessive die bond material formed on a die pad is poured, via the die bond material.

本発明に係る半導体装置は、ダイパッドを含むリードフレームと、ダイパッドのチップ搭載領域にダイボンド材により接合された半導体チップとを備え、チップ搭載領域は、半導体チップに間隔をおいて外嵌する第１の部分と、第１の部分よりもその壁面と半導体チップの側面との間隔が大きい第２の部分とを含む凹部であり、半導体チップの側面と凹部の壁面との間にはダイボンド材が充填されている。   A semiconductor device according to the present invention includes a lead frame including a die pad, and a semiconductor chip bonded to a chip mounting area of the die pad by a die bonding material, and the chip mounting area is externally fitted to the semiconductor chip at an interval. And a second portion having a larger distance between the wall surface and the side surface of the semiconductor chip than the first portion, and a die bond material is filled between the side surface of the semiconductor chip and the wall surface of the recess. Has been.

本発明の半導体装置は、チップ搭載領域が、半導体チップに間隔をおいて外嵌する第１の部分と、第１の部分よりもその壁面と半導体チップの側面との間隔が大きい第２の部分とを含む凹部である。このため、半導体チップをチップ搭載部に接合する際に、余剰のダイボンド材は第２の部分に流れ込む。従って、第１の部分における半導体チップの側面と凹部の壁面との間隔を小さくしても、半導体チップの側面と凹部の壁面との間に均一にダイボンド材が充填された状態で接合される。その結果、半導体チップの側面からダイパッドへ効率良く熱を伝えることができ、放熱性に優れた半導体装置を実現することができる。   In the semiconductor device of the present invention, the chip mounting region has a first part that is fitted over the semiconductor chip with a space therebetween, and a second part in which the space between the wall surface and the side surface of the semiconductor chip is larger than the first part. It is a recessed part containing these. For this reason, when the semiconductor chip is bonded to the chip mounting portion, excess die bond material flows into the second portion. Therefore, even if the distance between the side surface of the semiconductor chip and the wall surface of the recess in the first portion is reduced, the bonding is performed in a state where the die bond material is uniformly filled between the side surface of the semiconductor chip and the wall surface of the recess. As a result, heat can be efficiently transferred from the side surface of the semiconductor chip to the die pad, and a semiconductor device having excellent heat dissipation can be realized.

本発明の半導体装置において、半導体チップは、平面方形状であり、第２の部分は、半導体チップの角部と対応する部分に形成されていてもよい。   In the semiconductor device of the present invention, the semiconductor chip may have a planar rectangular shape, and the second portion may be formed at a portion corresponding to a corner portion of the semiconductor chip.

本発明の半導体装置において、凹部は、半導体チップの厚さの２分の１以上且つ半導体チップの厚さ未満の深さとすればよい。   In the semiconductor device of the present invention, the recess may have a depth that is at least one half of the thickness of the semiconductor chip and less than the thickness of the semiconductor chip.

本発明の半導体装置において、第１の部分における半導体チップの側面と凹部の壁面との間隔は、５μｍ以上且つ２００μｍ以下とすればよい。   In the semiconductor device of the present invention, the distance between the side surface of the semiconductor chip and the wall surface of the recess in the first portion may be 5 μm or more and 200 μm or less.

本発明の半導体装置において、半導体チップは、平面方形状であり、半導体チップの厚さは、長辺の長さの２０分の１以上とすればよい。   In the semiconductor device of the present invention, the semiconductor chip has a planar rectangular shape, and the thickness of the semiconductor chip may be at least 1/20 of the length of the long side.

本発明の半導体装置において、ダイパッドにおける凹部が形成された部分の厚さは、ダイパッドの他の部分における厚さと等しくてもよい。   In the semiconductor device of the present invention, the thickness of the portion of the die pad where the recess is formed may be equal to the thickness of the other portion of the die pad.

本発明の半導体装置において、凹部は、半切断プレス加工により形成してもよい。   In the semiconductor device of the present invention, the recess may be formed by half-cut pressing.

本発明の半導体装置において、ダイパッドは、その上面が凹部の側から外縁部に向かって次第に低くなるように傾斜していてもよい。   In the semiconductor device of the present invention, the die pad may be inclined so that the upper surface thereof gradually decreases from the concave side toward the outer edge.

本発明の半導体装置において、ダイパッドは、底板と底板の上に接合された枠体とを有していてもよい。   In the semiconductor device of the present invention, the die pad may have a bottom plate and a frame joined on the bottom plate.

本発明の半導体装置において、枠体は、その高さが凹部の側から外縁部に向かって次第に低くなるように傾斜していてもよい。   In the semiconductor device of the present invention, the frame body may be inclined so that its height gradually decreases from the recess side toward the outer edge portion.

本発明の半導体装置は、半導体チップ及びリードフレームを封止する絶縁モールドをさらに備え、リードフレームは、絶縁モールドの外側に突出した複数のリードを有していてもよい。   The semiconductor device of the present invention may further include an insulating mold that seals the semiconductor chip and the lead frame, and the lead frame may have a plurality of leads protruding outside the insulating mold.

本発明の半導体装置において、複数のリードの１つは、ダイパッドと一体であってもよい。   In the semiconductor device of the present invention, one of the plurality of leads may be integrated with the die pad.

本発明の半導体装置において、半導体チップはチップ端子を有し、チップ端子とリードとはバンプにより接続されていてもよい。   In the semiconductor device of the present invention, the semiconductor chip may have a chip terminal, and the chip terminal and the lead may be connected by a bump.

本発明の半導体装置において、ダイパッドは、実装基板に実装された際に、半導体チップを搭載した面と反対側の面が実装基板側となるように、リードと接続されていてもよい。   In the semiconductor device of the present invention, the die pad may be connected to the lead so that the surface opposite to the surface on which the semiconductor chip is mounted becomes the mounting substrate side when mounted on the mounting substrate.

本発明の半導体装置において、ダイパッドは、実装基板に実装された際に、半導体チップを搭載した面が実装基板側となるように、リードと接続されていてもよい。   In the semiconductor device of the present invention, the die pad may be connected to the lead so that the surface on which the semiconductor chip is mounted is on the mounting substrate side when mounted on the mounting substrate.

本発明の半導体装置において、ダイパッドは、半導体チップを搭載した面と反対側の面が絶縁モールドから露出していてもよい。   In the semiconductor device of the present invention, the surface of the die pad opposite to the surface on which the semiconductor chip is mounted may be exposed from the insulating mold.

本発明の半導体装置において、リードは、絶縁モールドに覆われたインナーリード部と、絶縁モールドから突出したアウターモールド部とを有し、インナーリード部の厚さは、アウターリード部側の部分よりも、半導体チップ側の部分において薄くてもよい。   In the semiconductor device of the present invention, the lead has an inner lead portion covered with an insulating mold and an outer mold portion protruding from the insulating mold, and the thickness of the inner lead portion is larger than that of the portion on the outer lead portion side. The semiconductor chip side portion may be thin.

本発明の半導体装置において、インナーリード部の厚さは、アウターリード部側から半導体チップ側に向かって連続的に薄くなっていてもよい。   In the semiconductor device of the present invention, the thickness of the inner lead portion may be continuously reduced from the outer lead portion side toward the semiconductor chip side.

本発明の半導体装置において、半導体チップは、発光ダイオードであってもよい。   In the semiconductor device of the present invention, the semiconductor chip may be a light emitting diode.

本発明に係る半導体装置によれば、半導体チップからダイパッドへ効率良く放熱する半導体装置を実現できる。   The semiconductor device according to the present invention can realize a semiconductor device that efficiently dissipates heat from a semiconductor chip to a die pad.

(ａ)及び（ｂ）は一実施形態に係る半導体装置を示し、(ａ)は平面図であり、（ｂ）は(ａ)のＩｂ−Ｉｂ線における断面図である。(a) And (b) shows the semiconductor device which concerns on one Embodiment, (a) is a top view, (b) is sectional drawing in the Ib-Ib line | wire of (a). 一実施形態に係る半導体装置の変形例を示す平面図である。It is a top view which shows the modification of the semiconductor device which concerns on one Embodiment. 一実施形態に係る半導体装置の変形例を示す平面図である。It is a top view which shows the modification of the semiconductor device which concerns on one Embodiment. 一実施形態に係る半導体装置の変形例を示す断面図である。It is sectional drawing which shows the modification of the semiconductor device which concerns on one Embodiment. 一実施形態に係る半導体装置の変形例を示す断面図である。It is sectional drawing which shows the modification of the semiconductor device which concerns on one Embodiment. 一実施形態に係る半導体装置の変形例を示す断面図である。It is sectional drawing which shows the modification of the semiconductor device which concerns on one Embodiment. 一実施形態に係る半導体装置の変形例を示す断面図である。It is sectional drawing which shows the modification of the semiconductor device which concerns on one Embodiment. 一実施形態に係る半導体装置の変形例を示す断面図である。It is sectional drawing which shows the modification of the semiconductor device which concerns on one Embodiment. 一実施形態に係る半導体装置の変形例を示す断面図である。It is sectional drawing which shows the modification of the semiconductor device which concerns on one Embodiment. 一実施形態に係る半導体装置の変形例を示す断面図である。It is sectional drawing which shows the modification of the semiconductor device which concerns on one Embodiment. 一実施形態に係る半導体装置の変形例を示す断面図である。It is sectional drawing which shows the modification of the semiconductor device which concerns on one Embodiment. 一実施形態に係る半導体装置の変形例を示す断面図である。It is sectional drawing which shows the modification of the semiconductor device which concerns on one Embodiment. 一実施形態に係る半導体装置の変形例を示す断面図である。It is sectional drawing which shows the modification of the semiconductor device which concerns on one Embodiment. 一実施形態に係る半導体装置の変形例を示す断面図である。It is sectional drawing which shows the modification of the semiconductor device which concerns on one Embodiment. 一実施形態に係る半導体装置の変形例を示す断面図である。It is sectional drawing which shows the modification of the semiconductor device which concerns on one Embodiment. 一実施形態に係る半導体装置の変形例を示す断面図である。It is sectional drawing which shows the modification of the semiconductor device which concerns on one Embodiment. 一実施形態に係る半導体装置の変形例を示す断面図である。It is sectional drawing which shows the modification of the semiconductor device which concerns on one Embodiment.

図１（ａ）及び（ｂ）に示すように、一実施形態に係る半導体装置は、ＱＦＰ（Quad Flat Package）タイプの半導体装置であり、半導体チップ１０１が、リードフレーム１０２に搭載されている。リードフレーム１０２は、半導体チップ１０１を搭載するダイパッド１２１と、半導体チップ１０１のチップ端子１１１とワイヤ１３１により接続されたリード１２２とを有している。半導体チップ１０１及びリードフレーム１０２は、樹脂からなる絶縁モールド１３３により封止されている。但し、図１(ａ)においては、ワイヤ１３１及び絶縁モールド１３３の図示を省略している。リード１２２は、絶縁モールド１３３に覆われたインナーリード部１２２Ａと、絶縁モールド１３３の外側に突出したアウターリード部１２２Ｂとを有している。半導体チップ１０１は、ダイパッド１２１のチップ搭載領域にダイボンド材１３２により接合されている。チップ搭載領域は、ダイパッド１２１に形成された凹部１２４である。凹部１２４は、半導体チップ１０１に間隔をおいて外嵌した第１の部分１２４ａと、半導体チップ１０１の角部と対応する部分に設けられた第２の部分１２４ｂとを含む。第２の部分１２４ｂは、半導体チップ１０１の側面と凹部の壁面との間隔が第１の部分１２４ａよりも大きい。   As shown in FIGS. 1A and 1B, the semiconductor device according to an embodiment is a QFP (Quad Flat Package) type semiconductor device, and a semiconductor chip 101 is mounted on a lead frame 102. The lead frame 102 has a die pad 121 on which the semiconductor chip 101 is mounted, and leads 122 connected to the chip terminals 111 of the semiconductor chip 101 by wires 131. The semiconductor chip 101 and the lead frame 102 are sealed with an insulating mold 133 made of resin. However, illustration of the wire 131 and the insulating mold 133 is omitted in FIG. The lead 122 has an inner lead part 122 </ b> A covered with the insulating mold 133 and an outer lead part 122 </ b> B protruding outside the insulating mold 133. The semiconductor chip 101 is bonded to the chip mounting area of the die pad 121 by a die bond material 132. The chip mounting area is a recess 124 formed in the die pad 121. The concave portion 124 includes a first portion 124 a that is externally fitted to the semiconductor chip 101 with an interval, and a second portion 124 b that is provided at a portion corresponding to the corner portion of the semiconductor chip 101. In the second portion 124b, the distance between the side surface of the semiconductor chip 101 and the wall surface of the recess is larger than that of the first portion 124a.

本実施形態においては、凹部１２４の深さは、半導体チップ１０１の高さとほぼ等しく、半導体チップ１０１は底面だけでなく、側面の大部分もダイボンド材１３２によりダイパッド１２１と接合されている。このため、半導体チップ１０１とダイパッド１２１との接触面積Ａは、Ａ＝Ｌ×Ｂ＋（Ｌ＋Ｂ）×Ｈ×２となる。但し、Ｌは半導体チップ１０１の縦方向の長さであり、Ｂは半導体チップ１０１の横方向の長さであり、Ｈは半導体チップ１０１の厚さである。このように、底面だけがダイパッド１２１と接合されている場合よりも、（Ｌ＋Ｂ）×Ｈだけ接触面積が大きくなる。熱抵抗θは、θ＝ｔ/（λ・Ａ) （但し、λはダイボンド材の熱伝導率であり、ｔはダイボンド材の厚さである。）であるため、半導体チップ１０１を凹部に収容して接触面積Ａを大きくすることにより、熱抵抗θを低減できる。   In the present embodiment, the depth of the recess 124 is substantially equal to the height of the semiconductor chip 101, and the semiconductor chip 101 is bonded to the die pad 121 not only by the bottom surface but also by the die bonding material 132 at most of the side surface. Therefore, the contact area A between the semiconductor chip 101 and the die pad 121 is A = L × B + (L + B) × H × 2. However, L is the length of the semiconductor chip 101 in the vertical direction, B is the length of the semiconductor chip 101 in the horizontal direction, and H is the thickness of the semiconductor chip 101. Thus, the contact area becomes larger by (L + B) × H than when only the bottom surface is bonded to the die pad 121. Since the thermal resistance θ is θ = t / (λ · A) (where λ is the thermal conductivity of the die bond material and t is the thickness of the die bond material), the semiconductor chip 101 is accommodated in the recess. By increasing the contact area A, the thermal resistance θ can be reduced.

熱抵抗θを小さくするためには、接触面積Ａを大きくするだけでなく、ダイボンド材の厚さｔをできるだけ薄くすることが好ましい。半導体チップを凹部に搭載する場合、凹部のサイズを半導体チップの外形と正確に同じにできれば、半導体チップの側面と凹部の壁面とが直接接するため最も熱抵抗を小さくできる。しかし、実際にはこのような加工は不可能である。このため、予め凹部にダイボンド材を薄く塗布し、半導体チップの側面と凹部の壁面との間にダイボンド材が均一に充填されるようにする必要がある。しかし、ダイボンド材は一般にフィラーを含み粘度が大きいため、塗布する厚さを薄くすることには限界がある。また、半導体チップの側面と凹部の壁面との間隔を小さくするためには、ダイボンド材を塗布する厚さを正確に制御する必要がある。例えば、ダイボンド材が不足すればボイドが発生する。一方、過剰になればダイボンド材があふれ出し、半導体チップの素子形成面に回り込んでしまう。このため、半導体チップの側面と凹部の壁面との間隔を小さくすることは困難である。   In order to reduce the thermal resistance θ, it is preferable not only to increase the contact area A but also to reduce the thickness t of the die bond material as much as possible. When mounting the semiconductor chip in the recess, if the size of the recess can be made exactly the same as the outer shape of the semiconductor chip, the side surface of the semiconductor chip and the wall surface of the recess are in direct contact with each other, so that the thermal resistance can be minimized. However, such processing is actually impossible. For this reason, it is necessary to apply a thin die bond material to the recesses in advance so that the die bond material is uniformly filled between the side surface of the semiconductor chip and the wall surface of the recess. However, since the die bond material generally contains a filler and has a large viscosity, there is a limit to reducing the thickness to be applied. In addition, in order to reduce the distance between the side surface of the semiconductor chip and the wall surface of the recess, it is necessary to accurately control the thickness at which the die bond material is applied. For example, if the die bond material is insufficient, voids are generated. On the other hand, if it becomes excessive, the die bond material overflows and wraps around the element formation surface of the semiconductor chip. For this reason, it is difficult to reduce the distance between the side surface of the semiconductor chip and the wall surface of the recess.

一方、本実施形態の半導体装置は、凹部１２４が半導体チップ１０１に間隔をおいて外嵌した第１の部分１２４ａと、半導体チップ１０１の角部と対応する部分に設けられた第２の部分１２４ｂとを含む。このため、第１の部分１２４ａにおける余剰のダイボンド材は、第２の部分１２４ｂに流れ込む。このため、第１の部分１２４ａにおいて半導体チップ１０１の側面と凹部１２４の壁面との間隔を非常に小さくすることができる。例えば、第１の部分１２４ａにおける半導体チップ１０１の側面と凹部１２４の壁面との間隔は、５μｍ〜２００μｍ程度とすることができる。このため、ダイボンド材１３２の厚さｔを薄くすることができ、熱抵抗をさらに低減できる。   On the other hand, in the semiconductor device according to the present embodiment, the first portion 124a in which the recess 124 is externally fitted to the semiconductor chip 101 with an interval, and the second portion 124b provided in a portion corresponding to the corner portion of the semiconductor chip 101. Including. For this reason, the surplus die-bonding material in the first portion 124a flows into the second portion 124b. For this reason, in the 1st part 124a, the space | interval of the side surface of the semiconductor chip 101 and the wall surface of the recessed part 124 can be made very small. For example, the distance between the side surface of the semiconductor chip 101 and the wall surface of the recess 124 in the first portion 124a can be about 5 μm to 200 μm. For this reason, the thickness t of the die bonding material 132 can be reduced, and the thermal resistance can be further reduced.

本実施形態においては、凹部１２４の深さを半導体チップ１０１の厚さとほぼ等しくしている。このようにすれば、半導体チップ１０１を凹部１２４に収容した際に半導体チップ１０１側面のほぼ全面がダイパッド１２１と接合されることになり、接触面積を最大とすることができる。しかし、必ずしも凹部１２４の深さを半導体チップ１０１の厚さと等しくする必要はなく、半導体チップ１０１の厚さの１／１０以上あれば、接触面積の増大による熱抵抗の低減効果が得られ、より効果的に熱抵抗を低減するためには１／２以上とすることが好ましい。但し、凹部１２４の深さが半導体チップ１０１の厚さよりも大きくなると、半導体チップ１０１の素子形成面にダイボンド材１３２が回り込むおそれがある。このため、凹部１２４の深さは半導体チップ１０１の厚さよりも小さいことが好ましい。半導体チップ１０１の下面と凹部１２４の底面との間にもダイボンド材１３２が存在するため、凹部１２４の深さは厳密には半導体チップ１０１の厚さと半導体チップ１０１の下側に存在するダイボンド材１３２の厚さとの和に基づいて設計する必要がある。しかし、半導体チップ１０１の下側に存在するダイボンド材１３２の厚さは、半導体チップ１０１の厚さよりも薄く、通常は無視してかまわない。   In the present embodiment, the depth of the recess 124 is substantially equal to the thickness of the semiconductor chip 101. In this way, when the semiconductor chip 101 is accommodated in the recess 124, almost the entire side surface of the semiconductor chip 101 is bonded to the die pad 121, and the contact area can be maximized. However, it is not always necessary to make the depth of the recess 124 equal to the thickness of the semiconductor chip 101. If the thickness of the semiconductor chip 101 is 1/10 or more, the effect of reducing the thermal resistance by increasing the contact area can be obtained. In order to effectively reduce the thermal resistance, it is preferably set to 1/2 or more. However, if the depth of the recess 124 is greater than the thickness of the semiconductor chip 101, the die bond material 132 may wrap around the element formation surface of the semiconductor chip 101. For this reason, the depth of the recess 124 is preferably smaller than the thickness of the semiconductor chip 101. Since the die bond material 132 exists also between the lower surface of the semiconductor chip 101 and the bottom surface of the recess 124, the depth of the recess 124 is strictly the thickness of the semiconductor chip 101 and the die bond material 132 existing below the semiconductor chip 101. It is necessary to design based on the sum of thickness. However, the thickness of the die bond material 132 present on the lower side of the semiconductor chip 101 is smaller than the thickness of the semiconductor chip 101 and may be normally ignored.

半導体チップ１０１の形状は特に問わないが、あまりにも極端に厚さが薄い場合には、側面からの放熱が小さくなる。半導体チップ１０１が平面方形状の場合には、半導体チップの厚さが、長辺の長さの１／２０以上である場合には、チップ搭載部を凹部とする効果が特に大きくなる。但し、半導体チップの厚さは、基板の厚さによってほぼ決まるため、最大でも０．５ｍｍ〜０．８ｍｍ程度となる。   The shape of the semiconductor chip 101 is not particularly limited, but if the thickness is too thin, the heat radiation from the side surface becomes small. In the case where the semiconductor chip 101 has a planar rectangular shape, the effect of making the chip mounting portion a recess is particularly large when the thickness of the semiconductor chip is 1/20 or more of the length of the long side. However, since the thickness of the semiconductor chip is almost determined by the thickness of the substrate, it is about 0.5 mm to 0.8 mm at the maximum.

本実施形態においては、第２の部分１２４ｂを平面三角形状としているが、余剰のダイボンド材１３２を吸収できればよく、どの様な平面形状であってもよい。例えば、図２に示すように平面方形状としてもよく、図３に示すように平面円形状としてもよい。本実施形態においては、半導体チップ１０１が平面方形状であり、その４つの角部に対応して第２の部分１２４ｂを４個所設けているが、全ての角部の設ける必要はなく、少なくとも１つの角部に設けられていればよい。また、角部以外の部分に設けられていてもよい。但し、全ての角部又は対称の角部若しくは辺部に余剰のダイボンド材１３２を吸収する部分を設けることによりダイボンド材１３２の流れを対称にし、半導体チップ１０１と凹部１２４との間に均一にダイボンド材１３２を充填することが容易となる。このため、半導体チップ１０１から周囲への不均一な熱伝導をおさえることができる。半導体チップ１０１は平面方形状である必要はなく、平面三角形状、平面６角形状又は平面８角形状等の平面多角形状や平面円形状等であって問題はない。   In the present embodiment, the second portion 124b has a planar triangular shape, but it may be any planar shape as long as it can absorb the excess die-bonding material 132. For example, it may have a planar square shape as shown in FIG. 2 or a planar circular shape as shown in FIG. In the present embodiment, the semiconductor chip 101 has a planar rectangular shape and four second portions 124b are provided corresponding to the four corners. However, it is not necessary to provide all the corners. It is only necessary to be provided at one corner. Moreover, you may provide in parts other than a corner | angular part. However, the flow of the die bonding material 132 is made symmetrical by providing a portion that absorbs the excess die bonding material 132 at all corners or symmetrical corners or sides, and the die bonding is uniformly performed between the semiconductor chip 101 and the recess 124. It becomes easy to fill the material 132. For this reason, non-uniform heat conduction from the semiconductor chip 101 to the surroundings can be suppressed. The semiconductor chip 101 does not need to have a planar rectangular shape, and has a planar polygonal shape such as a planar triangular shape, a planar hexagonal shape, or a planar octagonal shape, a planar circular shape, or the like.

図１〜３においては、ダイパッド１２１の凹部１２４を囲む部分の上面が平坦に形成されている例を示したが、図４に示すように凹部１２４を囲む部分は、その高さが外縁部に向かって次第に低くなるように傾斜していてもよい。このようにすれば、ワイヤ１３１がダイパッド１２１と接触する危険性を小さくすることができる。   1 to 3 show an example in which the upper surface of the portion surrounding the recess 124 of the die pad 121 is formed flat. However, as shown in FIG. 4, the height of the portion surrounding the recess 124 is at the outer edge. You may incline so that it may become low gradually toward it. In this way, the danger that the wire 131 contacts the die pad 121 can be reduced.

図１〜３においては、ダイパッド１２１の半導体チップ１０１を搭載する面と反対側の面（裏面）が絶縁モールド１３３に覆われている構成を示したが、図５に示すようにダイパッド１２１の裏面が絶縁モールド１３３から露出している構成としてもよい。このような構成とすれば、ダイパッド１２１の裏面にヒートシンク又は冷却器等を直接接触させることができ、放熱性をさらに向上させることができる。   1 to 3 show a configuration in which the surface (back surface) opposite to the surface on which the semiconductor chip 101 is mounted of the die pad 121 is covered with the insulating mold 133, but the back surface of the die pad 121 as shown in FIG. 5. May be exposed from the insulating mold 133. With such a configuration, a heat sink or a cooler or the like can be brought into direct contact with the back surface of the die pad 121, and heat dissipation can be further improved.

凹部１２４は、どのようにして形成してもよい。例えば、銅合金等の金属板を切削又はエッチングすることにより形成すればよい。また、半切断プレス加工等により形成してもよい。この場合には、図６に示すようにダイパッド１２１の裏面に凹部１２４に対応して凸部が形成される。このため、ダイパッド１２１の厚さは、凹部１２４と他の部分とにおいてほぼ等しくなる。プレスの精度等にもよるが、凹部１２４における厚さｄ１と他の部分における厚さｄ２との差は±１０％以下とすることができる。また、ダイパッド１２１の裏面に凸部が形成されているため、ダイパッド１２１の裏面を絶縁モールド１３３から露出させることが容易となるという利点も得られる。   The recess 124 may be formed in any way. For example, it may be formed by cutting or etching a metal plate such as a copper alloy. Moreover, you may form by a half-cut press process. In this case, as shown in FIG. 6, a convex portion is formed on the back surface of the die pad 121 corresponding to the concave portion 124. For this reason, the thickness of the die pad 121 is substantially equal between the concave portion 124 and other portions. Although it depends on the accuracy of pressing, etc., the difference between the thickness d1 in the recess 124 and the thickness d2 in other portions can be ± 10% or less. Moreover, since the convex part is formed in the back surface of the die pad 121, the advantage that it becomes easy to expose the back surface of the die pad 121 from the insulating mold 133 is also acquired.

また、図７に示すように底板１２１Ａと枠体１２１Ｂとを接合することにより、凹部１２４を形成してもよい。このようにすれば、インナーリード部１２２Ａの端部と、ダイパッド１２１の端部と平面視において重ねることができ、半導体装置のサイズを大きくすることなく、ダイパッド１２１のサイズを大きくすることが容易にできるという利点も得られる。また、図７に示すように、半導体チップ１０１側から反対側に向かって枠体１２１Ｂの高さが次第に低くなるようにすることが容易であり、このようにすればワイヤ１３１とダイパッド１２１とが接触する危険性を小さくすることができる。なお、底板１２１Ａの裏面は絶縁モールド１３３に覆われていなくてもよい。   Further, as shown in FIG. 7, the recess 124 may be formed by joining the bottom plate 121A and the frame body 121B. In this way, the end portion of the inner lead portion 122A and the end portion of the die pad 121 can be overlapped in plan view, and the size of the die pad 121 can be easily increased without increasing the size of the semiconductor device. The advantage of being able to do it is also obtained. In addition, as shown in FIG. 7, it is easy to make the height of the frame 121B gradually lower from the semiconductor chip 101 side to the opposite side, and in this way, the wire 131 and the die pad 121 can be connected. The risk of contact can be reduced. Note that the back surface of the bottom plate 121A may not be covered with the insulating mold 133.

図１〜７において、半導体チップ１０１のチップ端子１１１とインナーリード部１２２Ａとをワイヤ１３１により接続する例を示したが、図８に示すようにバンプ１３４により接続してもよい。バンプ１３４は、高さを１００μｍ以下とすればよい。このようにすれば、リード１２２と半導体チップ１０１との間隔を小さくでき、半導体チップ１０１において発生した熱をリード１２２へ効率良く伝達し、放熱することができる。   1-7, the example which connected the chip terminal 111 of the semiconductor chip 101 and the inner lead part 122A with the wire 131 was shown, However, You may connect with the bump 134 as shown in FIG. The bump 134 may have a height of 100 μm or less. In this way, the distance between the lead 122 and the semiconductor chip 101 can be reduced, and the heat generated in the semiconductor chip 101 can be efficiently transmitted to the lead 122 and radiated.

図８は、半導体装置をプリント基板等の実装基板１５１等に実装した際に、ダイパッド１２１の裏面が実装基板１５１側となるようにした例を示しているが、図９に示すようにダイパッド１２１の裏面が実装基板１５１と反対側となるようにしてもよい。図８及び図９においても、ダイパッド１２１の裏面は絶縁モールド１３３に覆われていなくてもよい。   FIG. 8 shows an example in which the back surface of the die pad 121 is on the mounting substrate 151 side when the semiconductor device is mounted on the mounting substrate 151 such as a printed circuit board. As shown in FIG. The back surface may be opposite to the mounting substrate 151. 8 and 9, the back surface of the die pad 121 may not be covered with the insulating mold 133.

図８及び図９においては、インナーリード部１２２Ａの厚さを一定とした例を示したが、図１０及び図１１に示すように半導体チップ１０１側においてアウターリード部１２２Ｂ側よりも厚さを薄くしてもよい。このようにすることにより、リード１２２のピッチを狭くすることができ、ピン数が多い場合にも半導体装置を小さくできる。   8 and 9 show an example in which the thickness of the inner lead portion 122A is constant. However, as shown in FIGS. 10 and 11, the thickness on the semiconductor chip 101 side is thinner than that on the outer lead portion 122B side. May be. By doing so, the pitch of the leads 122 can be reduced, and the semiconductor device can be reduced even when the number of pins is large.

図１０及び図１１においては、インナーリード部１２２Ａの厚さを連続的に変化させた例を示したが、図１２及び図１３に示すように、段差を設けるようにしてもよい。段差を設ける場合には、図１４及び図１５に示すようにしてもよい。   10 and 11, the example in which the thickness of the inner lead portion 122A is continuously changed is shown. However, as shown in FIGS. 12 and 13, a step may be provided. When providing a level | step difference, you may make it show in FIG.14 and FIG.15.

図１６に示すように、半導体チップ１０１を発光ダイオード（ＬＥＤ）又はレーザダイオード等の発光素子としてもよい。この場合には絶縁モールド１３３の一部を、透明樹脂等からなる透明窓１３６とすればよい。ＬＥＤの場合にはチップの底面積が小さい場合が多く、側面からも放熱できるようにすることの効果が大きい。発光素子に代えて、可視光若しくは赤外光等の受光素子又はイメージセンサ等とすることも可能である。   As shown in FIG. 16, the semiconductor chip 101 may be a light emitting element such as a light emitting diode (LED) or a laser diode. In this case, a part of the insulating mold 133 may be a transparent window 136 made of a transparent resin or the like. In the case of LEDs, the bottom area of the chip is often small, and the effect of enabling heat dissipation from the side surface is great. Instead of the light emitting element, a light receiving element such as visible light or infrared light, an image sensor, or the like may be used.

また、図１７に示すようにリード１２２の１つをダイパッド１２１と一体としてもよい。このようにすれば、ダイパッド１２１のトータルの面積が大きくなるため、放熱効果をさらに向上させることができる。また、半導体チップ１０１の裏面に電極を設け、ダイボンド材１３２を導電性とすれば、ダイパッド１２１と一体となったリード１２２とチップ端子１１１とをワイヤ１３１により接続しなくてもよい。ＱＦＰの場合にも、リード１２２の少なくとも１つをダイパッド１２１と一体としてもよい。   Further, as shown in FIG. 17, one of the leads 122 may be integrated with the die pad 121. In this way, the total area of the die pad 121 is increased, so that the heat dissipation effect can be further improved. Further, if an electrode is provided on the back surface of the semiconductor chip 101 and the die bonding material 132 is made conductive, the lead 122 integrated with the die pad 121 and the chip terminal 111 need not be connected by the wire 131. Also in the case of QFP, at least one of the leads 122 may be integrated with the die pad 121.

本実施形態において、ダイパッド１２１及びリード１２２は銅又は銅を含む合金等とすればよい。チップ端子１１１とリード１２２とを接続するワイヤは例えばアルミニウム線とすればよい。バンプ１３４は、金ワイヤバンプ又ははんだバンプ等とすればよい。絶縁モールド１３３は、絶縁性の樹脂又はセラミックス等とすればよい。   In the present embodiment, the die pad 121 and the lead 122 may be copper or an alloy containing copper. A wire connecting the chip terminal 111 and the lead 122 may be an aluminum wire, for example. The bumps 134 may be gold wire bumps or solder bumps. The insulating mold 133 may be made of insulating resin or ceramics.

ダイボンド材は、熱伝導率λが１Ｗ／ｍ・Ｋ〜５０Ｗ／ｍ・Ｋ程度ある材料を用いることが好ましい。可能であればさらに熱伝導率が高い材料であってもよい。また、厚さが薄いことが好ましく、ダイボンド材の材質により異なるが１μｍ〜４０μｍ程度とすることが好ましい。種々の材質のダイボンド材を用いることができるが、熱ストレスの観点から、銀に代表される金属等のフィラーを樹脂へ配合したペースト又はグリスが好ましい。樹脂は熱伝導率が高いものが好ましく、エポキシ及びアクリル等を用いることができる。この場合、樹脂骨格の熱伝導率を０．２Ｗ／ｍ・Ｋ〜０．５Ｗ／ｍ・Ｋとすることができ、さらに樹脂骨格を改良することにより樹脂骨格の熱伝導率を１Ｗ／ｍ・Ｋ程度まで高めることができる。このような、樹脂に金属等のフィラーを加えたダイボンド材の場合、ほとんどの熱伝導をフィラーにて担うことができる。フィラーは金属だけでなく、カーボンナノチューブ等の炭素フィラーとしてもよい。金属又は炭素フィラーを配合したダイボンド材を用いることによりλを１Ｗ／ｍ・Ｋ〜２０Ｗ／ｍ・Ｋ程度とすることができる。金属フィラーを配合したペースト等を用いることによりコストも低減できる。接合部の厚さを薄くするためには配合するフィラーの径をできるだけ小さくすることが好ましい。はんだ等の溶融金属からなるダイボンド材を用いた場合には接合工程のコストがかかるが、λを５０Ｗ／ｍ・Ｋ程度とすることができ、熱伝導をより向上できる。溶融金属の場合、金属側の濡れ性を向上させることにより接合部の厚さをより薄くすることができる。   As the die bond material, a material having a thermal conductivity λ of about 1 W / m · K to 50 W / m · K is preferably used. If possible, a material having higher thermal conductivity may be used. Moreover, it is preferable that thickness is thin, and although it changes with materials of die-bonding material, it is preferable to set it as about 1 micrometer-40 micrometers. Various die-bonding materials can be used, but from the viewpoint of thermal stress, a paste or grease in which a filler such as a metal represented by silver is blended with a resin is preferable. The resin preferably has high thermal conductivity, and epoxy, acrylic, or the like can be used. In this case, the thermal conductivity of the resin skeleton can be 0.2 W / m · K to 0.5 W / m · K, and the thermal conductivity of the resin skeleton can be improved to 1 W / m · K by further improving the resin skeleton. It can be increased to about K. In the case of such a die bond material in which a filler such as a metal is added to a resin, most heat conduction can be carried by the filler. The filler may be not only a metal but also a carbon filler such as a carbon nanotube. Λ can be set to about 1 W / m · K to 20 W / m · K by using a die bond material containing a metal or a carbon filler. Cost can also be reduced by using a paste or the like containing a metal filler. In order to reduce the thickness of the joint portion, it is preferable to reduce the diameter of the filler to be blended as much as possible. When a die bond material made of a molten metal such as solder is used, the cost of the joining process is high, but λ can be set to about 50 W / m · K, and the heat conduction can be further improved. In the case of molten metal, the thickness of the joint can be further reduced by improving the wettability on the metal side.

本発明に係る半導体装置は、半導体チップからダイパッドへ効率良く放熱する半導体装置を実現でき、特に発熱量が大きい半導体装置等として有用である。   The semiconductor device according to the present invention can realize a semiconductor device that efficiently dissipates heat from a semiconductor chip to a die pad, and is particularly useful as a semiconductor device that generates a large amount of heat.

１０１ 半導体チップ
１０２ リードフレーム
１１１ チップ端子
１２１ ダイパッド
１２１Ａ 底板
１２１Ｂ 枠体
１２２ リード
１２２Ａ インナーリード部
１２２Ｂ アウターリード部
１２４ 凹部
１２４ａ 第１の部分
１２４ｂ 第２の部分
１３１ ワイヤ
１３２ ダイボンド材
１３３ 絶縁モールド
１３４ バンプ
１３６ 透明窓
１５１ 実装基板 101 Semiconductor chip 102 Lead frame 111 Chip terminal 121 Die pad 121A Bottom plate 121B Frame body 122 Lead 122A Inner lead portion 122B Outer lead portion 124 Recessed portion 124a First portion 124b Second portion 131 Wire 132 Die bonding material 133 Insulating mold 134 Bump 136 Transparent Window 151 Mounting board

Claims (19)

ダイパッドを含むリードフレームと、
前記ダイパッドのチップ搭載領域にダイボンド材により接合された半導体チップとを備え、
前記チップ搭載領域は、前記半導体チップに間隔をおいて外嵌する第１の部分と、前記第１の部分よりもその壁面と前記半導体チップの側面との間隔が大きい第２の部分とを含む凹部であり、
前記半導体チップの側面と前記凹部の壁面との間には前記ダイボンド材が充填されていることを特徴とする半導体装置。 A lead frame including a die pad;
A semiconductor chip bonded to the chip mounting area of the die pad by a die bond material;
The chip mounting area includes a first portion that is fitted on the semiconductor chip with a space therebetween, and a second portion that has a larger space between the wall surface and the side surface of the semiconductor chip than the first portion. A recess,
The semiconductor device is characterized in that the die bond material is filled between a side surface of the semiconductor chip and a wall surface of the recess. 前記半導体チップは、平面方形状であり、
前記第２の部分は、前記半導体チップの角部と対応する部分に形成されていることを特徴とする請求項１に記載の半導体装置。 The semiconductor chip has a planar rectangular shape,
The semiconductor device according to claim 1, wherein the second portion is formed in a portion corresponding to a corner portion of the semiconductor chip. 前記凹部は、前記半導体チップの厚さの１０分の１以上且つ前記半導体チップの厚さ未満の深さであることを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the recess has a depth equal to or more than one-tenth of the thickness of the semiconductor chip and less than the thickness of the semiconductor chip. 前記第１の部分における前記半導体チップの側面と前記凹部の壁面との間隔は、５μｍ以上且つ２００μｍ以下であることを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein an interval between a side surface of the semiconductor chip and a wall surface of the recess in the first portion is 5 μm or more and 200 μm or less. 前記半導体チップは、平面方形状であり、
前記半導体チップの厚さは、長辺の長さの２０分の１以上であることを特徴とする請求項１に記載の半導体装置。 The semiconductor chip has a planar rectangular shape,
2. The semiconductor device according to claim 1, wherein the thickness of the semiconductor chip is 1/20 or more of the length of the long side. 前記ダイパッドにおける前記凹部が形成された部分の厚さは、前記ダイパッドにおける他の部分の厚さと等しいことを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein a thickness of a portion of the die pad where the concave portion is formed is equal to a thickness of another portion of the die pad. 前記凹部は、半切断プレス加工により形成されていることを特徴とする請求項６に記載の半導体装置。   The semiconductor device according to claim 6, wherein the concave portion is formed by half-cut pressing. 前記ダイパッドは、その上面が前記凹部の側から外縁部に向かって次第に低くなるように傾斜していることを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the die pad is inclined so that an upper surface of the die pad gradually becomes lower from the recess side toward the outer edge portion. 前記ダイパッドは、底板と、前記底板の上に接合された枠体とを有していることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the die pad includes a bottom plate and a frame joined to the bottom plate. 前記枠体は、その高さが前記凹部の側から外縁部に向かって次第に低くなるように傾斜していることを特徴とする請求項９に記載の半導体装置。   The semiconductor device according to claim 9, wherein the frame body is inclined so that the height thereof gradually decreases from the concave portion side toward the outer edge portion. 前記半導体チップ及びリードフレームを封止する絶縁モールドをさらに備え、
前記リードフレームは、前記絶縁モールドの外側に突出した複数のリードを有していることを特徴とする請求項１に記載の半導体装置。 An insulating mold for sealing the semiconductor chip and the lead frame;
The semiconductor device according to claim 1, wherein the lead frame includes a plurality of leads protruding outside the insulating mold. 前記複数のリードの１つは、前記ダイパッドと一体であることを特徴とする請求項１１に記載の半導体装置。   The semiconductor device according to claim 11, wherein one of the plurality of leads is integral with the die pad. 前記半導体チップはチップ端子を有し、
前記チップ端子と前記リードとはバンプにより接続されていることを特徴とする請求項１１に記載の半導体装置。 The semiconductor chip has a chip terminal,
The semiconductor device according to claim 11, wherein the chip terminal and the lead are connected by a bump. 前記ダイパッドは、実装基板に実装された際に、前記半導体チップを搭載した面と反対側の面が前記実装基板側となるように、前記リードと接続されていることを特徴とする請求項１３に記載の半導体装置。   14. The die pad is connected to the lead so that when mounted on a mounting substrate, the surface opposite to the surface on which the semiconductor chip is mounted is on the mounting substrate side. A semiconductor device according to 1. 前記ダイパッドは、実装基板に実装された際に、前記半導体チップを搭載した面が前記実装基板側となるように、前記リードと接続されていることを特徴とする請求項１３に記載の半導体装置。   The semiconductor device according to claim 13, wherein the die pad is connected to the lead so that a surface on which the semiconductor chip is mounted is on the mounting substrate side when mounted on the mounting substrate. . 前記ダイパッドは、前記半導体チップを搭載した面と反対側の面が前記絶縁モールドから露出していることを特徴とする請求項１１に記載の半導体装置。   The semiconductor device according to claim 11, wherein a surface of the die pad opposite to a surface on which the semiconductor chip is mounted is exposed from the insulating mold. 前記リードは、前記絶縁モールドに覆われたインナーリード部と、前記絶縁モールドから突出したアウターモールド部とを有し、
前記インナーリード部の厚さは、前記アウターリード部側の部分よりも、前記半導体チップ側の部分において薄いことを特徴とする請求項１１に記載の半導体装置。 The lead has an inner lead portion covered with the insulating mold and an outer mold portion protruding from the insulating mold,
12. The semiconductor device according to claim 11, wherein the thickness of the inner lead portion is thinner in the portion on the semiconductor chip side than the portion on the outer lead portion side. 前記インナーリード部の厚さは、前記アウターリード部側から前記半導体チップ側に向かって連続的に薄くなっていることを特徴とする請求項１７に記載の半導体装置。   18. The semiconductor device according to claim 17, wherein the thickness of the inner lead portion is continuously reduced from the outer lead portion side toward the semiconductor chip side. 前記半導体チップは、発光ダイオードであることを特徴とする請求項１〜１８のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the semiconductor chip is a light emitting diode.
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JP2018174232A (en) * 2017-03-31 2018-11-08 富士電機株式会社 Semiconductor device and manufacturing method
JP7019957B2 (en) 2017-03-31 2022-02-16 富士電機株式会社 Semiconductor devices and manufacturing methods
CN107958948A (en) * 2017-12-28 2018-04-24 广东晶科电子股份有限公司 A kind of LED light emitting diodes and preparation method thereof
CN113611753A (en) * 2021-07-20 2021-11-05 东莞先导先进科技有限公司 Infrared detector packaging structure and packaging method
CN116230555A (en) * 2023-05-06 2023-06-06 芯盟科技有限公司 Chip carrier, forming method thereof and forming method of wafer bonding structure
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CN117410428A (en) * 2023-12-13 2024-01-16 深圳市绿源极光科技有限公司 LED chip packaging structure for COB light source
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