CN113380725A - Chip packaging structure and packaging method - Google Patents
Chip packaging structure and packaging method Download PDFInfo
- Publication number
- CN113380725A CN113380725A CN202110477284.3A CN202110477284A CN113380725A CN 113380725 A CN113380725 A CN 113380725A CN 202110477284 A CN202110477284 A CN 202110477284A CN 113380725 A CN113380725 A CN 113380725A
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- Prior art keywords
- chip
- substrate
- heat dissipation
- filling layer
- package structure
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 72
- 230000017525 heat dissipation Effects 0.000 claims abstract description 45
- 230000003014 reinforcing effect Effects 0.000 claims description 15
- 239000003292 glue Substances 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 239000011347 resin Substances 0.000 claims description 5
- 229920005989 resin Polymers 0.000 claims description 5
- 238000007789 sealing Methods 0.000 claims description 5
- 239000002657 fibrous material Substances 0.000 claims description 3
- 230000002787 reinforcement Effects 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 239000008393 encapsulating agent Substances 0.000 claims 2
- 239000003351 stiffener Substances 0.000 claims 1
- 230000003139 buffering effect Effects 0.000 abstract description 4
- 230000000694 effects Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- 238000001816 cooling Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000012536 packaging technology Methods 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 239000012945 sealing adhesive Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The application discloses a chip packaging structure and a packaging method, wherein the structure comprises the following steps: the chip comprises a substrate, a chip attached to the substrate and a heat dissipation cover covering the chip, wherein a filling layer is arranged around the chip. The filling layer is arranged between the heat dissipation cover and the substrate, so that the filling layer surrounds the chip pasted on the substrate, the filling layer can be utilized to play a buffering role between the substrate and the heat dissipation cover, the deformation of the substrate is controlled, the deformation of the heat dissipation cover caused by the deformation of the substrate is avoided, the good contact between the chip and the substrate is ensured, and the product yield is improved.
Description
Technical Field
The present invention relates to the field of packaging technologies, and in particular, to a chip package structure and a chip package method.
Background
Packaging is a technique for packaging integrated circuits with an insulating plastic or ceramic material. At present, the flip chip packaging technology is more and more widely applied in the field of chip packaging, particularly in the fields of high power and large size.
The existing large-size flip-chip packaging product has the specific packaging process that: and pasting a chip on the bare substrate, arranging additional components around the chip, and finally pasting a heat dissipation cover on the chip to complete the flip chip structure.
For the chip packaging structure, due to the warping of the substrate and the heat dissipation cover, poor welding between the chip and the substrate occurs in the high-temperature reflow process of the product, and the heat dissipation cover is not in good contact with the chip, so that the product finally fails and the heat dissipation is not good.
Disclosure of Invention
In view of the above-mentioned drawbacks and deficiencies of the prior art, it is desirable to provide a chip package structure and a packaging method, which provide a buffer between a substrate and a heat dissipation cover by disposing a filling layer around a chip.
In a first aspect, an embodiment of the present application provides a chip packaging structure, including: the chip comprises a substrate, a chip attached to the substrate and a heat dissipation cover covering the chip, wherein a filling layer is arranged around the chip.
Optionally, in the chip package structure according to the embodiment of the present application, the filling layer is an annular structure with an opening in the middle for placing the chip.
Optionally, in the chip package structure according to the embodiment of the present application, the material of the filling layer is synthesized by a fiber material and a resin, or synthesized by a silicon dioxide and a resin.
Optionally, in the chip package structure of the embodiment of the application, a passive component is disposed around the chip, and the filling layer covers the passive component.
Optionally, in the chip packaging structure of the embodiment of the application, the edge of the substrate is provided with a reinforcing sheet.
Optionally, in the chip package structure according to the embodiment of the application, the reinforcing sheet is a ring-shaped structure disposed at an edge of the substrate.
Optionally, in the chip packaging structure of the embodiment of the present application, the bottom of the chip is provided with a bottom sealing adhesive, and the top of the chip is provided with a heat dissipation adhesive.
In a second aspect, an embodiment of the present application provides a chip packaging method, including:
arranging a pasting chip on the substrate;
disposing a filler layer around the chip;
and arranging a heat dissipation cover on the chip and the filling layer.
Optionally, in the chip packaging method according to the embodiment of the present application, before attaching the chip to the substrate, the method further includes:
reinforcing tabs are provided at the edges of the substrate.
Optionally, in the chip packaging method according to the embodiment of the present application, before attaching the chip to the substrate, the method further includes:
a bottom sealing glue is arranged at the position of the substrate where the chip is pasted,
after attaching the chip on the substrate, the method further comprises:
and the top of the chip is provided with heat dissipation glue.
In summary, according to the chip packaging structure and the chip packaging method provided by the embodiment of the application, in the technology from the large-size chip to the packaging technology, the filling layer is arranged between the heat dissipation cover and the substrate, so that the filling layer surrounds the chip attached to the substrate, the filling layer can be utilized to play a buffering role between the substrate and the heat dissipation cover, the deformation of the substrate is controlled, the deformation of the heat dissipation cover caused by the deformation of the substrate is avoided, the good contact between the chip and the substrate is ensured, and the product yield is improved.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
FIG. 1 is a schematic diagram of a prior art inverted package structure with warpage;
fig. 2 is a schematic diagram of a chip package structure according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of an encapsulation layer according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram of a chip package structure according to another embodiment of the present application;
FIG. 5 is a schematic structural diagram of a reinforcing plate according to an embodiment of the present disclosure;
fig. 6 is a schematic flowchart of a chip packaging method according to an embodiment of the present application.
Reference numerals:
1-substrate, 2-chip, 3-heat dissipation cover, 4-filling layer, 5-reinforcing sheet, 6-passive component, 7-bottom sealing glue and 8-heat dissipation glue.
Detailed Description
The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
It can be understood that, as shown in fig. 1, in the large-size package structure, because the overall structure size such as the substrate is large, and the substrate and the heat dissipation cover are suspended in the air, the substrate and the heat dissipation cover are easily warped in the using process, so that the chip and the substrate are soldered in a peeling manner during the high-temperature reflow process of the product, and the heat dissipation cover is not in good contact with the chip due to the warping of the heat dissipation cover, thereby finally affecting the heat dissipation effect.
In order to solve various problems caused by warping of a substrate and a heat dissipation cover in a product, the filling layer is arranged at the vacant position between the substrate and the heat dissipation cover to form buffering between the substrate and the heat dissipation cover, so that deformation of the substrate is controlled, deformation of the heat dissipation cover caused by deformation of the substrate is avoided in subsequent use, good contact between a chip and the substrate is further ensured, and the heat dissipation effect of the heat dissipation cover is ensured.
For better understanding and description of the chip packaging structure and the chip packaging method provided by the embodiments of the present application, the following is detailed with reference to fig. 2 to 6.
Fig. 2 shows a chip package structure provided in an embodiment of the present application, and as shown in fig. 2, the chip package structure may include:
the chip packaging structure comprises a substrate, a chip attached to the substrate, a filling layer arranged around the chip, and a heat dissipation cover arranged on the chip and the filling layer.
It can be understood that, this application embodiment sets up the filling layer through the vacancy between base plate and heating lid, namely around the chip to form the buffering between base plate and heating lid, avoid the warpage of base plate and heating lid, guaranteed the good contact of base plate and chip, and the radiating effect of cooling lid.
Optionally, as shown in fig. 3, in the embodiment of the present application, for convenience of the process, the filling layer may be fabricated by first forming a film structure with a flat surface, then cutting the film structure into individual pieces according to the size and height defined by the specific product characteristics, and finally digging out the middle according to the size of the chip to form the ring assembly structure.
Alternatively, the filling layer may be made of a composite material formed by laminating a fiber material or silica particles and a resin.
It is understood that in the embodiments of the present application, in order to provide a better buffer effect for the filling layer, the filling layer has the characteristics of high Tg, low CTE and small deformation.
In addition, in the embodiment of the present application, passive components, such as resistors or capacitors, may be disposed around the chip on the substrate. The filling layer is arranged on the substrate and completely covers the passive component, so that the passive component can be effectively protected, and the passive component is prevented from being invalid due to temperature and humidity change or electric performance invalidation due to metal splashing is avoided.
In the embodiment of the application, the filling layer is arranged between the substrate and the heat dissipation cover, the buffer layer is formed, the warpage of the substrate and the heat dissipation cover is effectively avoided in the using process of a product, the good contact between a chip and the substrate is ensured, passive components are effectively protected, the passive components are prevented from being out of work due to temperature and humidity changes, or electrical performance is caused to be out of work due to metal splashing, the control of the warpage of the product is realized, and the product yield is improved.
Optionally, as shown in fig. 4 and 5, in the embodiment of the present application, in order to more effectively control the deformation of the substrate as a whole, a reinforcing plate may be disposed at an edge position of the substrate to reinforce the entire substrate. In practice, warpage of 100-.
For example, as shown in fig. 5, a ring of reinforcing plates with a ring-shaped structure may be disposed at the edge position of the substrate.
It can be understood that, in order to stabilize the whole substrate by the reinforcing sheet, in the actual process, the reinforcing sheet is arranged around the edge of the substrate before the chip is attached to the substrate, so that the whole substrate can be stabilized from the initial state of the packaging process, and the substrate is prevented from being deformed in the subsequent process and the use process.
It will be appreciated that the provision of the reinforcing sheet allows the outer dimensions of the infill layer to be determined in accordance with the inner dimensions of the looped reinforcing sheet when the infill layer is cut.
It will also be appreciated that the heat dissipation on the chip is planar due to the provision of the reinforcing sheet, without the need for edge-disposed protrusions.
In the embodiment of the application, the reinforcing sheet is firstly pasted on the substrate so as to control the warping of a product in the chip mounting reflow process, and the risks of chip bridging and poor welding are reduced.
Optionally, as shown in fig. 4, in the package structure provided in the embodiment of the present application, a position of the chip may be further disposed on the substrate, that is, the bottom of the chip is disposed with the underfill adhesive, so that the chip is firmly attached to the substrate.
In addition, the top of the chip can be provided with heat dissipation glue, namely, the heat dissipation glue is arranged between the chip and the heat dissipation cover, so that the product has a better heat dissipation effect.
Optionally, in an embodiment, in order to improve the heat dissipation effect, the heat dissipation glue may be set to be a metal material.
On the other hand, as shown in fig. 6, an embodiment of the present application further provides a packaging method, where the method may include:
s1, arranging a reinforcing sheet at the edge of the substrate;
s2, arranging bottom sealing glue at the position where the chip is pasted at the central position of the substrate;
s3, attaching a chip on the bottom sealing glue, and attaching a passive element around the chip;
s4, reinforcing the inside of the chip on the substrate and arranging a filling layer around the chip;
s5, arranging heat dissipation glue on the chip;
and S6, arranging a heat dissipation cover on the heat dissipation glue and the filling layer.
The chip packaging method of the embodiment of the application, before pasting the chip, set up the reinforcement piece at the substrate edge earlier, in order to control the product warpage in the chip pastes dress backward flow process, reduce the risk of chip bridging and poor welding, then at the filling layer of reinforcement piece and the middle packing of chip, can play the cushioning effect between base plate and cooling cover, on the one hand, the deformation of control base plate, on the other hand avoids leading to the cooling cover to warp because the deformation of base plate, and can protect passive components and parts, avoid passive components and parts to lead to the inefficacy because temperature and humidity change, perhaps metal splashes and leads to the electrical property inefficacy, the warpage of product can effectively be controlled to this structure, promote the product yield.
It is understood that heating and ball-planting reflow can also be performed after the heat dissipation cover is attached.
The above description is only a preferred embodiment of the application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.
Claims (10)
1. A chip package structure, comprising: a substrate, a chip attached on the substrate, and a heat dissipation cover covering the chip, characterized in that,
and a filling layer is arranged around the chip.
2. The chip package structure according to claim 1, wherein the filling layer is a ring structure with an opening in the middle for placing the chip.
3. The chip package structure according to claim 1, wherein the material of the filling layer is formed by a fiber material and a resin, or a silicon dioxide and a resin.
4. The chip package structure according to claim 1, wherein a passive component is disposed around the chip, and the filling layer covers the passive component.
5. The chip package structure according to any one of claims 1 to 4, wherein the substrate edge is provided with a reinforcement sheet.
6. The chip package structure according to claim 5, wherein the stiffener is a ring-shaped structure disposed at an edge of the substrate.
7. The chip package structure according to any one of claims 1 to 4 or 6, wherein a bottom encapsulant is disposed on the bottom of the chip, and a heat dissipation encapsulant is disposed on the top of the chip.
8. A method of chip packaging, the method comprising:
arranging a pasting chip on the substrate;
arranging a filling layer around the chip;
and arranging heat dissipation covers on the chip and the filling layer.
9. The chip packaging method according to claim 8, wherein before attaching the chip on the substrate, the method further comprises:
and arranging a reinforcing sheet at the edge of the substrate.
10. The chip packaging method according to claim 9, wherein before attaching the chip on the substrate, the method further comprises:
bottom sealing glue is arranged at the position where the chip is pasted on the substrate,
after attaching a chip on the substrate, the method further comprises:
and arranging heat dissipation glue on the top of the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110477284.3A CN113380725A (en) | 2021-04-29 | 2021-04-29 | Chip packaging structure and packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110477284.3A CN113380725A (en) | 2021-04-29 | 2021-04-29 | Chip packaging structure and packaging method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113380725A true CN113380725A (en) | 2021-09-10 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202110477284.3A Pending CN113380725A (en) | 2021-04-29 | 2021-04-29 | Chip packaging structure and packaging method |
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| Country | Link |
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| CN (1) | CN113380725A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116454035A (en) * | 2023-06-09 | 2023-07-18 | 江苏芯德半导体科技有限公司 | Flip chip packaging structure and preparation method thereof |
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| WO2020199043A1 (en) * | 2019-03-29 | 2020-10-08 | 华为技术有限公司 | Packaged chip and packaged chip manufacturing method |
| CN112271170A (en) * | 2020-10-27 | 2021-01-26 | 苏州通富超威半导体有限公司 | Packaging substrate, flip chip packaging structure and manufacturing method thereof |
| CN112542427A (en) * | 2020-11-19 | 2021-03-23 | 苏州通富超威半导体有限公司 | Chip packaging structure |
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2021
- 2021-04-29 CN CN202110477284.3A patent/CN113380725A/en active Pending
Patent Citations (7)
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| WO2020199043A1 (en) * | 2019-03-29 | 2020-10-08 | 华为技术有限公司 | Packaged chip and packaged chip manufacturing method |
| CN210668340U (en) * | 2019-12-03 | 2020-06-02 | 星科金朋半导体（江阴）有限公司 | Heat radiation structure of base plate |
| CN111584478A (en) * | 2020-05-22 | 2020-08-25 | 甬矽电子(宁波)股份有限公司 | Laminated chip packaging structure and laminated chip packaging method |
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| CN116454035A (en) * | 2023-06-09 | 2023-07-18 | 江苏芯德半导体科技有限公司 | Flip chip packaging structure and preparation method thereof |
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