CN204834611U - Lead frame and unit, semiconductor package structure and unit thereof - Google Patents
Lead frame and unit, semiconductor package structure and unit thereof Download PDFInfo
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- CN204834611U CN204834611U CN201520558216.XU CN201520558216U CN204834611U CN 204834611 U CN204834611 U CN 204834611U CN 201520558216 U CN201520558216 U CN 201520558216U CN 204834611 U CN204834611 U CN 204834611U
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- lead frame
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- step trough
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model provides a lead frame and unit, semiconductor package structure and unit thereof, lower extreme to the side of the week of lead frame unit is equipped with the ladder groove, the surface in the ladder groove of semiconductor package unit is equipped with additional metal level, ladder flute profile in the lead frame between adjacent two lead frame units becomes the open slot, the surface of the open slot of semiconductor package structure and the surface in ladder groove all are equipped with additional metal level. The utility model provides the electric connection performance of the semiconductor package unit that high cutting back formed.
Description
Technical field
The utility model relates to technical field of semiconductor encapsulation, particularly a kind of lead frame that electrical connection properties is stronger when assembling or a kind of lead frame unit that electrical connection properties is stronger when assembling, the semiconductor package that when being also a kind of assembling, electrical connection properties is stronger, especially a kind of semiconductor packages unit that electrical connection properties is stronger when assembling.
Background technology
Lead frame is basic material conventional in semiconductor packages, using lead frame as prop carrier and electric signal transmission carrier in encapsulation, usually by the central welding disking area of chip attach in lead frame, by wire bonding, the pin of chip is connected with the pin of lead frame, thus realizes electric signal transmission.In numerous encapsulated type, QFN (QuadFlatNon-leadedPackage, QFN) quad flat non-pin package, it is packaging technology more advanced in semiconductor packages in recent years, belong to the one of CSP (ChipScalePackage) wafer-level package kind, it is also adopt lead frame to encapsulate as carrier, using epoxy resin as encapsulant, product after encapsulation is square, matrix center is provided with heat dissipation metal district, and pin is square, and to be arranged in base bottom heat dissipation metal district peripheral for apportion.
Fig. 6 is typical lead frame structure schematic diagram, Figure 12 is the cutaway view after the encapsulation of typical QFN product, as shown in Fig. 6 and Figure 12, the pin 12 of lead frame 11 is arranged evenly in the surrounding of central pad area 16, the centre of central authorities' pad area 16 and pin 12 is space 18, adjacent two lead frame unit 110 places are provided with intercell connector 14, are connected to each other to make several lead frame unit 110.
Fig. 7 is the cutaway view of Fig. 6 along A-A ' line, Fig. 8 is glue coated layer 20 on central pad area 16, then naked wafer 22 is sticked on glue-line 20, carry out wire bonding afterwards, utilize lead-in wire 24 to couple together the pin 12 of the miniature weld pad (not shown) on naked wafer 22 and lead frame 11.
Then plastic packaging is carried out to the finished product shown in Fig. 8, as shown in Figure 9, wherein, naked wafer 22 and lead-in wire 24 all coated by plastic packaging material, in the space 18 between the pin 12 and central pad area 16 of lead frame 11, be also filled with plastic packaging layer 26, the bottom surface of pin 12 and central pad area 16 is exposed.
Again metal cladding is carried out to the finished product shown in Fig. 9, be generally zinc-plated, as shown in Figure 10, to whole lead frame electrotinning, make the bottom surface of the coated all pins 12 of metal level 28 and central pad area 16, to lead frame carry out zinc-plated object be in order to follow-up further assemble with other electric device modules time, can be electrically connected in other electric device module.
Finally cut the finished product shown in Figure 10, as shown in figure 11, after cutting, the lead frame unit 110 be connected to each other is separated from each other, forms final single semiconductor packages unit.
The shortcoming of this technique of prior art is, pin side 30 after cutting cannot plate tin material, the electrical connection properties of semiconductor packages unit when this can reduce assembling, and then affect the reliability of whole electrical appliance module, have higher industry of being more strict with as automotive electronics series products for some to properties of product, the structure of this semiconductor packages unit then cannot meet its requirement to properties of product.
Utility model content
In order to improve the electrical connection properties of the rear semiconductor packages unit formed of cutting, the utility model provides a kind of lead frame and unit, semiconductor package and unit thereof, the pin side of the described semiconductor packages unit after cutting is made also to have additional metal layer, thus the electrical connection properties of the semiconductor packages unit formed after improving cutting.
The utility model solves the technical scheme that its technical problem adopts: a kind of lead frame unit, the lower end outside the pin of described lead frame unit is provided with step trough.
The degree of depth of step trough is 60% to 90% of the thickness of pin.
The degree of depth of step trough is 75% of the thickness of pin.
The surface of step trough comprises bottom surface and side, and the angle between bottom surface and side is more than or equal to 90 °.
The utility model additionally provides a kind of semiconductor packages unit, comprise foregoing lead frame unit, the central pad area of this lead frame unit is fixed with successively glue-line and naked wafer, naked wafer is arranged on glue-line, by lead-in wire electrical connection between naked wafer and pin, described semiconductor packages unit also comprises the plastic packaging layer for encapsulating naked wafer and lead-in wire, be connected and fixed by plastic packaging layer between central authorities' pad area and pin, the lower surface of pin, the lower surface of central pad area and the surface of step trough are equipped with additional metal layer.
Additional metal layer is tin coating, and the thickness of this tin coating is 0.01mm to 0.03mm.
The utility model additionally provides a kind of lead frame, comprise multiple foregoing lead frame unit, intercell connector is provided with between the step trough of two adjacent lead frame unit, intercell connector and two step troughs be connected with this intercell connector form open slot, and the width of open slot is greater than the width of intercell connector.
The surface of step trough comprises bottom surface and side, and the upper surface of intercell connector and the upper surface of pin are positioned at same plane, and the lower surface of intercell connector and the bottom surface of step trough are positioned at same plane.
The utility model additionally provides a kind of semiconductor package, containing foregoing lead frame, the central pad area of each lead frame unit of this lead frame is fixed with glue-line and naked wafer successively, naked wafer is arranged on glue-line, by lead-in wire electrical connection between naked wafer and pin, described semiconductor package also comprises the plastic packaging layer for encapsulating naked wafer and lead-in wire, be connected and fixed by plastic packaging layer between central authorities' pad area and pin, the lower surface of pin, the lower surface of central authorities' pad area, the surface of open slot and the surface of step trough are equipped with additional metal layer.
The beneficial effects of the utility model are, step trough is provided with by the lower end of all sides at lead frame unit, or, step trough between two lead frame unit adjacent in lead frame forms open slot, the surface of the open slot of semiconductor package and the surface of step trough is made to be equipped with additional metal layer, that is, the surface of the step trough of the semiconductor packages unit formed after cutting is provided with additional metal layer, thus improves the electrical connection properties of semiconductor packages unit.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the utility model is described further.
Fig. 1 is the structural representation of lead frame unit of the present utility model.
Fig. 2 is the structural representation of semiconductor packages unit of the present utility model.
Fig. 3 is the structural representation of lead frame of the present utility model.
Fig. 4 is the structural representation of semiconductor package of the present utility model.
Fig. 5 is the schematic diagram of semiconductor package of the present utility model cutting.
Fig. 6 is the lead frame structure schematic diagram of prior art.
Fig. 7 is the cutaway view along A-A line in Fig. 6.
Fig. 8 is the connection diagram of lead frame and naked wafer in prior art.
Fig. 9 is the structural representation in prior art after lead frame plastic packaging.
Figure 10 is the structural representation in prior art after lead frame plating additional metal layer.
Figure 11 is the schematic diagram after the cutting of prior art semiconductor package.
Figure 12 is the cutaway view of prior art semiconductor packages unit.
Description of reference numerals:
110. lead frame unit, 11. lead frames, 12. pins, 14. intercell connectors, 15. open slots, 16. central pads, 18. spaces, 20. glue-lines, 22. naked wafers, 24. lead-in wires, 26. plastic packaging layers, 28. additional metal layer, 30. pin sides, 32. step troughs, 321. bottom surfaces, 322. sides.
Embodiment
In order to there be understanding clearly to technical characteristic of the present utility model, object and effect, now contrast accompanying drawing and embodiment of the present utility model is described.
As shown in Figure 1, the utility model proposes a kind of lead frame unit 110, it contains central pad area 16 and multiple pin 12, and multiple pin 12 is arranged on the surrounding of central pad area 16, be provided with space 18 between central authorities' pad area 16 and pin 12, the lower end outside pin 12 is provided with step trough 32.
From aforementioned, the pin side 30 of prior art pin 12 is a plane, the side of the semiconductor packages unit be made up of this lead frame unit is also a plane and cannot plates additional metal layer 28, and at this semiconductor packages unit when assembling, electrical connection properties is lower.For this reason, the lower end of the utility model outside pin 12 is provided with step trough 32, in order to plate additional metal layer 28 in follow-up operation, improves the electrical connection properties of semiconductor packages unit.
The length of step trough 32 on the thickness direction of pin 12 is the degree of depth of step trough 32.In a feasible embodiment, the degree of depth of step trough 32 is 60% to 90% of the thickness of pin 12.Particularly, the degree of depth of step trough 32 is 75% of the thickness of pin 12.The thickness of central authorities' pad area 16 equals the thickness of pin 12.
The surface of step trough 32 comprises bottom surface 321 and side 322, in order to ensure that the side of the semiconductor packages unit be made up of lead frame unit 110 is after plating additional metal layer 28, can show good electrical connection properties when assembling, the angle between bottom surface 321 and side 322 is more than or equal to 90 °.That is, ensure whole side 322 can both assemble time be electrically connected with the external world, and can not hinder by bottom surface 321.
As shown in Figure 2, the utility model proposes a kind of semiconductor packages unit simultaneously, it comprises foregoing lead frame unit 110, the central pad area 16 of this lead frame unit 110 is fixed with successively glue-line 20 and naked wafer 22, naked wafer 22 is arranged on glue-line 20, be electrically connected by lead-in wire 24 between naked wafer 22 and pin 12, described semiconductor packages unit also comprises the plastic packaging layer 26 for encapsulating naked wafer 22 and lead-in wire 24, be connected and fixed by plastic packaging layer 26 between central authorities' pad area 16 and pin 12, the lower surface of pin 12, central authorities' lower surface of pad area 16 and the surface of step trough 32 are equipped with additional metal layer 28.
The lower peripheral of all sides of semiconductor packages unit of the present utility model is provided with the additional metal layer 28 of a circle, when described semiconductor packages unit is assembled, the bottom of its whole all side all can realize being electrically connected with the miscellaneous part of electrical appliance module, the electrical connection properties of described semiconductor packages unit obtains effective raising, can ensure the reliability of whole electrical appliance module.
In a specific embodiment, additional metal layer 28 is tin coating, and the thickness of this tin coating is 0.01mm to 0.03mm.
As shown in Figure 3, the utility model proposes a kind of lead frame 11, it comprises multiple foregoing lead frame unit 110, the surrounding of lead frame unit 110 is provided with intercell connector 14, pin 12 is connected with intercell connector 14, multiple lead frame unit 110 is in the arrangement of regular ranks, intercell connector 14 is provided with between the step trough 32 of two adjacent lead frame unit 110, intercell connector 14 and two step troughs 32 be connected with this intercell connector 14 form open slot 15, intercell connector 14 between two adjacent step troughs 32 is positioned at the top of the open slot 15 that these two adjacent step troughs 32 are formed, the width of open slot 15 is greater than the width of intercell connector 14.The structural representation of the lead frame described in the application is identical with Fig. 6, and Fig. 3 is equivalent to the cutaway view of the lead frame described in the application along A-A direction gained in Fig. 6.
Wherein, the width of step trough 32 refers to the width of the rectangular projection of step trough 32 on the bottom surface of lead frame unit 110; The width of intercell connector 14 refers to the width of the rectangular projection of intercell connector 14 on the bottom surface of lead frame unit 110; The width of open slot 15 refers to the width of the rectangular projection of open slot 15 on the bottom surface of lead frame unit 110.
The surface of step trough 32 comprises bottom surface 321 and side 322, and the upper surface of intercell connector 14 and the upper surface of pin 12 are positioned at same plane, and the lower surface of intercell connector 14 and the bottom surface 321 of step trough 32 are positioned at same plane.
A kind of semiconductor package as shown in Figure 4, it is characterized in that, described semiconductor package contains foregoing lead frame, the central pad area 16 of each lead frame unit 110 of this lead frame 11 is fixed with glue-line 20 and naked wafer 22 successively, naked wafer 22 is arranged on glue-line 20, be electrically connected by lead-in wire 24 between naked wafer 22 and pin 12, the plastic packaging layer 26 also comprised for encapsulating naked wafer 22 and lead-in wire 24 of described semiconductor package, be connected and fixed by plastic packaging layer 26 between central authorities' pad area 16 and pin 12, the lower surface of pin 12, the lower surface of central authorities' pad area 16, the surface of open slot 15 and the surface of step trough 32 are equipped with additional metal layer 28.
When sharing an intercell connector 14 between two lead frame unit 110 adjacent in cutting semiconductor package as shown in Figure 4, as shown in Figure 5, semiconductor packages unit as shown in Figure 3 can be obtained.It can thus be appreciated that, cut away width during intercell connector 14, be less than the width of open slot 15.Because the surface of the lower surface of pin 12, the lower surface of central pad area 16, the surface of open slot 15 and step trough 32 is equipped with additional metal layer 28, the surface of cutting the lower surface of pin 12 of the described semiconductor packages unit of gained, the lower surface of central pad area 16 and step trough 32 is equipped with additional metal layer 28, namely, effectively can improve the electrical connection properties of described semiconductor packages unit, ensure the reliability of whole electrical appliance module.
The foregoing is only the schematic embodiment of the utility model, and be not used to limit scope of the present utility model.Any those skilled in the art, the equivalent variations done under the prerequisite not departing from design of the present utility model and principle and amendment, all should belong to the scope of the utility model protection.And it should be noted that, each part of the present utility model is not limited in above-mentioned overall applicability, the each technical characteristic described in specification of the present utility model can select one to adopt separately or select the multinomial use that combines according to actual needs, therefore, the utility model naturally covers other relevant with this case innovative point and combines and embody rule.
Claims (8)
1. a lead frame unit, it is characterized in that, the lower end in pin (12) outside of described lead frame unit (110) is provided with step trough (32), the surface of step trough (32) comprises bottom surface (321) and side (322), and the angle between bottom surface (321) and side (322) is more than or equal to 90 °.
2. lead frame unit according to claim 1, is characterized in that, the degree of depth of step trough (32) is 60% to 90% of the thickness of pin (12).
3. lead frame unit according to claim 1, is characterized in that, the degree of depth of step trough (32) is 75% of the thickness of pin (12).
4. a semiconductor packages unit, it is characterized in that, described semiconductor packages unit comprises lead frame unit (110) according to claim 1, the central pad area (16) of this lead frame unit (110) is fixed with successively glue-line (20) and naked wafer (22), naked wafer (22) is arranged on glue-line (20), by lead-in wire (24) electrical connection between naked wafer (22) and pin (12), described semiconductor packages unit also comprises the plastic packaging layer (26) for encapsulating naked wafer (22) and lead-in wire (24), be connected and fixed by plastic packaging layer (26) between central authorities' pad area (16) and pin (12), the lower surface of pin (12), the lower surface of central authorities' pad area (16) and the surface of step trough (32) are equipped with additional metal layer (28).
5. semiconductor packages unit according to claim 4, is characterized in that, additional metal layer (28) is tin coating, and the thickness of this tin coating is 0.01mm to 0.03mm.
6. a lead frame, it is characterized in that, described lead frame (11) comprises multiple lead frame unit (110) according to claim 1, intercell connector (14) is provided with between the step trough (32) of two adjacent lead frame unit (110), intercell connector (14) and two step troughs (32) be connected with this intercell connector (14) form open slot (15), and the width of open slot (15) is greater than the width of intercell connector (14).
7. lead frame according to claim 6, it is characterized in that, the surface of step trough (32) comprises bottom surface (321) and side (322), the upper surface of intercell connector (14) and the upper surface of pin (12) are positioned at same plane, and the lower surface of intercell connector (14) and the bottom surface (321) of step trough (32) are positioned at same plane.
8. a semiconductor package, it is characterized in that, described semiconductor package contains the lead frame described in claim 6 or 7, the central pad area (16) of each lead frame unit (110) of this lead frame (11) is fixed with glue-line (20) and naked wafer (22) successively, naked wafer (22) is arranged on glue-line (20), by lead-in wire (24) electrical connection between naked wafer (22) and pin (12), described semiconductor package also comprises the plastic packaging layer (26) for encapsulating naked wafer (22) and lead-in wire (24), be connected and fixed by plastic packaging layer (26) between central authorities' pad area (16) and pin (12), the lower surface of pin (12), the lower surface of central authorities' pad area (16), the surface of open slot (15) and the surface of step trough (32) are equipped with additional additional metal layer (28).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520558216.XU CN204834611U (en) | 2015-07-29 | 2015-07-29 | Lead frame and unit, semiconductor package structure and unit thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520558216.XU CN204834611U (en) | 2015-07-29 | 2015-07-29 | Lead frame and unit, semiconductor package structure and unit thereof |
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| CN204834611U true CN204834611U (en) | 2015-12-02 |
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| CN201520558216.XU Active CN204834611U (en) | 2015-07-29 | 2015-07-29 | Lead frame and unit, semiconductor package structure and unit thereof |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107799475A (en) * | 2016-08-31 | 2018-03-13 | 新光电气工业株式会社 | Lead frame and electronic part apparatus |
| CN108987367A (en) * | 2017-05-31 | 2018-12-11 | 意法半导体公司 | The lead frame of the QFN pre-molded for the side wall that can adhere on each lead with solder |
| CN109037078A (en) * | 2018-06-13 | 2018-12-18 | 南通通富微电子有限公司 | A kind of semiconductor chip packaging method |
| CN109037077A (en) * | 2018-06-13 | 2018-12-18 | 南通通富微电子有限公司 | A kind of semiconductor chip packaging method |
| CN109037183A (en) * | 2018-06-13 | 2018-12-18 | 南通通富微电子有限公司 | A kind of semiconductor chip packaging array and semiconductor chip packaging device |
| CN109065518A (en) * | 2018-06-13 | 2018-12-21 | 南通通富微电子有限公司 | A kind of semiconductor chip packaging array |
| CN109065519A (en) * | 2018-06-13 | 2018-12-21 | 南通通富微电子有限公司 | A kind of semiconductor chip packaging device |
| CN109256367A (en) * | 2018-10-24 | 2019-01-22 | 嘉盛半导体(苏州)有限公司 | Pre-plastic package lead frame, semiconductor package and its unit, packaging method |
| CN109346454A (en) * | 2018-11-08 | 2019-02-15 | 嘉盛半导体(苏州)有限公司 | Leadframe strip, method for packaging semiconductor, semiconductor package and its unit |
-
2015
- 2015-07-29 CN CN201520558216.XU patent/CN204834611U/en active Active
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107799475A (en) * | 2016-08-31 | 2018-03-13 | 新光电气工业株式会社 | Lead frame and electronic part apparatus |
| CN107799475B (en) * | 2016-08-31 | 2023-04-28 | 新光电气工业株式会社 | Lead frame and electronic component device |
| CN108987367A (en) * | 2017-05-31 | 2018-12-11 | 意法半导体公司 | The lead frame of the QFN pre-molded for the side wall that can adhere on each lead with solder |
| CN108987367B (en) * | 2017-05-31 | 2022-06-14 | 意法半导体公司 | QFN premolded leadframe with solder attachable sidewalls on each lead |
| CN109065519A (en) * | 2018-06-13 | 2018-12-21 | 南通通富微电子有限公司 | A kind of semiconductor chip packaging device |
| CN109065518A (en) * | 2018-06-13 | 2018-12-21 | 南通通富微电子有限公司 | A kind of semiconductor chip packaging array |
| CN109037183A (en) * | 2018-06-13 | 2018-12-18 | 南通通富微电子有限公司 | A kind of semiconductor chip packaging array and semiconductor chip packaging device |
| CN109037077B (en) * | 2018-06-13 | 2020-12-25 | 南通通富微电子有限公司 | Semiconductor chip packaging method |
| CN109065519B (en) * | 2018-06-13 | 2020-12-25 | 南通通富微电子有限公司 | Semiconductor chip packaging device |
| CN109037077A (en) * | 2018-06-13 | 2018-12-18 | 南通通富微电子有限公司 | A kind of semiconductor chip packaging method |
| CN109037078A (en) * | 2018-06-13 | 2018-12-18 | 南通通富微电子有限公司 | A kind of semiconductor chip packaging method |
| CN109256367A (en) * | 2018-10-24 | 2019-01-22 | 嘉盛半导体(苏州)有限公司 | Pre-plastic package lead frame, semiconductor package and its unit, packaging method |
| CN109256367B (en) * | 2018-10-24 | 2024-03-22 | 嘉盛半导体(苏州)有限公司 | Pre-plastic package lead frame, semiconductor package structure, unit and package method thereof |
| CN109346454A (en) * | 2018-11-08 | 2019-02-15 | 嘉盛半导体(苏州)有限公司 | Leadframe strip, method for packaging semiconductor, semiconductor package and its unit |
| CN109346454B (en) * | 2018-11-08 | 2023-12-15 | 嘉盛半导体(苏州)有限公司 | Lead frame strip, semiconductor packaging method, semiconductor packaging structure and unit thereof |
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