CN209592024U - 绝缘间隔件和电子设备 - Google Patents
绝缘间隔件和电子设备 Download PDFInfo
- Publication number
- CN209592024U CN209592024U CN201822172340.9U CN201822172340U CN209592024U CN 209592024 U CN209592024 U CN 209592024U CN 201822172340 U CN201822172340 U CN 201822172340U CN 209592024 U CN209592024 U CN 209592024U
- Authority
- CN
- China
- Prior art keywords
- contact
- collets
- conductive via
- insulating spacer
- electronic equipment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
Abstract
本实用新型涉及绝缘间隔件和电子设备。绝缘间隔件提供了在用于电子芯片的封装的第一接触和连接器板的第二接触之间的电连接。绝缘间隔件包括具有彼此平行的直线轴线的导电过孔,导电过孔在第一接触和第二接触之间延伸。用于电子芯片的封装被安装到绝缘间隔件的一侧,并且连接器板被安装到绝缘间隔件的相对的一侧。
Description
技术领域
本公开涉及电子芯片封装,并且更特别地涉及电子芯片封装到印刷电路板的装配和连接。
背景技术
图1是经由焊球300在连接器板200(例如,印刷电路板)上组装的封装100(例如,矩形)的横截面图。封装100可以包括一个或多个电子芯片101(在图1中示出了两个芯片101)。每个芯片101 在其下表面上包括接触101A(图1中仅示出了一个接触101A)。
封装100由互连或引线框架110和例如侧壁120形成,互连或引线框架110形成封装100的基底,侧壁120形成封装100的侧表面。组件通常被包封在环氧树脂130中。树脂130能够保护芯片101免受杂质、短路等的影响。
引线框架110包括在其上表面上的焊盘111以及在其下表面上的接触113(图1中仅示出了一个焊盘111和一个接触113)。每个焊盘111通过过孔和金属化115连接到一个或多个接触113。作为变型,多个焊盘111可以被连接到同一接触113。焊盘111旨在例如经由焊球103连接到芯片101的接触101A。
接触113旨在被连接到印刷电路板200的焊盘,印刷电路板200 在其上表面处包括焊盘201(图1中仅示出了一个焊盘201)。封装的每个接触113经由焊球300被连接到板200的焊盘201。
期望至少部分地改进封装到印刷电路板的连接的元件的某些方面。
实用新型内容
因此,本实用新型提供了用于解决以上技术问题的绝缘间隔件及相关电子设备。
一个实施例提供了一种绝缘间隔件。所述绝缘间隔件用于在用于电子芯片的封装的第一接触和连接器板的第二接触之间提供电连接,所述绝缘间隔件包括具有彼此平行的直线轴线的多个导电过孔,每个导电过孔具有第一端部和第二端部,所述第一端部与所述第一接触中的一个第一接触直接物理和电气接触,所述第二端部与所述第二接触中的一个第二接触直接物理和电气接触。
在一个实施例中,绝缘间隔件进一步包括绝缘块,所述多个导电过孔穿过所述绝缘块,所述绝缘块具有在从100μm至1mm的范围内的厚度。
在一个实施例中,所述导电过孔具有内接在直径在从100μm至1 mm的范围内的圆内的横截面。
在一个实施例中,所述导电过孔具有圆柱形状。
在一个实施例中,所述导电过孔具有圆锥形状。
在一个实施例中,所述导电过孔由金属或者导电合金中的一个制成。
在一个实施例中,绝缘间隔件进一步包括绝缘块,所述多个导电过孔穿过所述绝缘块,所述绝缘块由绝缘树脂形成。
一个实施例提供了一种电子设备。该电子设备包括:电子芯片封装,包括第一接触;印刷电路板,包括第二接触;以及间隔件,被定位在所述电子芯片封装和所述印刷电路板之间;其中所述间隔件包括具有彼此平行的直线轴线的多个导电过孔,每个导电过孔具有第一端部和第二端部,所述第一端部与所述第一接触中的一个第一接触直接物理和电气接触,所述第二端部与所述第二接触中的一个第二接触直接物理和电气接触。
在一个实施例中,该电子设备进一步包括绝缘块,所述多个导电过孔穿过所述绝缘块,所述绝缘块具有在从100μm至1mm的范围内的厚度。
在一个实施例中,所述导电过孔具有内接在直径在从100μm至1 mm的范围内的圆内的横截面。
在一个实施例中,所述导电过孔具有圆柱形状。
在一个实施例中,所述导电过孔具有圆锥形状。
在一个实施例中,所述导电过孔由金属或者导电合金中的一个制成。
在一个实施例中,该电子设备进一步包括绝缘块,所述多个导电过孔穿过所述绝缘块,所述绝缘块由绝缘树脂形成。
在一个实施例中,该电子设备进一步包括显示器,并且其中所述封装包括至少一个光学单元,所述间隔件被定位为将所述光学单元粘附到所述显示器。
一个实施例提供了一种绝缘间隔件,该绝缘间隔件提供了在用于电子芯片的封装和连接器板之间的接触,该绝缘间隔件由具有彼此平行的直线轴线的导电过孔穿过。
根据一个实施例,间隔件具有在从100μm至1mm的范围内的厚度。
根据一个实施例,过孔具有内接在直径在从100μm至1mm的范围内的圆内的横截面。
根据一个实施例,过孔具有圆柱形状。
根据一个实施例,过孔具有圆锥形状。
根据一个实施例,过孔由金属或者导电合金制成。
根据一个实施例,间隔件由绝缘树脂形成。
另一实施例提供了一种包括电子芯片封装、间隔件和印刷电路板的电子设备。
根据一个实施例,该设备包括显示器,并且封装包括至少一个光学单元,间隔件被定位为使光学单元更接近显示器。
本公开的一些实施例的优点在于可以容易地调整间隔件的厚度。
附图说明
在结合附图的特定实施例的以下非限制性描述中将详细讨论前述和其它特征和优点,其中:
前面描述的图1图示封装到印刷电路板的连接的元件的横截面图;
图2是电子设备的横截面图;
图3是图示封装到印刷电路板的连接的其它元件的横截面图;
图4是图示封装到印刷电路板的连接的装置的一个实施例的横截面图;
图5A至图5F是图示图4的设备的连接装置的一个实施例的步骤的简化横截面图;
图6是图示图4的连接装置的备选实施例的横截面图;以及
图7是电子设备的横截面图。
具体实施方式
在不同的附图中,相同的元件用相同的参考标号表示。为清楚起见,仅示出了并且详细描述了对于理解所描述的实施例有用的那些步骤和元件。特别地,没有讨论引线框架110的设计。
在以下描述中,当参考诸如“上”、“下”等的限定相对位置的术语时,参考附图的取向。术语“大约”在本文中用于指定所讨论的值的正负10%的公差,优选地正负5%的公差。
图2是电子设备D(例如,蜂窝电话)的一部分的截面图,其图示使用诸如图1中所使用的设备的一个示例。设备D包括在其上表面的显示器E。图1的组件被布置在电子设备D中,连接器板经由支脚 P位于下表面侧,并且封装100位于显示器侧。在该配置中,封装100 的上表面被布置在与显示器E之间的距离为d处。
在该实施例中,芯片101中的一个芯片是光学单元OP,光学单元OP在其上表面处包括光学传感器或者光学发射器。因此,单元OP 的上表面未被树脂130覆盖,以避免阻止其操作。该设备的缺点是光学单元OP以距离d远离显示器,这可能不利地影响其良好的操作。
因此,期望增加图1的组件的厚度,例如,以便减小图1的实施例中的距离d。封装100和印刷电路板200的厚度通常由制作这些元件的方法来确定,增加连接装置的厚度是增加这种设备的厚度的最方便的解决方案。然而,增加焊球的尺寸将意味着,要考虑高宽比和两个相邻球之间的绝缘,增加封装100的和印刷电路板200的宽度。
图3是经由中介层400和焊球300A、300B在印刷电路板200上装配的图1的封装100的横截面图。球300A和300B是结合图1所说明的焊球300的类型。
中介层400是封装100的互连栅极110的类型的板。因此,中介层400包括在其上表面处的焊盘401以及在其下表面处的接触403。每个焊盘401经由过孔405被连接到一个或多个接触403。
封装100经由焊球300A被装配在中介层上。更特别地,封装100 的每个接触113通过焊球300A被连接到中介层400的焊盘401。
中介层100本身经由球300B被装配在印刷电路板200上。更特别地,中介层400的每个接触403通过球300B被连接到板200的焊盘201。
图3示出了能够使用直径小于图1的配置中所需的直径的两个堆叠球(经由中介层)的解决方案。然而,球的直径以及中介层的厚度只有很小的变化,这取决于其制造方法。此外,添加中介层意味着附加的设计成本。
图4是经由接触间隔件500的一个实施例在印刷电路板200上装配的图1的封装100的一个实施例的横截面图。
间隔件500是由直线型(rectilinear)过孔503穿过的绝缘层501。绝缘层501例如由电绝缘树脂制成,例如,环氧树脂。过孔503全部彼此平行。过孔503例如由金属或导电合金制成,并且具有内接在直径接近接触113的直径的圆内的横截面,例如,直径在从100μm至1mm的范围内,例如,大约300μm。作为示例,过孔503是圆柱形过孔。
间隔件500被定位在封装100和印刷电路板200之间。此外,封装100的每个接触113经由过孔503连接到板200的一个或多个过孔 201。
该实施例的优点在于可以容易地调整间隔件500的厚度。间隔件 500的厚度例如在从100μm至1mm的范围内。
图5A至图5F是图示制造关于图4所描述的封装100的方法的一个实施例的步骤的实施方式的横截面图。
在图5A的步骤中,芯片101被装配在封装100的引线框架110 上,封装100包括焊盘111、接触113和过孔115。更特别地,芯片 101的每个接触101A通过焊球103连接到焊盘111。
由引线框架110和芯片101形成的组件被翻转以将引线框架110 的接触113向上定位。
在图5B的步骤中,绝缘层501被沉积在引线框架110的接触113 上,并且形成间隔件500的绝缘层501。层501的厚度在从100μm至 1mm的范围内,例如,大约600μm。
在图5C的步骤中,形成穿过层501的腔510。每个腔510暴露引线框架110的接触113。然后,层501形成暴露接触113的掩模501。腔510例如借助于激光形成,例如通过TMV(“穿过模具的过孔”) 方法或者通过化学刻蚀形成。
作为变型,可以在层500的沉积期间直接形成腔510。作为一个示例,沉积步骤可以包括使用将树脂注入模具中的工具。
在图5D的步骤中,利用焊球520填充腔510。每个腔510可以根据其尺寸容纳一个或多个焊球520。焊球520例如由金属或导电合金制成。
在图5E的步骤中,焊球520熔化以完全填充腔510,并且形成关于图4所示的过孔503。因此,每个过孔503的端部中的一个端部连接到接触113。
作为变型,可以利用焊膏填充腔510。
例如,选择焊球520的体积以对应于腔510的体积,否则提供平坦化层501的表面以将其降低到过孔503的表面的水平的步骤。
在图5F的步骤中,关于图5E所描述的设备被装配在集成电路卡 200上。更特别地,每个过孔503被连接到集成电路卡的焊盘201。图5E图示被翻转以将芯片101向上定位所获得的设备。
在后续制造步骤中,完成封装100的制造。更具体地,在引线框架110上形成侧壁120,然后利用树脂130填充封装100使能保护芯片101。
该方法的优点在于它适合于多个封装的并行制造。更具体地,通过将多个封装100定位在同一板上,可以在每个封装100上同时形成间隔件500。
图6是图4的间隔件500的备选实施例600的横截面图。间隔件 600通过由过孔603穿过的绝缘层601形成。绝缘层601是关于图4 所描述的层501的类型。过孔603具有圆锥形状,即,它们的上表面具有比其下表面小的面积。
该实施例的优点在于在间隔件制造过程中,它简化了在绝缘层中形成的腔的填充。另一优点在于它使能连接不同尺寸的接触和焊盘。
图7是其中已经布置了图4的组件的图3的设备D的横截面图。通过使间隔件500的厚度与设备D适配,光学单元OP的上表面被定位为抵靠设备D的显示器E。
已经描述了具体实施例。本领域技术人员将想到各种变更和修改。特别地,可以在关于图5A所描述的步骤之前的步骤期间布置侧壁120和树脂130。
这种变更、修改和改进旨在成为本公开的一部分,并且旨在处于本实用新型的精神和范围内。相应地,前述描述只是以示例的方式,并且不旨在限制。本实用新型仅如随附的权利要求及其等同所限定的那样被限制。
Claims (15)
1.一种绝缘间隔件,其特征在于,所述绝缘间隔件用于在用于电子芯片的封装的第一接触和连接器板的第二接触之间提供电连接,所述绝缘间隔件包括具有彼此平行的直线轴线的多个导电过孔,每个导电过孔具有第一端部和第二端部,所述第一端部与所述第一接触中的一个第一接触直接物理和电气接触,所述第二端部与所述第二接触中的一个第二接触直接物理和电气接触。
2.根据权利要求1所述的绝缘间隔件,其特征在于,进一步包括绝缘块,所述多个导电过孔穿过所述绝缘块,所述绝缘块具有在从100μm至1mm的范围内的厚度。
3.根据权利要求1所述的绝缘间隔件,其特征在于,所述导电过孔具有内接在直径在从100μm至1mm的范围内的圆内的横截面。
4.根据权利要求1所述的绝缘间隔件,其特征在于,所述导电过孔具有圆柱形状。
5.根据权利要求1所述的绝缘间隔件,其特征在于,所述导电过孔具有圆锥形状。
6.根据权利要求1所述的绝缘间隔件,其特征在于,所述导电过孔由金属或者导电合金中的一个制成。
7.根据权利要求1所述的绝缘间隔件,其特征在于,进一步包括绝缘块,所述多个导电过孔穿过所述绝缘块,所述绝缘块由绝缘树脂形成。
8.一种电子设备,其特征在于,包括:
电子芯片封装,包括第一接触;
印刷电路板,包括第二接触;以及
间隔件,被定位在所述电子芯片封装和所述印刷电路板之间;
其中所述间隔件包括具有彼此平行的直线轴线的多个导电过孔,每个导电过孔具有第一端部和第二端部,所述第一端部与所述第一接触中的一个第一接触直接物理和电气接触,所述第二端部与所述第二接触中的一个第二接触直接物理和电气接触。
9.根据权利要求8所述的电子设备,其特征在于,进一步包括绝缘块,所述多个导电过孔穿过所述绝缘块,所述绝缘块具有在从100μm至1mm的范围内的厚度。
10.根据权利要求8所述的电子设备,其特征在于,所述导电过孔具有内接在直径在从100μm至1mm的范围内的圆内的横截面。
11.根据权利要求8所述的电子设备,其特征在于,所述导电过孔具有圆柱形状。
12.根据权利要求8所述的电子设备,其特征在于,所述导电过孔具有圆锥形状。
13.根据权利要求8所述的电子设备,其特征在于,所述导电过孔由金属或者导电合金中的一个制成。
14.根据权利要求8所述的电子设备,其特征在于,进一步包括绝缘块,所述多个导电过孔穿过所述绝缘块,所述绝缘块由绝缘树脂形成。
15.根据权利要求8所述的电子设备,其特征在于,进一步包括显示器,并且其中所述封装包括至少一个光学单元,所述间隔件被定位为将所述光学单元粘附到所述显示器。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1850083A FR3076659B1 (fr) | 2018-01-05 | 2018-01-05 | Entretoise isolante de reprise de contacts |
FR1850083 | 2018-01-05 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN209592024U true CN209592024U (zh) | 2019-11-05 |
Family
ID=62067657
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201811581385.XA Pending CN110010581A (zh) | 2018-01-05 | 2018-12-24 | 绝缘接触间隔件 |
CN201822172340.9U Active CN209592024U (zh) | 2018-01-05 | 2018-12-24 | 绝缘间隔件和电子设备 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201811581385.XA Pending CN110010581A (zh) | 2018-01-05 | 2018-12-24 | 绝缘接触间隔件 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20190214274A1 (zh) |
CN (2) | CN110010581A (zh) |
FR (1) | FR3076659B1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110010581A (zh) * | 2018-01-05 | 2019-07-12 | 意法半导体(格勒诺布尔2)公司 | 绝缘接触间隔件 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI711131B (zh) * | 2019-12-31 | 2020-11-21 | 力成科技股份有限公司 | 晶片封裝結構 |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6075710A (en) * | 1998-02-11 | 2000-06-13 | Express Packaging Systems, Inc. | Low-cost surface-mount compatible land-grid array (LGA) chip scale package (CSP) for packaging solder-bumped flip chips |
US6406939B1 (en) * | 1998-05-02 | 2002-06-18 | Charles W. C. Lin | Flip chip assembly with via interconnection |
JP2002076615A (ja) * | 2000-08-31 | 2002-03-15 | Asahi Chem Res Lab Ltd | プリント配線基板及びそのスルーホールへの半田付け方法 |
US6791035B2 (en) * | 2002-02-21 | 2004-09-14 | Intel Corporation | Interposer to couple a microelectronic device package to a circuit board |
JP2004356618A (ja) * | 2003-03-19 | 2004-12-16 | Ngk Spark Plug Co Ltd | 中継基板、半導体素子付き中継基板、中継基板付き基板、半導体素子と中継基板と基板とからなる構造体、中継基板の製造方法 |
CN1792126A (zh) * | 2003-05-19 | 2006-06-21 | 大日本印刷株式会社 | 双面布线基板和双面布线基板的制造方法以及多层布线基板 |
KR101107976B1 (ko) * | 2004-02-04 | 2012-01-30 | 이비덴 가부시키가이샤 | 다층프린트배선판 |
JP2005236220A (ja) * | 2004-02-23 | 2005-09-02 | Dainippon Printing Co Ltd | 配線基板と配線基板の製造方法、および半導パッケージ |
KR100792352B1 (ko) * | 2006-07-06 | 2008-01-08 | 삼성전기주식회사 | 패키지 온 패키지의 바텀기판 및 그 제조방법 |
US20080284037A1 (en) * | 2007-05-15 | 2008-11-20 | Andry Paul S | Apparatus and Methods for Constructing Semiconductor Chip Packages with Silicon Space Transformer Carriers |
JP2010157690A (ja) * | 2008-12-29 | 2010-07-15 | Ibiden Co Ltd | 電子部品実装用基板及び電子部品実装用基板の製造方法 |
JP5644242B2 (ja) * | 2009-09-09 | 2014-12-24 | 大日本印刷株式会社 | 貫通電極基板及びその製造方法 |
FR2953063B1 (fr) * | 2009-11-20 | 2012-08-24 | St Microelectronics Tours Sas | Procede d'encapsulation de composants electroniques sur tranche |
US8405229B2 (en) * | 2009-11-30 | 2013-03-26 | Endicott Interconnect Technologies, Inc. | Electronic package including high density interposer and circuitized substrate assembly utilizing same |
US8053283B2 (en) * | 2010-03-25 | 2011-11-08 | International Business Machines Corporation | Die level integrated interconnect decal manufacturing method and apparatus |
US8584354B2 (en) * | 2010-08-26 | 2013-11-19 | Corning Incorporated | Method for making glass interposer panels |
US20130242493A1 (en) * | 2012-03-13 | 2013-09-19 | Qualcomm Mems Technologies, Inc. | Low cost interposer fabricated with additive processes |
JP2013206937A (ja) * | 2012-03-27 | 2013-10-07 | Kyocer Slc Technologies Corp | 配線基板およびその製造方法 |
TWI467723B (zh) * | 2012-09-26 | 2015-01-01 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
US9691693B2 (en) * | 2013-12-04 | 2017-06-27 | Invensas Corporation | Carrier-less silicon interposer using photo patterned polymer as substrate |
FR3018953B1 (fr) * | 2014-03-19 | 2017-09-15 | St Microelectronics Crolles 2 Sas | Puce de circuit integre montee sur un interposeur |
US9666559B2 (en) * | 2014-09-05 | 2017-05-30 | Invensas Corporation | Multichip modules and methods of fabrication |
CN104409364B (zh) * | 2014-11-19 | 2017-12-01 | 清华大学 | 转接板及其制作方法、封装结构及用于转接板的键合方法 |
US20160343646A1 (en) * | 2015-05-21 | 2016-11-24 | Qualcomm Incorporated | High aspect ratio interconnect for wafer level package (wlp) and integrated circuit (ic) package |
CN106973495B (zh) * | 2017-05-04 | 2019-12-13 | 奇酷互联网络科技(深圳)有限公司 | 一种印刷电路板的内层电路调试方法 |
FR3076659B1 (fr) * | 2018-01-05 | 2020-07-17 | Stmicroelectronics (Grenoble 2) Sas | Entretoise isolante de reprise de contacts |
-
2018
- 2018-01-05 FR FR1850083A patent/FR3076659B1/fr not_active Expired - Fee Related
- 2018-12-24 CN CN201811581385.XA patent/CN110010581A/zh active Pending
- 2018-12-24 CN CN201822172340.9U patent/CN209592024U/zh active Active
-
2019
- 2019-01-04 US US16/240,220 patent/US20190214274A1/en not_active Abandoned
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110010581A (zh) * | 2018-01-05 | 2019-07-12 | 意法半导体(格勒诺布尔2)公司 | 绝缘接触间隔件 |
Also Published As
Publication number | Publication date |
---|---|
FR3076659B1 (fr) | 2020-07-17 |
FR3076659A1 (fr) | 2019-07-12 |
CN110010581A (zh) | 2019-07-12 |
US20190214274A1 (en) | 2019-07-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6611052B2 (en) | Wafer level stackable semiconductor package | |
KR101484494B1 (ko) | 반도체 디바이스 및 사전에 제조된 커넥터를 패키징하는 방법 | |
JP5042623B2 (ja) | 半導体デバイス | |
US6528869B1 (en) | Semiconductor package with molded substrate and recessed input/output terminals | |
US20030006494A1 (en) | Thin profile stackable semiconductor package and method for manufacturing | |
US9496210B1 (en) | Stackable package and method | |
US20070096265A1 (en) | Multiple die integrated circuit package | |
US20070096284A1 (en) | Methods for a multiple die integrated circuit package | |
JP5615936B2 (ja) | パネルベースのリードフレームパッケージング方法及び装置 | |
TW201644024A (zh) | 晶片封裝結構及其製造方法 | |
CN101996896A (zh) | 半导体器件及其制造方法 | |
CN101194360A (zh) | 接插件及半导体装置 | |
CN211150513U (zh) | 封装体 | |
US9129975B2 (en) | Method of forming a thin substrate chip scale package device and structure | |
US9653414B2 (en) | Shielded QFN package and method of making | |
US11257765B2 (en) | Chip package structure including connecting posts and chip package method | |
CN112310063A (zh) | 半导体装置封装及其制造方法 | |
CN209592024U (zh) | 绝缘间隔件和电子设备 | |
US20040012928A1 (en) | High-power ball grid array package, heat spreader used in the BGA package and method for manufacturing the same | |
US8723313B2 (en) | Semiconductor package structure and method for manufacturing the same | |
KR20130015393A (ko) | 반도체 패키지 및 이의 제조 방법 | |
KR101653563B1 (ko) | 적층형 반도체 패키지 및 이의 제조 방법 | |
CN112018055B (zh) | 电磁屏蔽散热封装结构及其制备方法 | |
CN104916599A (zh) | 芯片封装方法和芯片封装结构 | |
JP2014086963A (ja) | パッケージおよびパッケージの製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GR01 | Patent grant | ||
GR01 | Patent grant |