CN207068843U - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN207068843U
CN207068843U CN201720758267.6U CN201720758267U CN207068843U CN 207068843 U CN207068843 U CN 207068843U CN 201720758267 U CN201720758267 U CN 201720758267U CN 207068843 U CN207068843 U CN 207068843U
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layer
film
conductor
semiconductor devices
diaphragm
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矢岛明
山田义明
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Renesas Electronics Corp
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Renesas Electronics Corp
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Abstract

本实用新型涉及半导体器件，能够提高半导体器件的可靠性。半导体器件具有：半导体衬底(1)；导体层(RM)，形成在半导体衬底(1)上、且具有上表面及下表面；导体柱(CP)，在导体层(RM)的上表面上形成，且具有上表面、下表面及侧壁；保护膜(16)，覆盖导体层(RM)的上表面，且具有露出导体柱(CP)上表面及侧壁的开口(16a)；及覆盖导体柱(CP)的侧壁的保护膜(SW)。而且，在俯视中，保护膜(16)的开口(16a)大于导体柱(CP)的上表面，并露出导体柱(CP)的上表面的整个区域。

Description

半导体器件
技术领域
本实用新型涉及在半导体器件，例如涉及在包含具有再布线(再配置的布线)的半导体芯片的半导体器件中应用的有效技术。
背景技术
美国专利第8441124号说明书(专利文献1)中公开了，为了防止在UBM层之上形成的Cu柱的氧化及UBM层的侵蚀(undercut)，在Cu柱的侧壁上形成保护膜，并且使UBM层的宽度大于Cu柱的宽度。
现有技术文献
专利文献
专利文献1：美国专利第8441124号说明书
实用新型内容
实用新型要解决的技术问题
本申请的发明人研究的半导体芯片的凸块电极按以下方式构成。
在由半导体衬底上的布线层所形成的焊盘电极上形成晶种膜(seed film)后，在晶种膜上形成抗蚀膜，所述抗蚀膜在形成凸块电极的区域开口，利用镀覆法形成由镀Cu膜形成的圆柱形的接线柱电极(post electrode)(导体柱，Cu柱)，在将抗蚀膜除去后，将向接线柱电极的外侧延伸的晶种膜蚀刻除去。然后，向接线柱电极上供给球状的焊料球，并实施凸块电极形成用回流焊，从而将焊料球熔融、并在接线柱电极的上表面上形成焊料球电极，从而完成半导体芯片的凸块电极。
进一步地，在布线衬底的端子上设置预焊料(日文：迎え半田)后，将半导体芯片搭载于布线衬底上。在凸块电极隔着预焊料而配置在布线衬底的端子上的状态下，通过实施封装用的回流焊(热处理)，从而将凸块电极接合于端子，从而完成包含具有凸块电极的半导体芯片的半导体器件。
本申请的发明人在上述半导体器件的研究阶段中，认识到以下问题。
由硅等构成的半导体芯片搭载于由玻璃环氧树脂形成的布线衬底上，由于半导体器件的设置环境或半导体芯片工作时的发热，从而对将两者间连接的凸块电极施加应力，由此在后述的半导体芯片的表面保护膜或层间绝缘膜等中产生裂纹。特别的，当作为层间绝缘膜而使用了低介电常数的Low-k材的情况下，由于其脆弱性的缘故，产生裂纹的概率高。
根据本申请的发明人的研究探明了：若实施封装用的回流焊，焊料球或预焊料、或构成上述两者的焊料(特别地，锡(Sn))向接线柱电极的侧壁流出，到达半导体芯片的焊盘电极。还认识到，锡(Sn)的硬度比铜(Cu)的硬度还高，向接线柱电极的侧壁流出的焊料部分地存在于侧壁，因此发生应力局部地集中于焊盘电极的现象，且在半导体芯片的表面保护膜或层间绝缘膜等中产生裂纹、耐湿性降低，或布线发生断线等问题。
也就是说，在具有凸块电极的半导体器件中，需要可靠性的提高或性能的提高。
由本说明书的记述及所附附图，能够明了其他问题及新颖的特征。
用于解决问题的手段
一个实施方式中的半导体器件具有：半导体衬底；导体层，所述导体层在半导体衬底上形成、且具有第一上表面及第一下表面；导体柱，所述导体柱形成在导体层的第一上表面上，且具有第二上表面、第二下表面及侧壁；绝缘膜，所述绝缘膜覆盖导体层的第一上表面，且具有露出导体柱的第二上表面及侧壁的开口；及保护膜，所述保护膜覆盖导体柱的侧壁。而且，在俯视中，绝缘膜的开口大于导体柱的第二上表面，并露出第二上表面的整个区域。
实用新型效果
根据一个实施方式，能够提高半导体器件的可靠性。
附图说明
图1：为实施方式中的半导体器件的上表面图。
图2：为实施方式中的半导体器件的侧面图。
图3：为实施方式中的半导体器件的下表面图。
图4：为实施方式中的半导体器件的部分剖面图。
图5：为本实施方式的半导体芯片的俯视图。
图6：为图5的A部的扩大俯视图。
图7：为示出本实施方式的半导体器件的制造工序的一部分的工艺流程图。
图8：为本实施方式的半导体器件的制造工序中的主要部分剖面图。
图9：为接着图8的、半导体器件的制造工序中的主要部分剖面图。
图10：为接着图9的、半导体器件的制造工序中的主要部分剖面图。
图11：为接着图10的、半导体器件的制造工序中的主要部分剖面图。
图12：为接着图11的、半导体器件的制造工序中的主要部分剖面图。
图13：为接着图12的、半导体器件的制造工序中的主要部分剖面图。
图14：为示出本实施方式的半导体器件的制造工序中的一个工序的详情的工艺流程图。
图15：为接着图13的、半导体器件的制造工序中的主要部分剖面图。
图16：为接着图15的、半导体器件的制造工序中的主要部分剖面图。
图17：为接着图16的、半导体器件的制造工序中的主要部分剖面图。
图18：为接着图17的、半导体器件的制造工序中的主要部分剖面图。
图19：为接着图18的、半导体器件的制造工序中的主要部分剖面图。
图20：为示出变形例1的半导体器件的制造工序的一部分的工艺流程图。
图21：为变形例1的半导体器件的制造工序中的主要部分剖面图。
图22：为示出变形例2的半导体器件的制造工序的一部分的工艺流程图。
图23：为变形例2的半导体器件的制造工序中的主要部分剖面图。
图24：为变形例2的半导体器件的制造工序中的主要部分剖面图。
附图标记说明
1 半导体衬底
2Pp 型阱
2Nn 型阱
3 元件分离槽
3a 元件分离膜
4、6、8 层间绝缘膜
5 第一层Cu布线
5a 绝缘膜
7 第二层Cu布线
9 第三层Al布线
10 表面保护膜
10a 开口
11 保护膜
11a 开口
12 晶种层
13a、13b 掩膜层
13aa、13bb 开口
14、15 镀膜
16 保护膜
16a 开口
19 预焊料(迎接焊料)
20 焊料层
BE1、BE2 凸块电极
BF 阻隔层
CHP 半导体芯片
CL 芯层
CP 导体柱
LND 末端
ML11、ML12 金属层
ML21、ML22、ML23 金属层
p1、p2、p3 插塞
PA 焊盘电极
PB 探针
Qnn 沟道型MIS晶体管
Qpp 沟道型MIS晶体管
RM 导体层(再布线)
SA 半导体器件
SB 衬底用焊料球
SBC、SBC1 焊料球电极
SR1、SR2 阻焊膜
SW 保护膜
TA 端子
UC 侵蚀
UF 密封材料(底层填料)
WB 布线衬底
WL1、WL2、WL3 布线
具体实施方式
在以下实施方式中，为了方便，在必要时分割成多个部分或实施方式来说明，但除了特别明示的情况之外，它们之间并不是毫无关系的，而是一方为另一方的部分或全部的变形例、详情、补充说明等关系。
另外，在以下实施方式中，提到要素的数等(包括个数、数值、量、范围等)时，除了特别明示的情况以及在原理上明确限定为特定数的情况等之外，均不限定于该特定数，可以是特定数以上也可以是特定数以下。
而且，在以下实施方式中，除了特别明示的情况以及被认为原理上明确是必须的情况等之外，其构成要素(还包括要素步骤等)当然并非一定是必须的。
相同地，在以下实施方式中，涉及到构成要素等的形状、位置关系等时，除了特别明示的情况和认为原理上明确不成立的情况等之外，包括实质上与该形状等近似或类似的情况等。在这点上，对于上述数等(包括个数、数值、量、范围等)也是同样的。
另外，在用于说明实施方式的全部附图中，对具有同一功能的部件原则上标注同一符号，省略对其的重复说明。需要说明的是，也存在为了易于观察附图而在俯视图中也标注了剖面线的情况。
(实施方式)
＜半导体器件的结构＞
图1为本实施方式中的半导体器件的上表面图。图2为本实施方式中的半导体器件的侧面图。图3为本实施方式中的半导体器件的下表面图。图4为本实施方式中的半导体器件的部分剖面图。图5为本实施方式的半导体芯片的俯视图。图6为图5的A部的扩大俯视图。图16为沿图6的A-A线的剖面图。
如图1所示，本实施方式中的半导体器件SA具有矩形(例如，正方形)的布线衬底WB，在该布线衬底WB的中央部隔着密封材料(底层填料)UF而搭载有矩形(例如，长方形)的半导体芯片CHP。如图1所示，半导体芯片CHP的尺寸小于布线衬底WB的尺寸。
然后，如图2所示，本实施方式中的半导体器件SA具有布线衬底WB，在该布线衬底WB的背面(下表面)上形成有多个衬底用焊料球SB。另一方面，布线衬底WB的表面(主表面，上表面)上搭载半导体芯片CHP，在该半导体芯片CHP上形成有多个凸块电极BE2。该凸块电极BE2的高度例如为40μm～200μm程度。并且，半导体芯片CHP与布线衬底WB经上述凸块电极BE2而电连接。需要说明的是，如图2所示，由于凸块电极BE2的存在而产生的、半导体芯片CHP与布线衬底WB之间的间隙中填充有密封材料UF。密封材料UF与半导体芯片CHP的主表面、布线衬底WB的表面、及凸块电极BE2的侧面(表面)接触。
接着，如图3所示，在布线衬底WB的背面上以阵列状配置有多个衬底用焊料球SB。图3中，示出了沿例如布线衬底WB的外周部(外缘部)，以4列配置衬底用焊料球SB的例子。上述这些衬底用焊料球SB作为用于将半导体器件SA与外部设备连接的外部连接端子而发挥功能。即，关于衬底用焊料球SB，在将半导体器件SA搭载于例如以主板(mother board)为代表的电路衬底时而使用。关于衬底用焊料球SB，也可以在遍及布线衬底WB的背面的整个面的范围内以矩阵状配置。
图4为本实施方式中的半导体器件SA的部分剖面图。布线衬底WB采取多层布线结构，但在图4中，分别将芯层CL、和芯层CL的表面侧的布线WL1及背面侧的布线WL2仅示出了一层。关于形成于芯层CL的表面侧的布线WL1，其上表面及侧面由阻焊膜SR1(solderresist membrane)被覆。形成于布线WL1的一部分的端子TA在设置于阻焊膜SR1的开口部处从阻焊膜SR1露出，并且，在该开口部处，凸块电极BE2连接于端子TA。关于形成于芯层CL的背面侧的布线WL2，其上表面及侧面由阻焊膜SR2被覆。形成于布线WL2的一部分的连接盘(日文：ランド)LND在设置于阻焊膜SR2的开口部处从阻焊膜SR2露出，在该开口部处，衬底用焊料球SB连接于连接盘LND。表面的布线WL1经由设置在贯通芯层CL的通路内的布线WL3，而与背面的布线WL2连接。阻焊膜SR1及SR2为由绝缘性的树脂构成的绝缘膜，芯层CL由将例如玻璃环氧树脂等制成绝缘层的树脂衬底构成。
在布线衬底WB上搭载半导体芯片CHP，连接于(在半导体芯片CHP的主表面上形成的)导体层(再布线，再配置的布线)RM的凸块电极BE2与从阻焊膜SR1露出的端子TA连接。而且，向半导体芯片CHP与布线衬底WB的间隙填充有密封材料UF。也就是说，以半导体芯片CHP的主表面与布线衬底WB的表面相对的方式，半导体芯片CHP经由凸块电极BE2而搭载于布线衬底WB的表面上。而且，半导体芯片CHP的主表面与布线衬底WB的表面之间由密封材料UF完全包埋，多个凸块电极BE2间也由密封材料UF完全包埋。也就是说，凸块电极BE2的侧壁(侧面，表面)在整个周围与密封材料UF接触。关于密封材料UF，例如，出于对凸块电极BE2与端子TA的接合部所承受的应力进行缓和的目的而设置，且由例如环氧树脂等绝缘性树脂膜构成。凸块电极BE2表示处于半导体芯片CHP连接于布线衬底WB的状态下的凸块电极。另一方面，如图5及图6中所示，在将半导体芯片CHP连接于布线衬底WB之前，在半导体芯片CHP的主表面形成的凸块电极为凸块电极BE1。在俯视中，凸块电极BE1与BE2处于对应的位置上。
在图5所示的半导体芯片CHP的主表面上，在其周缘部以1列配置有焊盘电极PA。分别沿由长方形构成的主表面的2个长边及2个短边的各边，配置1列焊盘电极PA，从而构成环状的焊盘电极PA的列。而且，在环状的焊盘电极PA的列的内侧，多个凸块电极BE1在X方向及Y方向上以行列状配置，从而整体上构成凸块电极BE1的组。上述的、各自具有圆形的多个凸块电极BE1在X方向或Y方向上以分别相等的节距配置。图5的圆形记号均为凸块电极BE1。焊盘电极PA还能够沿各边配置2列、或2列的锯齿配置。半导体芯片CHP也可以为正方形。
各个焊盘电极PA与凸块电极BE1由未图示的导体层RM连接，导体层RM从半导体芯片CHP的周缘部向中央部延伸。也就是说，使用导体层RM，将配置于半导体芯片CHP的周缘部的焊盘电极PA再配置于在半导体芯片CHP的中央部的区域配置的凸块电极BE1。邻接的凸块电极BE1的节距大于邻接的焊盘电极PA的节距。这里，所谓邻接的凸块电极BE1的节距及邻接的焊盘电极PA的节距，分别以最小的节距作为对象。作为半导体芯片CHP的外部连接端子而发挥功能的凸块电极BE1的节距大于焊盘电极PA的节距，由此使其与前述的布线衬底WB之间的连接变得容易。
图6表示图5的A部的焊盘电极PA与凸块电极BE1。如图6所示，焊盘电极PA经由导体层RM而连接于凸块电极BE1。凸块电极BE1具有导体柱CP及焊料球电极SBC。
导体层RM由以下区域构成：作为导体层RM与焊盘电极的连接部的第一区域P1、作为导体层RM与凸块电极的连接部的第三区域P3，及连结第一区域P1及第三区域P3的第二区域P2。
在导体层RM的一端即第一区域P1中，导体层RM经由正方形的开口10a及11a而连接于焊盘电极PA。如后文所述，在剖视中，在焊盘电极PA与导体层PM之间存在表面保护膜10及保护膜11，开口10a形成于表面保护膜10，开口11a形成于保护膜11。在第一区域P1中，导体层RM的一端成为正方形，其一边大于开口10a及11a的一边。另外，导体层RM的一端及开口10a及11a也可以为圆形，但重要的是，导体层RM的一端的直径大于开口10a及11a的直径。
在作为导体层RM的另一端的第三区域P3中，在导体层RM上在保护膜16的开口16a内连接有凸块电极BE1。如后文所述，在剖视中，导体层RM由保护膜16覆盖，但其一部分经由开口16a而从保护膜16露出。而且，在开口16a内，在导体层RM上配置有导体柱CP。
如图6所示，在第三区域P3中，导体层RM成为的圆形，保护膜16的开口16a成为的圆形，导体柱CP成为的圆形。而且，重要的是，设置为 的关系。在导体柱CP的侧壁上在整个外周形成膜厚(t)的保护膜SW，如后文所述，保护膜SW也遍及导体柱CP的高度方向的整个区域、从而在导体柱CP的侧壁上形成。为了在导体柱CP的侧壁上形成保护膜SW，重要的是设置为此外设置为的关系也是重要的。也就是说，如图6所示，在俯视中，导体柱CP及保护膜SW的整个区域位于开口16a的内部，且从保护膜16完全地露出。
另外，在第三区域P3中，导体层RM的外周优选为在遍及整个外周的范围内由保护膜16覆盖，且重要的是设置为 的关系。而且，为了维持的关系，并考虑到保护膜16的加工余量等，优选使导体层RM的比导体柱CP的大10μm以上。
基于以上内容，例如，能够设置为
另外，关于配置于导体柱CP上的球形的焊料球电极SBC的直径，将其设置为大于导体柱CP的而小于开口16a的但也可以将其设为大于开口16a的或导体层RM的
在将第一区域P1及第三区域P3连结的第二区域P2中，导体层RM的宽度(图6的Y方向)比第一区域P1及第三区域P3的导体层RM的宽度(图6的Y方向)窄。在第二区域P2与第三区域P3的边界处，也可以使导体层RM的宽度(图6的Y方向)从第二区域P2向第三区域P3缓缓地或者阶梯式地增加。
如前所述，导体层RM由保护膜16覆盖，但图6中，以直线表示导体层RM。
接下来，使用图16，说明本实施方式的半导体器件的剖面结构。图16示出沿图6的A-A线的剖面图。
如图16所示，在半导体衬底1上形成焊盘电极PA，在半导体衬底1及焊盘电极PA上形成表面保护膜10及保护膜11。表面保护膜10及保护膜11具有露出焊盘电极PA的一部分的开口10a及11a。开口11a的直径比开口10a的直径更大，且在开口10a的整个区域开口。
焊盘电极PA通过由例如铝膜、铝合金膜(AlSi膜，AlCu膜或AlSiCu膜等)或铜膜构成的导体膜构成。当通过铝膜或铝合金膜形成焊盘电极PA时，可在铝膜或铝合金膜的上下设置金属阻隔膜。例如，关于焊盘电极PA，能够设为从下层起为Ti膜/TiN膜/AlCu膜/TiN膜的层叠结构。另外，当通过铜膜形成焊盘电极PA时，可在铜膜之下设置金属阻隔膜、在铜膜之上设置防氧化用的金属阻隔膜。例如，关于焊盘电极PA，能够设为从下层起为TaN膜/Cu膜/Ni膜的层叠结构。
表面保护膜10由无机绝缘膜构成，且由例如氧化硅膜、氮化硅膜、或两者的层叠膜等构成。顺便，在层叠膜的情况中，从下层起依次层叠氧化硅膜、氮化硅膜。表面保护膜10的膜厚优选设为例如1μm以下。
保护膜11由有机绝缘膜构成，例如由膜厚为3～5μm程度的聚酰亚胺膜构成。保护膜11具有防止施加至凸块电极BE1及导体层RM的应力传导至表面保护膜10、半导体芯片CHP等的应力缓和功能。
如图16所示，在表面保护膜10及保护膜11上形成导体层RM，且导体层RM经由表面保护膜10及保护膜11的开口10a及11a而与焊盘电极PA接触并连接。也就是说，在表面保护膜10及保护膜11的开口10a及11a内，导体层RM的下表面与焊盘电极PA的上表面接触。导体层RM由晶种层12、镀膜14及15的层叠膜构成，镀膜14及15在俯视中具有相等的形状。晶种层12在俯视下具有与镀膜14及15大体相等的形状，如后文所述，晶种层12的端部具有从镀膜14的端部稍向内侧(焊盘电极PA侧)后退的形状。也就是说，晶种层12相对于镀膜14而发生了侵蚀。图中未示出，但晶种层12成为阻隔层(其防止焊盘电极PA与导体层RM的反应)与电解镀覆时的镀覆晶种层的层叠结构。阻隔层例如从下方起由钛(Ti)膜、氮化钛(TiN)膜及钛(Ti)膜的层叠膜构成，上述这些膜的膜厚依次设为10nm、50nm及10nm。镀覆晶种层在阻隔层上形成，且由铜膜构成，其膜厚设为100～500nm。镀膜14由铜膜构成，其膜厚为5～20μm程度，镀膜15由镍膜构成，其膜厚设为2～3μm。另外，作为构成晶种层12的阻隔层，可使用钛(Ti)膜、氮化钛(TiN)膜、钛钨(TiW)膜、铬(Cr)膜、钽(Ta)膜、钨(W)膜、氮化钨(WN)膜、高熔点金属膜、贵金属膜(Pd、Ru、Pt、Ni等)。
导体层RM为电阻非常低的布线，且具有比焊盘电极PA的膜厚更厚的(更大的)膜厚。而且，导体层RM的膜厚优选为焊盘电极PA膜厚的5～10倍或以上。
另外，如图16所示，关于导体层RM，其上表面(主表面)及侧壁(侧面)由保护膜16覆盖。保护膜16中形成有用于露出导体层RM的上表面的一部分的开口16a。保护膜16覆盖导体层RM的上表面及侧壁、而导体层RM的肩部等不露出是重要的，且由有机绝缘膜(例如，聚酰亚胺膜)构成，其膜厚设为5～8μm。开口16a的直径为从保护膜16露出的导体层RM的上表面的长度。
在设置于保护膜16的开口16a内，导体层RM连接有导体柱CP，导体柱CP的下表面的整个区域与导体层RM的上表面(镍镀膜15)接触。也就是说，开口16a将导体柱CP的上表面及侧壁(侧面)完全露出。在开口16a内，在导体柱CP的周围、遍及导体柱CP的整个外周地存在从保护膜16露出的导体层RM的上表面。导体柱CP由镀铜膜构成，其膜厚为20μm程度。
如图16及图6所示，在导体柱CP的侧壁上形成保护膜SW，保护膜SW完全覆盖导体柱CP的侧壁。也就是说，在俯视中，在圆形的导体柱CP的高度方向及圆周方向上，覆盖侧壁的整个区域。保护膜SW为含有铜(Cu)的有机膜，且其膜厚为100nm程度。另外，保护膜SW包含铜(Cu)、碳(C)、氮(N)、氢(H)及氧(O)。保护膜SW为酰亚胺与Cu2O的混合层。保护膜SW例如具有防止焊料球电极SBC或后述预焊料19中所含的焊料(例如，Sn)向导体柱CP的侧壁附着的功能。
如图16所示，在导体柱CP的上表面隔着阻隔层BF而形成焊料球电极SBC。焊料球电极SBC为例如3元系的锡(Sn)-银(Ag)-铜(Cu)构成的无铅焊料。具体而言，能够使用具有Sn、1％Ag、0.5％Cu的组成比的焊料。另外，可在焊料中适当进行组成比的改变、或含有铋(Bi)或其他的添加剂。
另外，阻隔层BF由金(Au)、银(Ag)、钯(Pd)等贵金属构成。也就是说，导体柱CP的上表面被由贵金属构成的阻隔层BF覆盖。通过预先由贵金属构成的阻隔层BF覆盖导体柱CP的上表面，在导体柱CP的侧壁上形成保护膜SW时，能够防止在导体柱CP的上表面上形成保护膜SW。作为阻隔层BF，代替贵金属，能够使用例如Pd合金、Au合金、Ag合金等贵金属合金。另外，为了防止焊料球电极SBC或后述的预焊料19中所含的焊料(例如，Sn)向导体柱CP中扩散，优选将阻隔层BF设为防扩散膜与贵金属膜或贵金属合金膜的层叠结构。防扩散膜优选存在于贵金属膜或贵金属合金膜与导体柱CP之间。作为防扩散膜，能够使用镍(Ni)、镍合金。
另外，如图16所示，凸块电极BE1由导体柱CP、阻隔层BF、及焊料球电极SBC构成。
＜半导体器件的制造方法＞
然后，使用图7～图19，说明本实施方式的半导体器件的制造方法。图7及图14为示出本实施方式的半导体器件的制造工序中的一个工序的详情的工艺流程图。图8～图13及图15～图19为本实施方式的半导体器件的制造工序中的主要部分剖面图。
如图8所示，预备(准备)在表面上形成有焊盘电极Pa的半导体芯片CHP(图7的步骤S1)。
如图8所示，在由例如p型的单晶硅构成的半导体衬底1上形成有p型阱2P、n型阱2N及元件分离槽3，且在元件分离槽3的内部埋入由例如氧化硅膜构成的元件分离膜3a。
上述p型阱2P内形成有n沟道型MIS晶体管(Qn)。n沟道型MIS晶体管(Qn)在由元件分离槽3规定的活性区域形成，且具有在p型阱2P内形成的源区域ns及漏区域nd、和在p型阱2P上隔着栅极绝缘膜ni而形成的栅电极ng。另外，上述n型阱2N内形成有p沟道型MIS晶体管(Qp)，p沟道型MIS晶体管(Qp)具有源区域ps及漏区域pd、和在n型阱2N上隔着栅极绝缘膜pi而形成的栅电极pg。
在上述n沟道型MIS晶体管(Qn)及p沟道型MIS晶体管(Qp)的上部形成有连接半导体元件间的、由金属膜形成的布线。连接半导体元件间的布线一般而言具有3层～10层程度的多层布线结构，但作为多层布线的一个例子，图8中示出了以铜合金为主体的金属膜所构成的2层的布线层(第一层Cu布线5、第二层Cu布线7)和以Al合金为主体的金属膜所构成的1层的布线层(第三层Al布线9)。所谓布线层，在将由各布线层形成的多个布线总括表示的情况下使用。关于布线层的膜厚，第二层的布线层比第一层的布线层厚，第三层的布线层比第二层的布线层厚。
在n沟道型MIS晶体管(Qn)及p沟道型MIS晶体管(Qp)与第一层Cu布线5之间、第一层Cu布线5与第二层Cu布线7之间，及第二层Cu布线7与第三层Al布线9之间分别形成有由氧化硅膜等构成的层间绝缘膜4、6、8，及将3层的布线间电连接的插塞p1、p2、p3。
上述层间绝缘膜4以例如覆盖半导体元件的方式在半导体衬底1上形成，第一层Cu布线5在上述层间绝缘膜4上的绝缘膜5a内形成。第一层Cu布线5经由例如在层间绝缘膜4中形成的插塞p1而与作为半导体元件的n沟道型MIS晶体管(Qn)的源区域ns、漏区域nd、栅电极ng电连接。另外，第一层Cu布线5经由在层间绝缘膜4中形成的插塞p1而与作为半导体元件的p沟道型MIS晶体管(Qp)的源区域ps、漏区域pd、栅电极pg电连接。栅电极ng、pg与第一层Cu布线5的连接没有进行图示。插塞p1、p2、p3由金属膜、例如W(钨)膜构成。第一层Cu布线5通过镶嵌(damascene)法而在绝缘膜5a的布线槽内形成，第一层Cu布线5由阻隔导体膜、及其上层的以铜为主体的导体膜的层叠结构构成。阻隔导体膜由钽(Ta)、钛(Ti)、钌(Ru)、钨(W)、锰(Mn)及它们的氮化物、及/或氮化硅化物，或它们的层叠膜构成。以铜为主体的导体膜由铜(Cu)或铜合金(铜(Cu)与铝(Al)、镁(Mg)、钛(Ti)、锰(Mn)、铁(Fe)、锌(Zn)、锆(Zr)、铌(Nb)、钼(Mo)、钌(Ru)、钯(Pd)、银(Ag)、金(Au)、In(铟)、镧系金属、或锕系金属等的合金)形成。
第二层Cu布线7经由在例如层间绝缘膜6内形成的插塞p2而与第一层Cu布线5电连接。第三层Al布线9经由在例如层间绝缘膜8内形成的插塞p3而与第二层Cu布线7电连接。插塞p3由金属膜(例如W(钨)膜)构成。
第二层Cu布线7与插塞p2一体地在层间绝缘膜6内形成，第二层Cu布线7及插塞p2由阻隔导体膜、及其上层的以铜为主体的导体膜的层叠结构构成。并且，阻隔导体膜和以铜为主体的导体膜由与第一层Cu布线5同样的材料构成。
另外，在第一层Cu布线5与层间绝缘膜6之间，及第二层Cu布线7与层间绝缘膜8之间优选设置用于防止铜向层间绝缘膜6或8扩散的阻隔绝缘膜，且阻隔绝缘膜能够使用SiCN膜或SiCN膜与SiCO膜的层叠膜。
另外，第三层Al布线9由铝合金膜(例如，添加有Si及Cu的Al膜)构成，但也可以设为Cu布线。
另外，层间绝缘膜4由氧化硅膜(SiO2)构成，但当然，也可以由包含碳的氧化硅膜(SiOC膜)、包含氮和碳的氧化硅膜(SiCON膜)、包含氟的氧化硅膜(SiOF膜)的单层膜或层叠膜构成。
在作为多层布线的最上层的布线层即上述第三层Al布线9的上部形成有(作为最终钝化膜)例如氧化硅膜、氮化硅膜等的单层膜，或由它们的2层膜构成的表面保护膜(保护膜、绝缘膜)10。而且，在该表面保护膜10内形成的焊盘开口(开口)10a的底部露出的最上层的布线层即第三层Al布线9构成焊盘电极(焊盘、电极焊盘)PA。
然后，如图9所示，在表面保护膜10上形成保护膜(有机绝缘膜)11(图7的步骤S2)。需要说明的是，图9以后，比焊盘电极PA靠下的布线层、晶体管等省略。作为保护膜11而使用感光性聚酰亚胺树脂。在表面保护膜10上进行感光性聚酰亚胺的涂布、曝光及显影，从而使开口10a及焊盘电极PA露出后，进行凝固(cure)(热处理)从而进行固化。也就是说，通过对感光性聚酰亚胺树脂膜进行构图，从而形成具有比开口10a及焊盘电极PA大的开口11a的保护膜11。在俯视中，开口10a及11a为正方形。需要说明的是，开口10a及11a也可以设为圆形。
然后，如图10所示，在保护膜11上形成晶种层12(图7的步骤S3)。晶种层12由阻隔层与阻隔层上的镀覆晶种膜的层叠结构构成。阻隔层例如由溅射法或CVD(Chemical VaporDeposition)法形成钛膜(Ti膜)、氮化钛膜(TiN膜)、及钛膜(Ti膜)，其膜厚设为10nm、50nm、10nm，镀覆晶种膜例如由溅射法形成铜(Cu)膜，其膜厚设为200nm。晶种层12与焊盘电极PA的上表面接触，形成在构成开口10a及11a的表面保护膜10的侧壁及保护膜11的侧壁、以及表面保护膜10的上表面及保护膜11的上表面。
然后，如图10所示，在晶种层12上形成掩膜层(绝缘膜、有机绝缘膜)13a(图7的步骤S4)。作为掩膜层13a，能够使用液态抗蚀剂或干膜抗蚀剂，其膜厚例如为10～30μm。掩膜层13a具有开口13aa，掩膜层13a的开口13aa内包开口11a及10a。在从掩膜层13a露出的开口13aa的内部形成导体层RM。
然后，如图10所示，形成镀膜14及15(图7的步骤S5)。利用电解镀覆法，在掩膜层13a的开口13aa内形成镀膜14及15。通过该电解镀覆工序，晶种层12作为晶种层而发挥功能。镀膜14设为镀铜(Cu)膜，镀膜15设为镀镍(Ni)膜。第一镀膜14将开口10a及11a完全包埋。镀膜15形成后将掩膜层13a。
然后，如图11所示，在导体层RM上形成掩膜层(绝缘膜，有机绝缘膜)13b(图7的步骤S6)。作为掩膜层13b，能够使用液态抗蚀剂或干膜抗蚀剂，该膜厚例如为30～40μm。掩膜层13b具有开口13bb，掩膜层13b的开口13bb不将开口11a及10a内包。
然后，如图11所示，形成导体柱CP及阻隔层BF(图7的步骤S7)。利用电解镀覆法，在作为开口13bb的内部的、从掩膜层13b露出的导体层RM的上表面的一部分上，依次形成导体柱CP用的镀铜(Cu)膜，及阻隔层BF用的镀镍(Ni)膜及镀钯(Pd)膜。在该电解镀覆工序中，晶种层12作为晶种层而发挥功能。在形成阻隔层BF用的镀膜后，除去掩膜层13b。
然后，如图12所示，除去晶种层12(图7的步骤S8)。对将前述的掩膜层13b除去从而露出的晶种层12进行例如湿式蚀刻处理，从而将从镀膜14及15露出的区域的晶种层12除去。由此，形成由镀膜15、镀膜14及晶种层12构成的导体层RM。在该工序中，为了将从镀膜14及15露出的区域的晶种层12完全除去，需要过蚀刻(overetch)。因此，在晶种层12形成侵蚀UC。也就是说，晶种层12的端部从镀膜14及15的端部向内侧方向(焊盘电极PA的方向)后退，因此在保护膜11上形成镀膜14及15的檐。晶种层12的侵蚀UC在遍及导体层RM的整个外周的范围内形成。
然后，如图13所示，形成保护膜16(图7的步骤S9)。需要说明的是，上述工序的详情使用图14的工艺流程图进行说明。如图13所示，保护膜16覆盖导体层RM的上表面及侧壁。保护膜16具有露出导体层RM的上表面的一部分的开口16a。另外，在保护膜16的形成工序中，在导体柱CP的侧壁上形成保护膜SW。导体柱CP的上表面由阻隔层BF覆盖，因此导体柱CP的上表面(阻隔层BF的上表面)上不形成保护膜SW。
首先，以覆盖导体层RM及导体柱CP的方式，在半导体衬底1上涂布感光性聚酰亚胺清漆(图14的步骤S9a)。然后，形成感光性聚酰亚胺清漆层。感光性聚酰亚胺清漆是作为聚酰亚胺的前体的聚酰胺酸溶液。
然后，对感光性聚酰亚胺清漆层实施前烘工序(图14的步骤S9b)。关于前烘，进行90～100℃、270～300秒的热处理。
然后，对感光性聚酰亚胺清漆层实施曝光工序(图14的步骤S9c)。例如，进行对与图13的开口16a对应的区域照射光的曝光工序。
然后，对感光性聚酰亚胺清漆层实施后烘工序(图14的步骤S9d)。关于后烘，进行100～110℃、60～70秒的热处理。
然后，对感光性聚酰亚胺清漆层实施显影工序(图14的步骤S9e)。显影工序中，将曝光区域的感光性聚酰亚胺清漆除去。
然后，对感光性聚酰亚胺清漆层实施固化烘干工序(图14的步骤S9f)。关于固化烘干，进行340～350℃、180～200秒的热处理。
由此，形成由聚酰亚胺形成的、具有开口16a的保护膜16。需要说明的是，通过感光性聚酰亚胺清漆中所含的羧基的作用，在前烘及后烘的工序中，导体柱CP的铜发生离子化，从而向感光性聚酰亚胺清漆溶出，由此形成与聚酰胺酸的络合物(Cu羧酸盐络合物)。在显影工序中，Cu羧酸盐络合物残存于导体柱CP的侧壁上。由此，通过固化烘干工序中的脱水作用，分解为酰亚胺和Cu2O，从而形成改性了的混合层，成为保护膜SW。
需要说明的是，关于保护膜SW，能够确认到，在固化烘干之后即便实施O2灰化(ashing)也不会被除去而残留，在后述的焊料回流焊的工序中，其会阻碍焊料(Sn)与构成导体柱CP的铜的反应。
另外，在保护膜16的形成工序中，导体柱CP的上表面由于被由对聚酰胺酸无反应的贵金属构成的阻隔层BF覆盖，因此导体柱CP的上表面没有形成保护膜SW。这是由于，通过阻隔层防止了前烘及后烘的工序中的铜的溶出。
然后，如图15所示，实施探头检查(图7的步骤S10)。使在导体柱CP上形成的阻隔层BF接触探针PB，从而检查半导体器件所要求的电特性。另外，在形成焊料球电极SBC前，由于实施了探头检查，因此例如，能够实现在250～300℃的高温环境下长时间实施烘干的存储保持测试(memory retention test)等。
然后，如图16所示，形成焊料球电极SBC(图7的步骤S11)。在向阻隔层BF上供给球状的焊料球后，例如通过实施275℃的回流焊处理(热处理)，将焊料球熔融，从而在导体柱CP上隔着阻隔层BF而形成焊料球电极SBC。由此，形成导体柱CP、阻隔层BF，及由焊料球电极SBC构成的凸块电极BE1。
然后，如图17及图18所示，实施衬底封装(图7的步骤S12)。首先，如图17所示，以在半导体芯片CHP的主表面上形成的凸块电极BE1与在布线衬底WB的表面上形成的端子TA相对的方式，在布线衬底WB上配置半导体芯片CHP。在布线衬底WB的端子TA的表面上形成有预焊料19。作为预焊料19，能够使用由3元系的锡(Sn)-银(Ag)-铜(Cu)构成的无铅焊料。并且，使端子TA上的预焊料19与凸块电极BE1接触。
然后，对图18中的半导体芯片CHP及布线衬底WB实施例如270～280℃的回流焊，将凸块电极BE1及预焊料19熔融从而形成焊料层20。由此，形成由导体柱CP、阻隔层BF及焊料层20构成的凸块电极BE2，通过该凸块电极BE2将导体层RM与端子TA连接。也就是说，通过凸块电极BE2将半导体芯片CHP连接于布线衬底WB。
由于导体柱CP的侧壁被保护膜SW覆盖，因此能够防止焊料层20向导体柱CP的侧壁迂回进入。另外，能够防止焊料润湿(导体柱CP的铜(Cu)与焊料形成合金)。
然后，如图19所示，填充密封材料UF(图7的步骤S13)。向半导体芯片CHP的主表面与布线衬底WB的表面之间、且多个凸块电极BE2之间流入密封材料UF，之后，加上热处理从而将溶剂挥发，由密封材料UF将半导体芯片CHP与布线衬底WB之间包埋。密封材料UF与半导体芯片CHP的保护膜16的整个表面、及从开口16a的露出的导体层RM，以及布线衬底WB的阻焊膜SR1的整个表面接触。而且，密封材料UF与凸块电极BE2的整个周围接触，并以包埋凸块电极BE2的方式覆盖。其中，导体柱CP的整个外周隔着保护膜SW而由密封材料UF覆盖。在导体柱CP的周围，保护膜SW与密封材料UF接触。也就是说，密封材料UF完全覆盖凸块电极BE2的侧面。密封材料UF以没有间隙或孔隙的方式将由半导体芯片CHP、布线衬底WB及凸块电极BE2形成的空间包埋。
这里，导体柱CP的侧壁由于由有机膜构成的保护膜SW覆盖，因此能够提高导体柱CP与密封材料UF的粘接性。
经上述的制法，完成本实施方式的半导体器件SA。
＜本实施方式的半导体器件及其制造方法的特征＞
导体柱CP的侧壁由保护膜SW覆盖，因此能够防止在导体柱CP的上部形成的焊料球电极SBC或焊料20迂回进入导体柱CP的侧壁。另外，能够防止导体柱CP的侧壁的焊料润湿。因而，能够防止由于焊料迂回进入导体柱CP的侧壁而导致的在半导体芯片的表面保护膜或层间绝缘膜等中产生裂纹以及布线的断线。
导体柱CP在比焊盘电极PA的膜厚更厚的导体层RM上形成，且导体柱CP的下表面的整个区域位于导体层RM上，因此凸块电极BE2受到的应力能够通过导体层RM而被缓和。
另外，由于导体柱CP的下表面整个区域与导体层RM的上表面接触，因此能够降低导体柱CP与导体层RM间的接触电阻。
另外，导体柱CP的下表面整个区域与导体层RM的上表面接触，且界面上没有形成晶种层。晶种层12形成在导体层RM之下。因此，能够防止在导体层RM与导体柱CP的界面存在晶种层的情况下所产生的问题点、即“由晶种层的侵蚀导致的导体柱CP的宽度(直径)的减缩”。
此外，在导体层RM与表面保护膜10之间存在由聚酰亚胺膜构成的保护膜11，且在俯视中，导体柱CP的整个区域位于保护膜11上，因此凸块电极BE2受到的应力能够通过保护膜11缓和。
导体柱CP的侧壁由保护膜SW覆盖，其周围由密封材料UF覆盖。也就是说，由于在导体柱CP与密封材料UF之间存在由有机膜构成的保护膜SW，因此能够提高导体柱CP与密封材料UF之间的粘接力，且能够减少导体柱CP与密封材料UF的界面的剥离。
导体层RM的上表面及侧壁被由有机膜构成的保护膜16覆盖，因此能够提高其与密封材料UF的粘接性，且减少导体层RM与密封材料UF的界面的剥离。
导体柱CP的上表面被由贵金属构成的阻隔层BF覆盖，因此没有形成包含铜(Cu)的由有机膜形成的保护膜SW，焊料球电极SBC或焊料20润湿性提高。
另外，阻隔层BF包含用于防止焊料的扩散的层，因此能够提高导体柱CP与焊料球电极SBC或焊料20之间的粘接强度。
在保护膜16的形成工序中，由于在导体柱CP的侧壁上形成保护膜SW，因此能够减少制造工序数，能够降低半导体器件的成本。
在导体柱CP形成后、焊料球电极SBC形成前，实施探头检查，因此能够实现焊料的熔融温度以上的高温探头检查。另外，使导体柱CP的上表面或导体柱CP上的阻隔层BF与探针接触从而实施探头检查。也就是说，由于探针不与焊料球电极SBC接触，因此能够防止由半导体芯片CHP的表面内的焊料球电极SBC的高度的偏差导致的半导体芯片CHP与布线衬底WB间的连接不良。若探针接触焊料球电极SBC，则焊料球电极SBC发生损伤、变形，因此在多个焊料球电极SBC间产生高度的偏差，在衬底封装工序中，产生发生连接不良这样的问题。
另外，在保护膜16的形成工序中，在导体层RM的端部(第三区域P3)中，通过使圆形的导体层RM的比导体柱CP的大10μm以上，能够充分地确保开口16a的加工余量。也就是说，在俯视中，由于将导体柱CP完全露出，因此即便形成具有比导体柱CP还大的的开口16a，也能够通过保护膜16覆盖导体层RM的端部及侧壁。换而言之，在俯视中，导体柱CP配置在自导体层RM的端部起向内5μm以上的内侧。
需要说明的是，上述实施方式中，导体柱CP形成于与焊盘电极PA分离开的位置，但也可在与焊盘电极PA重合的位置形成导体柱CP。也就是说，也可以以与焊盘电极PA重合的方式设置导体层RM、以与导体层RM重合的方式配置导体柱CP。
＜变形例1＞
变形例1为上述实施方式的变形例，且为代替阻隔层而形成金属层、并在探头检查后实施热处理工序的变形例。将与上述实施方式共通的工序及构成标注同样的标记。
图20为示出变形例1的半导体器件的制造工序的一部分的工艺流程图。图21为变形例1的半导体器件的制造工序中的主要部分剖面图。
在实施图20所示的步骤S1～S6后，实施图20的步骤S71。如图21所示，利用电解镀覆法在开口13bb的内部、即在从掩膜层13b露出的导体层RM的上表面的一部分上依次形成导体柱CP用的镀铜(Cu)膜、以及由镀锡(Sn)膜构成的金属层ML11及由镀银(Ag)膜构成的金属层ML12。
实施图20的步骤S8及S9后，在探头检查(步骤S10)中，使探针接触在导体柱CP的上形成的金属层ML11及ML12，从而实施探头检查。
然后，实施热处理工序(图20的步骤S111)。关于热处理温度，例如在200℃以下实施，通过该热处理，在导体柱CP上形成由Cu3Sn构成的第一合金层及由Ag3Sn构成的第二合金层。
然后，实施图20的步骤S12及S13，从而完成变形例1的半导体器件。
在衬底封装(步骤S12)之前，实施热处理工序(步骤S111)从而在导体柱CP的上表面形成合金层，从而提高表面的耐氧化性及耐热性，因此能够得到相对于布线衬底WB侧预焊料的润湿性、及焊料连接后的作为良好的焊料阻隔层的连接部的高耐热性优异的结构，且能够制成车载制品所要求的200℃耐长期保存性的试验中也能够稳定的结构。
＜变形例2＞
变形例2为上述实施方式的变形例，且为代替阻隔层而形成金属层、并在探头检查后实施热处理工序的变形例。将与上述实施方式共通的工序及构成标注同样的标记。
图22为示出变形例2的半导体器件的制造工序的一部分的工艺流程图。图23及24为变形例2的半导体器件的制造工序中的主要部分剖面图。
在实施图22所示的步骤S1～S6后，实施图22的步骤S72。如图23所示，利用电解镀覆法，从而在作为开口13bb的内部的、从掩膜层13b露出的导体层RM的上表面的一部分上，依次形成导体柱CP用的镀铜(Cu)膜、以及由镀镍(Ni)膜构成的金属层ML21、由镀锡铜合金(Sn0.5Cu)膜构成的金属层M22，及由镀银(Ag)膜构成的金属层ML23。
实施图22的步骤S8及S9后，在探头检查(步骤S10)中，使探针接触导体柱CP的上形成的金属层ML23，从而实施探头检查。
然后，实施热处理工序(图22的步骤S112)。关于热处理温度，例如在300℃以上实施。通过该热处理，如图24所示，在导体柱CP上隔着金属层ML21而形成焊料球电极SBC1。焊料球电极SBC1为金属层ML22及ML23的合金层，其组成为SnXAg0.5Cu。对于探头检查而言在平坦面上实施，之后通过进行热处理工序从而形成凸点结构，有助于其衬底侧的预焊料与焊料球电极SBC1之间的封装的稳定化、容易化。此外，无需追加新的焊接工序，能够在两工序中产生适当的表面结构。
然后，实施图22的步骤S12及S13，从而完成变形例2的半导体器件。
以上，基于实用新型的实施方式对由本申请的实用新型人所做的实用新型进行了具体说明，但本实用新型不限于所述实施方式，当然，在不超出其主旨的范围内可进行各种变更。

Claims (9)

1.一种半导体器件，具有：
半导体衬底，
导体层，所述导体层形成在所述半导体衬底上、且具有第一上表面及第一下表面，
导体柱，所述导体柱形成在所述导体层的所述第一上表面上，且具有第二上表面、第二下表面及侧壁，
第一绝缘膜，所述第一绝缘膜覆盖所述导体层的所述第一上表面，且具有露出所述导体柱的所述第二上表面及所述侧壁的开口，及
保护膜，所述保护膜覆盖所述导体柱的所述侧壁，
在俯视中，所述开口大于所述第二上表面，并露出所述第二上表面的整个区域。
2.根据权利要求1所述的半导体器件，其中，
所述导体柱是以铜为主体的金属膜，
所述保护膜由含有铜的有机膜构成。
3.根据权利要求1所述的半导体器件，所述半导体器件进一步具有：
形成在所述半导体衬底之上、且形成在所述导体层之下的焊盘电极，
所述导体层的所述第一下表面连接于所述焊盘电极。
4.根据权利要求1所述的半导体器件，其中，
所述导体层由晶种层、和形成在所述晶种层上的镀铜膜构成。
5.根据权利要求4所述的半导体器件，其中，
所述晶种层的端部相对于所述镀铜膜的端部后退。
6.根据权利要求1所述的半导体器件，其中，
所述导体柱的所述第二下表面在其整个区域与所述导体层的所述第一上表面接触。
7.根据权利要求6所述的半导体器件，
所述半导体器件进一步具有第二绝缘膜，所述第二绝缘膜以在俯视中与所述导体柱的整个区域重合的方式形成在所述导体层之下。
8.根据权利要求7所述的半导体器件，其中，
所述第一绝缘膜及所述第二绝缘膜由聚酰亚胺膜构成。
9.根据权利要求1所述的半导体器件，所述半导体器件进一步具有：
覆盖所述导体柱的所述第二上表面的阻隔层，
所述阻隔层由贵金属膜构成。
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