CN109755137A - 半导体装置以及半导体装置的制造方法 - Google Patents

半导体装置以及半导体装置的制造方法 Download PDF

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Publication number
CN109755137A
CN109755137A CN201811317194.2A CN201811317194A CN109755137A CN 109755137 A CN109755137 A CN 109755137A CN 201811317194 A CN201811317194 A CN 201811317194A CN 109755137 A CN109755137 A CN 109755137A
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China
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mentioned
scolding tin
tin film
base portion
film
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进藤正典
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Lapis Semiconductor Co Ltd
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Lapis Semiconductor Co Ltd
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Abstract

本发明提供一种半导体装置以及半导体装置的制造方法。抑制外部连接端子内的空隙的产生。准备具有电极的半导体基板。形成与电极连接的布线。形成具有第一开口部的第一绝缘膜，该第一开口部使布线局部露出。形成由与布线的从第一开口部露出的部分连接，并具有与第一开口部对应的凹部的导电体构成的基座部。在基座部的表面形成焊锡膜。通过第一热处理使构成焊锡膜的焊锡熔融，并利用熔融的焊锡填充凹部。

Description

半导体装置以及半导体装置的制造方法
技术领域
本发明涉及半导体装置以及半导体装置的制造方法。
背景技术
WL－CSP(晶圆级芯片尺寸封装)是利用晶圆工艺进行重新布线的形成、外部连接端子的形成、树脂密封以及到切割为止的半导体装置的封装技术。作为外部连接端子使用焊球的情况较多。
例如在专利文献1中，记载有包含在母芯片的金属柱上形成焊锡膜的第一工序、以及在第一工序之后在母芯片上印刷焊锡膏并回流，从而形成焊球的第二工序的半导体装置的制造方法。
专利文献1：日本特开2007－165671号公报
在WL－CSP中，通过在覆盖重新布线的表面的绝缘膜设置开口部使重新布线局部露出，并在重新布线的露出部分经由作为阻挡金属发挥功能的基座部设置作为外部连接端子的焊球。基座部在与绝缘膜的开口部对应的部位具有凹部而形成。作为外部连接端子的焊球通过在印刷焊锡膏以覆盖基座部之后进行热处理(回流处理)而形成，但在基座部具有凹部的情况下，存在凹部内的空气在热处理(回流处理)后仍残留在焊球内，而在焊球内形成空隙的可能。若在外部连接端子内形成空隙，则该半导体装置和与外部连接端子接合的接合对象物(例如印刷电路基板)的接合强度降低，另外，接合部处的电阻升高损失增大。进一步，存在由于长期的使用而产生接合不良的可能。在为了满足WL－CSP的进一步小型化的要求，进行了外部连接端子的尺寸的缩小化的情况下，凹部的宽度w和凹部的深度d之比(d/w)增大，除去凹部内的空气更困难。
也考虑利用填充电镀，形成填充基座部的凹部的金属柱的对策。然而，在该情况下，需要用于进行填充电镀的专用的装置。另外，对于填充电镀所使用的电镀液而言，由组成引起的特性变动较大，为了进行稳定的电镀处理，需要电镀液的组成的管理工时。由于这些理由，在使用填充电镀的情况下，半导体装置的制造成本上升。
发明内容
本发明是鉴于上述的点而完成的，其目的在于抑制外部连接端子内的空隙的产生。
本发明的半导体装置的制造方法包含：准备具有电极的半导体基板的工序；形成与上述电极连接的布线的工序；形成具有使上述布线局部露出的第一开口部的第一绝缘膜的工序；形成由与上述布线的从上述第一开口部露出的部分连接，并具有与上述第一开口部对应的凹部的导电体构成的基座部的工序；在上述基座部的表面形成焊锡膜的工序；以及通过第一热处理使构成上述焊锡膜的焊锡熔融，并通过熔融的焊锡填充上述凹部的工序。
本发明的半导体装置包含：半导体基板，具有电极；布线，与上述电极连接；第一绝缘膜，具有使上述布线局部露出的第一开口部；基座部，形成由与上述布线的从上述第一开口部露出的部分连接，并具有与上述第一开口部对应的凹部的导电体构成；以及焊锡膜，设置于上述基座部的表面，填充上述凹部。
根据本发明，抑制外部连接端子内的空隙的产生。
附图说明
图1是表示本发明的实施方式的半导体装置的结构的一个例子的剖视图。
图2是表示本发明的实施方式的半导体装置的结构的一个例子的剖视图。
图3A是表示本发明的实施方式的半导体装置的制造方法的一个例子的剖视图。
图3B是表示本发明的实施方式的半导体装置的制造方法的一个例子的剖视图。
图3C是表示本发明的实施方式的半导体装置的制造方法的一个例子的剖视图。
图3D是表示本发明的实施方式的半导体装置的制造方法的一个例子的剖视图。
图3E是表示本发明的实施方式的半导体装置的制造方法的一个例子的剖视图。
图3F是表示本发明的实施方式的半导体装置的制造方法的一个例子的剖视图。
图3G是表示本发明的实施方式的半导体装置的制造方法的一个例子的剖视图。
图3H是表示本发明的实施方式的半导体装置的制造方法的一个例子的剖视图。
图3I是表示本发明的实施方式的半导体装置的制造方法的一个例子的剖视图。
图3J是表示本发明的实施方式的半导体装置的制造方法的一个例子的剖视图。
图3K是表示本发明的实施方式的半导体装置的制造方法的一个例子的剖视图。
图3L是表示本发明的实施方式的半导体装置的制造方法的一个例子的剖视图。
图3M是表示本发明的实施方式的半导体装置的制造方法的一个例子的剖视图。
图3N是表示本发明的实施方式的半导体装置的制造方法的一个例子的剖视图。
图3O是表示本发明的实施方式的半导体装置的制造方法的一个例子的剖视图。
图3P是表示本发明的实施方式的半导体装置的制造方法的一个例子的剖视图。
具体实施方式
以下，参照附图对本发明的实施方式进行说明。此外，在各附图中，对于实质相同或者等价的构成要素或者部分标注相同的参照附图标记。
图1是表示本发明的实施方式的半导体装置10的结构的一个例子的剖视图。半导体装置10的封装的方式具有WL－CSP的方式。即，半导体装置10的封装的平面尺寸与半导体基板11的平面尺寸大致相同。半导体装置10具备设置在半导体基板11上的下层绝缘膜15、设置于下层绝缘膜15的表面的重新布线22、覆盖下层绝缘膜15和重新布线22的上层绝缘膜30、与重新布线22连接的基座部42、以及覆盖基座部42的表面的焊锡膜50。
在半导体基板11的表面形成有晶体管、电阻元件以及电容器等半导体元件(未图示)。半导体基板11的表面被由SiO2等绝缘体构成的层间绝缘膜12覆盖。在层间绝缘膜12的表面设置有与半导体元件连接的芯片电极13、以及具有使芯片电极13的表面局部露出的开口部的钝化膜(保护膜)14。
钝化膜14的表面被由聚酰亚胺以及PBO(聚苯并恶唑)等感光性有机系绝缘部件构成的厚度5～10μm左右的下层绝缘膜15覆盖。在下层绝缘膜15设置有使芯片电极13的表面局部露出的开口部15A。
在下层绝缘膜15的表面，经由UBM膜21设置有重新布线22。UBM膜21包含为了提高下层绝缘膜15和重新布线22的紧贴性而包含Ti膜的紧贴层而构成。重新布线22例如包含Cu而构成。重新布线22在下层绝缘膜15的开口部15A与芯片电极13连接。
下层绝缘膜15以及重新布线22被由聚酰亚胺以及PBO等感光性有机系绝缘部件构成的厚度5～10μm左右的上层绝缘膜30覆盖。在上层绝缘膜30设置有在基座部42的形成位置使重新布线22局部露出的开口部30A。
基座部42经由UBM膜41与重新布线22的从开口部30A露出的部分连接。基座部42由厚度5μm左右的Ni膜构成。基座部42作为抑制构成重新布线22的Cu向外部连接端子60(参照图2)的扩散的阻挡金属发挥功能。基座部42的覆盖重新布线22的表面的部分的表面高度位置和覆盖上层绝缘膜30的表面的部分的表面高度位置相互不同。即，基座部42具有与上层绝缘膜30的开口部30A对应的凹部42A。
焊锡膜50由包含Sn－Ag的焊锡构成，覆盖基座部42的表面。基座部42的凹部42A被焊锡膜50填充，与焊锡膜50的凹部42A对应的表面为平坦面。即，伴随着上层绝缘膜30的开口部30A形成于基座部42的表面的凹凸通过焊锡膜50而平坦化。此外，焊锡膜50的表面并不局限于平坦，也可以为凸状的曲面。
在焊锡膜50和基座部42的界面形成有包含焊锡膜50所包含的Sn和基座部42所包含的Ni的厚度1μm左右的合金层(Ni－Sn合金层)51。合金层51通过利用热处理(回流)使焊锡膜50熔融而形成。优选合金层51遍及基座部42的整个区域被焊锡膜50覆盖。换言之，优选合金层51不在焊锡膜50的表面露出。包含Ni－Sn合金而构成的合金层51其本身的焊锡润湿性较低。因此，若合金层51在焊锡膜50的表面露出，则在经由焊锡膜50使基座部42和外部连接端子60接合时，构成外部连接端子60的焊锡的润湿性降低，基座部42和外部连接端子60的接合强度降低。例如，在焊锡膜50成膜时的膜厚较薄的情况下，在热处理(回流)后，存在合金层51在焊锡膜50的表面露出的可能。因此，优选将焊锡膜50成膜时的膜厚设为合金层51不在焊锡膜50的表面露出的充分的膜厚。
在这里，在将焊锡膜50成膜时的体积设为V、将基座部42的凹部42A的体积设为A、将合金层51的厚度设为t、将基座部42与焊锡膜50的接触面的面积设为S时，通过满足下述的(1)式，能够通过焊锡膜50填充基座部42的凹部42A，进一步能够抑制合金层51在焊锡膜50的表面露出。
V＞A+(t×S)···(1)
如图2所示，半导体装置10还可以包含与基座部42连接的外部连接端子60。外部连接端子60通过包含Sn－Ag的焊锡而构成，具有焊球的形式。外部连接端子60覆盖焊锡膜50的侧面和同与基座部42的接触面相反侧的面、以及基座部42的侧面。即，基座部42以及焊锡膜50埋设于外部连接端子60的内部。此外，在图2中，分别示有外部连接端子60和焊锡膜50，但构成外部连接端子60的焊锡以及构成焊锡膜50的焊锡相互融合，外部连接端子60和焊锡膜50成为一体。
以下参照图3A～图3P对半导体装置10的制造方法进行说明。首先，准备晶圆工序完成的半导体基板11(图3A)。晶圆工序包含在半导体基板11上形成晶体管等半导体元件(未图示)的工序、在半导体基板11的表面形成由SiO2等绝缘体构成的层间绝缘膜12的工序、在层间绝缘膜12的表面形成与半导体元件连接的芯片电极13的工序、以及在层间绝缘膜12的表面形成具有使芯片电极13部分露出的开口部的钝化膜14的工序。
接下来，例如，使用旋涂法，在晶圆工序完成后的半导体基板11的表面涂覆5μm左右的膜厚的聚酰亚胺以及PBO等感光性有机系绝缘部件，从而形成覆盖钝化膜14以及芯片电极13的表面的下层绝缘膜15。接着，通过对下层绝缘膜15实施曝光以及显影处理，在下层绝缘膜15形成使芯片电极13的表面局部露出的开口部15A。之后，通过热处理使下层绝缘膜15固化。通过热固化，下层绝缘膜15收缩，开口部15A的侧面成为正锥形形状(图3B)。
接下来，形成覆盖下层绝缘膜15的表面以及在下层绝缘膜15的开口部15A露出的芯片电极13的表面的UBM膜21(图3C)。UBM膜21由紧贴层以及种子层的层叠膜构成。紧贴层起到提高下层绝缘膜15和重新布线22的紧贴性的作用，例如由厚度150nm左右的Ti膜构成。种子层起到作为在通过电镀法形成重新布线22时的通电层的作用，例如由厚度300nm左右的Cu膜构成。紧贴层以及种子层分别例如通过溅射法来形成。
接下来，在UBM膜21上形成在重新布线22的形成预定位置具备开口部100A的抗蚀掩模100(图3D)。抗蚀掩模100通过在使用旋涂法在UBM膜21上涂覆由感光性有机系绝缘部件构成的抗蚀剂材料之后，通过曝光以及显影处理将该抗蚀剂材料图案化而形成。
接下来，使用电镀法，在抗蚀掩模100的开口部100A露出的UBM膜21上形成厚度为5μm左右的由Cu膜构成的重新布线22(图3E)。在电镀时，在将半导体基板11的表面浸入电镀液的状态下，电流经由设置于半导体基板11的外周的电镀电极(未图示)流过构成UBM膜21的种子层。由此，在UBM膜的露出部分析出Cu，在UBM膜上形成构成重新布线22的Cu膜。构成UBM膜21的种子层被纳入构成重新布线22的Cu。
接下来，使用灰化工序或者有机溶剂等除去抗蚀掩模100。接着，通过将重新布线22作为掩模来使用的湿式蚀刻处理依次除去构成UBM膜21的种子层(Cu)以及紧贴层(Ni)(图3F)。
接下来，例如，使用旋涂法，以10μm左右的膜厚涂覆聚酰亚胺以及PBO等感光性有机系绝缘部件，从而形成覆盖重新布线22以及下层绝缘膜15的上层绝缘膜30。接着，通过对上层绝缘膜30实施曝光以及显影处理，在上层绝缘膜30上形成在基座部42的形成预定位置使重新布线22局部露出的开口部30A。之后，通过热处理使上层绝缘膜30固化。通过热固化，上层绝缘膜30收缩，开口部30A的侧面成为正锥形形状(图3G)。
接下来，形成覆盖上层绝缘膜30的表面以及重新布线20的从上层绝缘膜30的开口部30A露出的部分的表面的UBM膜41(图3H)。UBM膜41由紧贴层以及种子层的层叠膜构成。紧贴层起到提高上层绝缘膜30和基座部42的紧贴性的作用，例如由厚度150nm左右的Ti膜构成。种子层起到作为在通过电镀法形成基座部42以及焊锡膜50时的通电层的作用，例如由厚度为500nm左右的Cu膜构成。紧贴层以及种子层分别例如由溅射法形成。
接下来，在UBM膜41上形成在基座部42的形成预定位置具备开口部101A的、厚度20μm左右的抗蚀掩模101。抗蚀掩模101的开口部101A内含有上层绝缘膜30的开口部30A(图3I)。抗蚀掩模101通过在使用旋涂法在UBM膜41上涂覆由感光性有机系绝缘部件构成的抗蚀剂材料之后，通过曝光以及显影处理将该抗蚀剂材料图案化而形成。
接下来，使用电镀法，在抗蚀掩模101的开口部101A露出的UBM膜41上，形成由厚度5μm左右的Ni膜构成的基座部42(图3J)。基座部42的覆盖重新布线22的表面的部分的表面高度位置和覆盖上层绝缘膜30的表面的部分的表面高度位置相互不同。即，基座部42具有与上层绝缘膜30的开口部30A对应的凹部42A而形成。基座部42作为构成重新布线22的Cu向外部连接端子60(参照图2)的扩散的阻挡金属发挥功能。
接下来，使用电镀法，在抗蚀掩模101的开口部101A露出的基座部42上，形成包含厚度5μm左右的Sn－Ag而构成的焊锡膜50(图3K)。由此，在抗蚀掩模101的开口部101A内形成包含基座部42和焊锡膜50的层叠膜。焊锡膜50使用与在基座部42的形成所使用的抗蚀掩模101共用的抗蚀掩模101而形成。焊锡膜50沿着基座部42的表面形成，具有与基座部42的凹部42A对应的凹部而形成。在这里，优选焊锡膜50成膜时的体积V满足上述的(1)式。
另一方面，优选焊锡膜50的表面的高度位置比抗蚀掩模101的表面的高度位置低。通过电镀处理形成的焊锡膜50随着处理时间的经过各向同性地生长。在外部连接端子60(参照图2)高密度地形成的WL－CSP中，在焊锡膜50的表面的高度位置超过抗蚀掩模101的表面的高度位置的情况下，焊锡膜50在抗蚀掩模101上横向扩展，有在与邻接的外部连接端子60之间引起短路的可能。通过使焊锡膜50的表面的高度位置比抗蚀掩模101的表面的高度位置低，能够防止与邻接的外部连接端子60之间的短路。例如，优选在抗蚀掩模101的厚度为20μm，基座部42的厚度为5μm的情况下，焊锡膜50的厚度为15μm以下。
接下来，使用灰化工序或者有机溶剂等除去抗蚀掩模101。接着，通过将焊锡膜50以及基座部42作为掩模来使用的湿式蚀刻处理依次除去构成UBM膜41的种子层(Cu)以及紧贴层(Ni)(图3L)。
接下来，在上层绝缘膜30和焊锡膜50上涂覆助焊剂之后，实施热处理(回流)，从而使构成焊锡膜50的焊锡熔融。熔融的焊锡流入基座部42的凹部42A内。另外，焊锡膜50所含的Sn－Ag和构成的基座部42的Ni反应，在焊锡膜50和基座部42的界面形成包含Ni－Sn合金的合金层51。焊锡膜50成膜时的体积V满足上述的(1)式，从而基座部42的凹部42A被焊锡膜50完全填充。另外，合金层51遍及基座部42的整个区域被焊锡膜50覆盖。即，焊锡膜50以合金层51不会在焊锡膜50的表面露出的厚度形成。另外，在本实施方式中，焊锡膜50以表面成为平坦的厚度形成(图3M)。此外，焊锡膜50的表面并不局限于平坦，也可以是凸状的曲面。本工序中的热处理(回流)是本发明中的第一热处理的一个例子。
接下来，通过使用具备内含基座部42以及焊锡膜50的开口部102A的印刷用掩模102的印刷法，形成包含Sn－Ag的焊锡膏60a。焊锡膏60a被填充至印刷用掩模102的开口部102A内，焊锡膜50以及基座部42被埋设于焊锡膏60a的内部。即，焊锡膜50的同与基座部42的接触面相反侧的面和侧面以及基座部42的侧面被焊锡膏60a覆盖。由于基座部42的凹部42A被焊锡膜50填充，所以能够抑制凹部42A内的空气残留于焊锡膏60a内(图3N)。
接下来，除去印刷用掩模102(图3O)。之后，通过实施第二次的热处理(回流)，使焊锡膏60a熔融。由此，焊锡膏60a的形状成为球状，形成具有焊球的形式的外部连接端子60(图3P)。通过第二次的热处理，构成焊锡膜50的焊锡也熔融，与外部连接端子60融合。如上述那样，基座部42的凹部42A被焊锡膜50填充，由此，由于抑制凹部42A内的空气残留于焊锡膏60a内，所以能够抑制外部连接端子60的内部的空隙的产生。此外，也可以在外部连接端子60形成之前在上层绝缘膜30的表面粘贴保护胶带，从半导体基板11的背面研磨半导体基板11来进行半导体基板11的薄膜化。本工序中的热处理(回流)是本发明中的第二热处理的一个例子。
在上述工序之后，将半导体基板11分割为多个半导体器件，从而WL－CSP型的半导体装置10完成。
根据本实施方式的半导体装置10及其制造方法，通过设置在基座部42和外部连接端子60之间的焊锡膜50填充基座部42的凹部42A。由此，能够抑制凹部42A内的空气残留于焊锡膏60a内，抑制外部连接端子60的内部的空隙的产生。由此，能够在与外部连接端子60接合的接合对象物(例如印刷电路基板)和半导体装置10接合时，确保充分的强度，另外，能够较低地抑制接合部的电阻。进一步，能够减少因长期的使用而产生接合不良的风险。另外，能够为了满足WL－CSP的进一步的小型化的要求，也应对外部连接端子的缩小化以及高密度化。
另外，根据本实施方式的半导体装置10及其制造方法，焊锡膜50形成为成膜时的体积V满足上述的(1)式。由此，由于合金层51遍及基座部42的整个区域被焊锡膜50覆盖，所以能够抑制构成外部连接端子60的焊锡的润湿性的降低，并能够确保基座部42和外部连接端子60的接合强度。
上层绝缘膜30是本发明中的第一绝缘膜的一个例子。开口部30A是本发明中的第一开口部的一个例子。抗蚀掩模101是本发明中的第一掩模的一个例子。印刷用掩模102是本发明中的第二掩模的一个例子。下层绝缘膜15是本发明中的第二绝缘膜的一个例子。开口部15A是本发明中的第二开口部的一个例子。
附图标记说明
10…半导体装置；11…半导体基板；12…层间绝缘膜；13…芯片电极；15…下层绝缘膜；15A…开口部；22…重新布线；30…上层绝缘膜；30A…开口部；42…基座部；42A…凹部；50…焊锡膜；51…合金层；60…外部连接端子；60a…焊锡膏。

Claims (16)

1.一种半导体装置的制造方法，包含：
准备具有电极的半导体基板的工序；
形成与上述电极连接的布线的工序；
形成具有使上述布线局部露出的第一开口部的第一绝缘膜的工序；
形成由与上述布线的从上述第一开口部露出的部分连接，并具有与上述第一开口部对应的凹部的导电体构成的基座部的工序；
在上述基座部的表面形成焊锡膜的工序；以及
通过第一热处理使构成上述焊锡膜的焊锡熔融，并通过熔融的焊锡填充上述凹部的工序。
2.根据权利要求1所述的制造方法，其中，还包含：
在上述第一热处理后，形成覆盖上述焊锡膜的表面的焊锡膏的工序；以及
通过第二热处理，使上述焊锡膏以及构成上述焊锡膜的焊锡熔融，形成与上述基座部连接的外部连接端子的工序。
3.根据权利要求2所述的制造方法，其中，
上述焊锡膜通过电镀处理形成，
上述焊锡膏通过印刷形成，
上述焊锡膜以及上述基座部埋设于上述焊锡膏的内部。
4.根据权利要求3所述的制造方法，其中，
上述焊锡膜通过使用具备开口部的第一掩模，以上述焊锡膜的表面的高度位置不超过上述第一掩模的表面的高度位置的厚度形成，上述开口部内含上述第一开口部。
5.根据权利要求3或4所述的制造方法，其中，
上述焊锡膏通过使用内含上述基座部以及上述焊锡膜的第二掩模的印刷而形成。
6.根据权利要求1～5中任意一项所述的制造方法，其中，
在上述第一热处理中，在上述焊锡膜和上述基座部的界面形成包含上述基座部的材料和上述焊锡膜的材料的合金层。
7.根据权利要求6所述的制造方法，其中，
在将上述焊锡膜成膜时的体积设为V、将上述凹部的体积设为A、将上述合金层的厚度设为t、将上述基座部与上述焊锡膜的接触面的面积设为S时，满足：V＞A+(t×S)。
8.根据权利要求6或7所述的制造方法，其中，
上述合金层遍及上述基座部的整个区域，并被上述焊锡膜覆盖。
9.根据权利要求1～8中任意一项所述的制造方法，其中，
在上述第一热处理后，上述焊锡膜的表面是平坦的。
10.根据权利要求1～9中任意一项所述的制造方法，其中，
还包含形成具有使上述电极局部露出的第二开口部的第二绝缘膜的工序，
上述布线形成于上述第二绝缘膜的表面，与上述电极的从上述第二开口部露出的部分连接。
11.一种半导体装置，包含：
半导体基板，具有电极；
布线，与上述电极连接；
第一绝缘膜，具有使上述布线局部露出的第一开口部；
基座部，由与上述布线的从上述第一开口部露出的部分连接，并具有与上述第一开口部对应的凹部的导电体构成；以及
焊锡膜，设置于上述基座部的表面，填充上述凹部。
12.根据权利要求11所述的半导体装置，其中，
在上述焊锡膜和上述基座部的界面，具有包含上述基座部的材料和上述焊锡膜的材料的合金层。
13.根据权利要求12所述的半导体装置，其中，
在将上述焊锡膜成膜时的体积设为V、将上述凹部的体积设为A、将上述合金层的厚度设为t、将上述基座部与上述焊锡膜的接触面的面积设为S时，满足：V＞A+(t×S)。
14.根据权利要求12或13所述的半导体装置，其中，
上述合金层遍及上述基座部的整个区域，并被上述焊锡膜覆盖。
15.根据权利要求11～14中任意一项所述的半导体装置，其中，
上述焊锡膜的表面是平坦的。
16.根据权利要求11～15中任意一项所述的半导体装置，其中，
还包括将上述基座部埋设于内部的外部连接端子。
CN201811317194.2A 2017-11-07 2018-11-07 半导体装置以及半导体装置的制造方法 Pending CN109755137A (zh)

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