CN207068843U - Semiconductor devices - Google Patents

Semiconductor devices Download PDF

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Publication number
CN207068843U
CN207068843U CN201720758267.6U CN201720758267U CN207068843U CN 207068843 U CN207068843 U CN 207068843U CN 201720758267 U CN201720758267 U CN 201720758267U CN 207068843 U CN207068843 U CN 207068843U
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Prior art keywords
layer
film
conductor
semiconductor devices
diaphragm
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CN201720758267.6U
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Chinese (zh)
Inventor
矢岛明
山田义明
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Renesas Electronics Corp
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Renesas Electronics Corp
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
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    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
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Abstract

It the utility model is related to semiconductor devices, it is possible to increase the reliability of semiconductor devices.Semiconductor devices has：Semiconductor substrate (1)；Conductor layer (RM), formed in Semiconductor substrate (1) and there is upper surface and lower surface；Conductor pin (CP), is formed on conductor layer (RM) upper surface, and has upper surface, lower surface and side wall；Diaphragm (16), the upper surface of covering conductor layer (RM), and with the opening (16a) for exposing conductor pin (CP) upper surface and side wall；And the diaphragm (SW) of the side wall of covering conductor pin (CP).Moreover, in vertical view, the opening (16a) of diaphragm (16) is more than the upper surface of conductor pin (CP), and exposes the whole region of the upper surface of conductor pin (CP).

Description

Semiconductor devices
Technical field
The utility model is related in semiconductor devices, for example, be related to comprising with connect up again (wiring being reconfigured at) half The effective technology applied in the semiconductor devices of conductor chip.
Background technology
Disclosed in No. 8441124 specifications (patent document 1) of U.S. Patent No., in order to prevent being formed on UBM layer The oxidation of Cu posts and the erosion (undercut) of UBM layer, diaphragm is formed in the side wall of Cu posts, and make the width of UBM layer Width of the degree more than Cu posts.
Prior art literature
Patent document
Patent document 1：No. 8441124 specifications of U.S. Patent No.
Utility model content
Utility model technical problems to be solved
The salient pole of the semiconductor chip of present inventor's research is formed in the following manner.
After crystal seed film (seed film) is formed on the pad electrode that wiring layer on by Semiconductor substrate is formed, Etchant resist is formed on crystal seed film, the etchant resist is being formed the region openings of salient pole, formed using plating method by plating Cu films The cylindrical wiring column electrode (post electrode) (conductor pin, Cu posts) of formation, will be to connecing after etchant resist is removed The crystal seed film etching of the outside extension of terminal electrode removes.Then, to supplying spherical solder ball in wiring column electrode, and implement Salient pole formation Reflow Soldering, so as to which solder ball to be melted to and formed on the upper surface of wiring column electrode solder ball electrode, So as to complete the salient pole of semiconductor chip.
Further, pre-welding material (Japanese is set on the terminal of wiring board：Meet the fields of え half) after, semiconductor chip is taken It is loaded on wiring board.In salient pole in the state of pre-welding material is configured on terminal in wiring board, pass through implementation The Reflow Soldering (heat treatment) of encapsulation, so as to which salient pole is engaged in into terminal, so as to complete comprising half with salient pole The semiconductor devices of conductor chip.
Present inventor is in the conceptual phase of above-mentioned semiconductor device, it is understood that problems with.
By the semiconductor-chip-mounting that silicon etc. is formed on the wiring board formed by glass epoxy resin, due to semiconductor Heating when the setting environment or semiconductor chip of device work, so as to the salient pole connected between the two is applied into stress, Thus cracked in the surface protection film of semiconductor chip described later or interlayer dielectric etc..Particularly, when as interlayer Dielectric film and in the case of having used the Low-k materials of low-k, due to the reason of its fragility, the probability cracked It is high.
Verified according to the research of present inventor：If implementing the Reflow Soldering of encapsulation, solder ball or pre-welding material or Form the two solder (especially, tin (Sn)) to flow out to the side wall of wiring column electrode, reach the pad of semiconductor chip Electrode.It is also to be recognized that the hardness of tin (Sn) is also higher than the hardness of copper (Cu), the solder part flowed out to the side wall of wiring column electrode Ground is present in side wall, therefore the phenomenon that stress partly concentrates on pad electrode occurs, and in the surface protection of semiconductor chip Cracked in film or interlayer dielectric etc., moisture-proof reduction, or connect up the problems such as breaking.
That is, it is necessary to the raising of reliability or the raising of performance in the semiconductor devices with salient pole.
Description and appended accompanying drawing by this specification, the feature of other problemses and novelty can be understood.
The means used to solve the problem
Semiconductor devices in one embodiment has：Semiconductor substrate；Conductor layer, the conductor layer serve as a contrast in semiconductor Formed on bottom and there is the first upper surface and the first lower surface；Conductor pin, the conductor pin form the first upper table in conductor layer On face, and there is the second upper surface, the second lower surface and side wall；Dielectric film, the first upper table of the dielectric film covering conductor layer Face, and with the second upper surface for exposing conductor pin and the opening of side wall；And diaphragm, the side of the diaphragm covering conductor pin Wall.Moreover, in vertical view, the opening of dielectric film is more than the second upper surface of conductor pin, and exposes the whole area of the second upper surface Domain.
Utility model effect
According to an embodiment, it is possible to increase the reliability of semiconductor devices.
Brief description of the drawings
Fig. 1：For the upper surface figure of the semiconductor devices in embodiment.
Fig. 2：For the side view of the semiconductor devices in embodiment.
Fig. 3：For the lower surface figure of the semiconductor devices in embodiment.
Fig. 4：For the fragmentary cross-sectional view of the semiconductor devices in embodiment.
Fig. 5：For the top view of the semiconductor chip of present embodiment.
Fig. 6：For the expansion top view in Fig. 5 A portions.
Fig. 7：To show the process chart of a part for the manufacturing process of the semiconductor devices of present embodiment.
Fig. 8：For the major part profile in the manufacturing process of the semiconductor devices of present embodiment.
Fig. 9：For the major part profile in then Fig. 8, semiconductor devices manufacturing process.
Figure 10：For the major part profile in then Fig. 9, semiconductor devices manufacturing process.
Figure 11：For the major part profile in then Figure 10, semiconductor devices manufacturing process.
Figure 12：For the major part profile in then Figure 11, semiconductor devices manufacturing process.
Figure 13：For the major part profile in then Figure 12, semiconductor devices manufacturing process.
Figure 14：To show the technique stream of the details of a process in the manufacturing process of the semiconductor devices of present embodiment Cheng Tu.
Figure 15：For the major part profile in then Figure 13, semiconductor devices manufacturing process.
Figure 16：For the major part profile in then Figure 15, semiconductor devices manufacturing process.
Figure 17：For the major part profile in then Figure 16, semiconductor devices manufacturing process.
Figure 18：For the major part profile in then Figure 17, semiconductor devices manufacturing process.
Figure 19：For the major part profile in then Figure 18, semiconductor devices manufacturing process.
Figure 20：To show the process chart of a part for the manufacturing process of the semiconductor devices of variation 1.
Figure 21：For the major part profile in the manufacturing process of the semiconductor devices of variation 1.
Figure 22：To show the process chart of a part for the manufacturing process of the semiconductor devices of variation 2.
Figure 23：For the major part profile in the manufacturing process of the semiconductor devices of variation 2.
Figure 24：For the major part profile in the manufacturing process of the semiconductor devices of variation 2.
Description of reference numerals
1 Semiconductor substrate
2Pp type traps
2Nn type traps
3 element separating tanks
3a element isolation films
4th, 6,8 interlayer dielectric
5 first layer Cu are connected up
5a dielectric films
7 second layer Cu are connected up
9 third layer Al are connected up
10 surface protection films
10a is open
11 diaphragms
11a is open
12 crystal seed layers
13a, 13b mask layer
13aa, 13bb are open
14th, 15 plated film
16 diaphragms
16a is open
19 pre-welding materials (meet solder)
20 solder layers
BE1, BE2 salient pole
BF barrier layers
CHP semiconductor chips
CL sandwich layers
CP conductor pins
LND ends
ML11, ML12 metal level
ML21, ML22, ML23 metal level
P1, p2, p3 connector
PA pad electrodes
PB probes
Qnn channel-type MIS transistors
Qpp channel-type MIS transistors
RM conductor layers (connect up) again
SA semiconductor devices
SB substrate solder balls
SBC, SBC1 solder ball electrode
SR1, SR2 soldering-resistance layer
SW diaphragms
TA terminals
UC corrodes
UF encapsulants (underfilling)
WB wiring boards
WL1, WL2, WL3 are connected up
Embodiment
In the following embodiments, for convenience, it is divided into some or embodiment to illustrate when necessary, but removes It is not what is had no bearing between them outside situation about especially expressing, but a side is all or part of of the opposing party The relations such as variation, details, supplementary notes.
In addition, in the following embodiments, when mentioning number of key element etc. (including number, numerical value, amount, scope etc.), except Situation about especially expressing and it is expressly defined in principle outside situation of certain number etc., is not limited to the certain number, can More than certain number can also be below certain number to be.
Moreover, in the following embodiments, except situation about especially expressing and it is considered as in principle being clearly necessary Outside situation etc., its inscape (in addition to key element step etc.) is certainly not necessarily necessary.
In the same manner, in the following embodiments, when being related to shape, position relationship of inscape etc. etc., except special Situation about expressing and think outside situation clearly invalid in principle etc., including it is approximate or similar substantially with the shape etc. Situation etc..At this point, for above-mentioned number etc. (including number, numerical value, amount, scope etc.) and equally.
In addition, in whole accompanying drawings for illustrating embodiment, the part with same function is marked in principle together One symbol, omit the repeat specification to it.It should be noted that there is also also marked in a top view for ease of observation accompanying drawing The situation of hatching is noted.
(embodiment)
The structure ＞ of ＜ semiconductor devices
Fig. 1 is the upper surface figure of the semiconductor devices in present embodiment.Fig. 2 is the semiconductor devices in present embodiment Side view.Fig. 3 is the lower surface figure of the semiconductor devices in present embodiment.Fig. 4 is the semiconductor device in present embodiment The fragmentary cross-sectional view of part.Fig. 5 is the top view of the semiconductor chip of present embodiment.Fig. 6 is the expansion top view in Fig. 5 A portions. Figure 16 is the profile along Fig. 6 line A-A.
As shown in figure 1, the semiconductor devices SA in present embodiment has the wiring board of rectangle (for example, square) WB, rectangle (for example, rectangle) is equipped with across encapsulant (underfilling) UF in wiring board WB central portion Semiconductor chip CHP.As shown in figure 1, semiconductor chip CHP size is less than wiring board WB size.
Then, as shown in Fig. 2 the semiconductor devices SA in present embodiment has wiring board WB, in the wiring board Formed with multiple substrates solder ball SB on the WB back side (lower surface).On the other hand, wiring board WB surface (main surface, Upper surface) on carry semiconductor chip CHP, formed with multiple salient pole BE2 on semiconductor chip CHP.Projection electricity Pole BE2 height is, for example, 40 μm~200 μm degree.Also, semiconductor chip CHP and wiring board WB is through above-mentioned salient pole BE2 and electrically connect.It should be noted that as shown in Fig. 2 due to salient pole BE2 presence and caused, semiconductor chip Encapsulant UF is filled with gap between CHP and wiring board WB.Encapsulant UF and semiconductor chip CHP main table Side (surface) contact in face, wiring board WB surface and salient pole BE2.
Then, as shown in figure 3, being configured with multiple substrate solder ball SB on the wiring board WB back side with array-like. In Fig. 3, the peripheral part (outer edge) along such as wiring board WB is shown, substrate solder ball SB example is configured with 4 row.On These substrates are stated by the use of solder ball SB as the external connection terminals that semiconductor devices SA is connected with external equipment to be played Function.That is, on substrate solder ball SB, it is equipped on by semiconductor devices SA for example with mainboard (mother board) as generation Used during the circuitry substrate of table., can also be in the entire surface throughout the wiring board WB back side on substrate solder ball SB In the range of with rectangular configuration.
Fig. 4 is the fragmentary cross-sectional view of the semiconductor devices SA in present embodiment.Wiring board WB takes laminates knot Structure, but in Fig. 4, respectively illustrate only the wiring WL1 of sandwich layer CL and sandwich layer CL face side and rear side wiring WL2 One layer.On the wiring WL1 for the face side for being formed at sandwich layer CL, its upper surface and side are by soldering-resistance layer SR1 (solder Resist membrane) it is coated.The terminal TA for being formed at a wiring WL1 part is being arranged at soldering-resistance layer SR1 opening portion Expose from soldering-resistance layer SR1, also, at the opening portion, salient pole BE2 is connected to terminal TA.On being formed at sandwich layer CL's The wiring WL2 of rear side, its upper surface and side are coated to by soldering-resistance layer SR2.It is formed at the terminal pad of a wiring WL2 part (Japanese：ラ Application De) LND exposes from soldering-resistance layer SR2 being arranged at soldering-resistance layer SR2 opening portion, at the opening portion, substrate Terminal pad LND is connected to solder ball SB.The wiring WL1 on surface via the wiring WL3 being arranged in insertion sandwich layer CL path, And it is connected with the wiring WL2 at the back side.Soldering-resistance layer SR1 and SR2 are the dielectric film that is made up of the resin of insulating properties, and sandwich layer CL is by by example The resin substrates that insulating barrier is made in such as glass epoxy resin are formed.
Semiconductor chip CHP is carried on wiring board WB, is connected to and (is formed on semiconductor chip CHP main surface ) conductor layer (connects up, the wiring being reconfigured at) RM salient pole BE2 and be connected with the terminal TA exposed from soldering-resistance layer SR1 again.And And it is filled with encapsulant UF to semiconductor chip CHP and wiring board WB gap.That is, with semiconductor chip CHP The main surface mode relative with wiring board WB surface, semiconductor chip CHP is equipped on wiring via salient pole BE2 On substrate WB surface.It is moreover, complete by encapsulant UF between semiconductor chip CHP main surface and wiring board WB surface It is complete to embed, also embedded completely by encapsulant UF between multiple salient pole BE2.That is, salient pole BE2 side wall (side Face, surface) contacted with encapsulant UF around whole.On encapsulant UF, for example, for salient pole BE2 and end Purpose that the stress that sub- TA junction surface is born is relaxed and set, and by the insulative resin film structure such as epoxy resin Into.Salient pole BE2 represents to be connected to the salient pole in the state of wiring board WB in semiconductor chip CHP.The opposing party Face, as shown in figs. 5 and 6, before semiconductor chip CHP is connected into wiring board WB, in semiconductor chip CHP master The salient pole that surface is formed is salient pole BE1.In vertical view, salient pole BE1 is on corresponding position with BE2.
On the main surface of the semiconductor chip CHP shown in Fig. 5, pad electrode PA is configured with 1 row in its peripheral part.Point Not along 2 long sides on main surface and each side of 2 short sides being made up of rectangle, 1 row pad electrode PA is configured, so as to form ring The pad electrode PA of shape row.Moreover, the inner side of the row in the pad electrode PA of ring-type, multiple salient pole BE1 in X-direction and Configured in Y-direction with ranks shape, so as to form salient pole BE1 group on the whole.It is above-mentioned, each have it is circular multiple convex Block electrode B E1 is configured in X-direction or Y-direction with pitch equal respectively.Fig. 5 circular mark is salient pole BE1.Weldering Disc electrode PA can also configure the saw-tooth arrangement of 2 row or 2 row along each side.Semiconductor chip CHP can also be square.
Each pad electrode PA is connected with salient pole BE1 by conductor layer RM (not shown), and conductor layer RM is from semiconductor core Piece CHP peripheral part extends to central portion.That is, using conductor layer RM, semiconductor chip CHP peripheral part will be configured at Pad electrode PA be reconfigured in the central portion in semiconductor chip CHP region configuration salient pole BE1.Adjacent projection Electrode B E1 pitch is more than adjacent pad electrode PA pitch.Here, the salient pole BE1 of so-called adjoining pitch and neighbour The pad electrode PA connect pitch, object is used as using the pitch of minimum respectively.External connection terminals as semiconductor chip CHP And the pitch for playing the salient pole BE1 of function is more than pad electrode PA pitch, thus make itself and foregoing wiring board WB Between connection become easy.
Fig. 6 represents the pad electrode PA and salient pole BE1 in Fig. 5 A portions.As shown in fig. 6, pad electrode PA is via conductor Layer RM and be connected to salient pole BE1.Salient pole BE1 has conductor pin CP and solder ball electrode SBC.
Conductor layer RM is made up of region below：As the first area P1 of conductor layer RM and the connecting portion of pad electrode, make For conductor layer RM and the 3rd region P3 of the connecting portion of salient pole, and link first area P1 and the 3rd region P3 the secondth area Domain P2.
It is in the P1 of first area in conductor layer RM one end, conductor layer RM connects via the opening 10a and 11a of square In pad electrode PA.As described later, in section view, exist between pad electrode PA and conductor layer PM surface protection film 10 and Diaphragm 11, opening 10a are formed at surface protection film 10, and opening 11a is formed at diaphragm 11.In the P1 of first area, conductor Layer RM one end turn into square, its be more than opening 10a and 11a's while.In addition, conductor layer RM one end and opening 10a and 11a can also be circle, it is important that the diameter of conductor layer RM one end is more than opening 10a and 11a diameter.
In the 3rd region P3 as the conductor layer RM other end, in the opening 16a of diaphragm 16 on conductor layer RM Inside it is connected with salient pole BE1.As described later, in section view, conductor layer RM is covered by diaphragm 16, but one part via Opening 16a and expose from diaphragm 16.Moreover, in opening 16a, conductor pin CP is configured with conductor layer RM.
As shown in fig. 6, in the 3rd region P3, conductor layer RM turns intoCircle, diaphragm 16 opens Mouth 16a turns intoCircle, conductor pin CP turns intoCircle.Moreover, it is important that set For Relation.In whole periphery in conductor pin CP side wall Formed thickness (t) diaphragm SW, as described later, diaphragm SW also throughout conductor pin CP short transverse whole region, So as to be formed in conductor pin CP side wall.In order to form diaphragm SW in conductor pin CP side wall, it is important that be arranged toIn addition it is arranged toRelation It is and important.That is, as shown in fig. 6, in vertical view, conductor pin CP and diaphragm SW whole region are located at opening 16a inside, and fully expose from diaphragm 16.
In addition, in the 3rd region P3, conductor layer RM periphery be preferably in the range of whole periphery by protecting Film 16 covers, and it is important that is arranged to Relation.Moreover, in order to maintainRelation, and in view of allowance etc. of diaphragm 16, preferably make conductor layer RM'sThan conductor pin CP'sIt is big more than 10 μm.
Based on above content, for example, can be arranged to
In addition, on the diameter for the spherical solder ball electrode SBC being configured on conductor pin CP, it is set to be more than and leads Scapus CP'sAnd less than opening 16a'sBut it can also be set to more than opening 16a'sOr conductor layer RM
In the second area P2 for linking first area P1 and the 3rd region P3, conductor layer RM width (Fig. 6 Y side To) narrower than first area P1 and the 3rd region P3 conductor layer RM width (Fig. 6 Y-direction).In second area P2 and the 3rd Region P3 boundary, can also make conductor layer RM width (Fig. 6 Y-direction) from second area P2 to the 3rd region P3 slowly Ground stepwise increases.
As it was previously stated, conductor layer RM is covered by diaphragm 16, but in Fig. 6, conductor layer RM is represented with straight line.
Next, using Figure 16, illustrate the cross-section structure of the semiconductor devices of present embodiment.Figure 16 is shown along Fig. 6's The profile of line A-A.
As shown in figure 16, pad electrode PA is formed on semiconductor substrate 1, in Semiconductor substrate 1 and pad electrode PA Form surface protection film 10 and diaphragm 11.The part of surface protection film 10 and diaphragm 11 with exposed pad electrode PA Be open 10a and 11a.Opening 11a diameter is bigger than opening 10a diameter, and in opening 10a whole region opening.
Pad electrode PA passes through by such as aluminium film, aluminium alloy film (AlSi films, AlCu films or AlSiCu films etc.) or copper film structure Into electrically conductive film form.When forming pad electrode PA by aluminium film or aluminium alloy film, can aluminium film or aluminium alloy film up and down Metal Obstruct membrane is set.For example, on pad electrode PA, can be set to from lower floor as Ti films/TiN film/AlCu films/TiN film Stepped construction.In addition, when forming pad electrode PA by copper film, can metal Obstruct membrane be set under copper film, in copper film On anti-oxidation metal Obstruct membrane is set.For example, on pad electrode PA, can be set to from lower floor as TaN film/Cu The stepped construction of film/Ni films.
Surface protection film 10 is made up of inorganic insulating membrane, and by such as silicon oxide film, silicon nitride film, or both stacked film Deng composition.In passing, in the case of stacked film, silicon oxide film, silicon nitride film are stacked gradually from lower floor.Surface protection film 10 Thickness is preferably set to such as less than 1 μm.
Diaphragm 11 is made up of organic insulating film, such as is made up of thickness for the polyimide film of 3~5 μm of degree.Protection Film 11, which has to prevent from applying to salient pole BE1 and conductor layer RM stress, to be conducted to surface protection film 10, semiconductor chip CHP Deng stress alleviating function.
As shown in figure 16, conductor layer RM is formed on surface protection film 10 and diaphragm 11, and conductor layer RM is via surface The opening 10a and 11a of diaphragm 10 and diaphragm 11 and contact and connect with pad electrode PA.That is, in surface protection In the opening 10a and 11a of film 10 and diaphragm 11, conductor layer RM lower surface and pad electrode PA upper surface.Conductor Layer RM is made up of the stacked film of crystal seed layer 12, plated film 14 and 15, and plated film 14 and 15 has equal shape in vertical view.Crystal seed layer 12 have under vertical view with 14 and 15 generally equalized shape of plated film, as described later, the end of crystal seed layer 12 has from plated film The 14 end shape that side (pad electrode PA sides) retreats slightly inwards.That is, crystal seed layer 12 occurs relative to plated film 14 Corrode.Not shown in figure, but crystal seed layer 12 turns into barrier layer (it prevents pad electrode PA and conductor layer RM reaction) and electricity The stepped construction of plating crystal seed layer during solution plating.Barrier layer for example rises by titanium (Ti) film, titanium nitride (TiN) film and titanium from below (Ti) stacked film of film is formed, and the thickness of these above-mentioned films is set to 10nm, 50nm and 10nm successively.Plating crystal seed layer is in barrier layer Upper formation, and be made up of copper film, its thickness is set to 100~500nm.Plated film 14 is made up of copper film, and its thickness is 5~20 μm of journeys Degree, plated film 15 are made up of nickel film, and its thickness is set to 2~3 μm.In addition, as the barrier layer for forming crystal seed layer 12, titanium can be used (Ti) film, titanium nitride (TiN) film, titanium tungsten (TiW) film, chromium (Cr) film, tantalum (Ta) film, tungsten (W) film, tungsten nitride (WN) film, Gao Rong Point metal film, noble metal film (Pd, Ru, Pt, Ni etc.).
Conductor layer RM is the low-down wiring of resistance, and has (bigger) film thicker than pad electrode PA thickness It is thick.Moreover, conductor layer RM thickness is preferably 5~10 times or more of pad electrode PA thickness.
In addition, as shown in figure 16, on conductor layer RM, its upper surface (main surface) and side wall (side) are covered by diaphragm 16 Lid.The opening 16a of a part formed with the upper surface for exposing conductor layer RM in diaphragm 16.Diaphragm 16 covers conductor Layer RM upper surface and side wall and conductor layer RM shoulder etc. does not expose is important, and by organic insulating film (for example, polyamides Imines film) form, its thickness is set to 5~8 μm.Opening 16a diameterFor the upper of the conductor layer RM that exposes from diaphragm 16 The length on surface.
It is being arranged in the opening 16a of diaphragm 16, conductor layer RM is connected with conductor pin CP, conductor pin CP lower surface Whole region contacts with conductor layer RM upper surface (nickel plated film 15).That is, opening 16a by conductor pin CP upper surface and Side wall (side) is completely exposed.In opening 16a, exist around conductor pin CP, throughout conductor pin CP whole periphery The conductor layer RM exposed from diaphragm 16 upper surface.Conductor pin CP is made up of copper plating film, and its thickness is 20 μm of degree.
As shown in Figure 16 and Fig. 6, diaphragm SW is formed in conductor pin CP side wall, conductor pin is completely covered in diaphragm SW CP side wall.That is, in vertical view, in the conductor pin CP of circle short transverse and circumferencial direction, side wall is covered Whole region.Diaphragm SW is the organic film containing copper (Cu), and its thickness is 100nm degree.In addition, diaphragm SW includes copper (Cu), carbon (C), nitrogen (N), hydrogen (H) and oxygen (O).Diaphragm SW is acid imide and Cu2O mixed layer.Diaphragm SW for example with Prevent the work(of solder (for example, Sn) guide scapus CP contained in solder ball electrode SBC or aftermentioned pre-welding materials 19 side wall attachment Energy.
As shown in figure 16, solder ball electrode SBC is formed across barrier layer BF in conductor pin CP upper surface.Solder ball electricity Pole SBC is the lead-free solder that such as 3 yuan tin (Sn) for being-silver (Ag)-copper (Cu) is formed.Specifically, can use with Sn, The solder of 1%Ag, 0.5%Cu ratio of components.In addition, the change of ratio of components can suitably be carried out in solder or containing bismuth (Bi) Or other additives.
In addition, barrier layer BF is made up of the noble metal such as golden (Au), silver-colored (Ag), palladium (Pd).That is, conductor pin CP's is upper The barrier layer BF coverings that surface is made up of noble metal.Cover conductor pin CP's by the barrier layer BF being made up of in advance noble metal Upper surface, when forming diaphragm SW in conductor pin CP side wall, it can prevent from forming protection on conductor pin CP upper surface Film SW.As barrier layer BF, instead of noble metal, the precious metal alloys such as Pd alloys, Au alloys, Ag alloys can be used.Separately Outside, in order to prevent from solder ball electrode SBC or described later pre-welding materials 19 expanding in contained solder (for example, Sn) guide scapus CP Dissipate, barrier layer BF is preferably set to the stepped construction of nonproliferation film and noble metal film or precious metal alloys film.Nonproliferation film is preferred It is present between noble metal film or precious metal alloys film and conductor pin CP.As nonproliferation film, nickel (Ni), nickel can be used to close Gold.
In addition, as shown in figure 16, salient pole BE1 is made up of conductor pin CP, barrier layer BF and solder ball electrode SBC.
The manufacture method ＞ of ＜ semiconductor devices
Then, using Fig. 7~Figure 19, the manufacture method of the semiconductor devices of present embodiment is illustrated.Fig. 7 and Figure 14 is to show The process chart of the details of the process gone out in the manufacturing process of the semiconductor devices of present embodiment.Fig. 8~Figure 13 and Figure 15~Figure 19 is the major part profile in the manufacturing process of the semiconductor devices of present embodiment.
As shown in figure 8, preparation (preparation) semiconductor chip CHP (the step of Fig. 7 formed with pad electrode Pa on the surface S1)。
As shown in figure 8, formed with p-type trap 2P, n-type trap 2N in the Semiconductor substrate 1 that the monocrystalline silicon by such as p-type is formed And element separating tank 3, and the element isolation film 3a being made up of in the embedment of the inside of element separating tank 3 such as silicon oxide film.
Formed with n-channel type MIS transistors (Qn) in above-mentioned p-type trap 2P.N-channel type MIS transistors (Qn) are by element Active region as defined in separating tank 3 is formed, and with the source region ns and drain region nd that are formed in p-type trap 2P and in p-type trap The upper gate electrode ng formed across gate insulating film ni of 2P.In addition, formed with p-channel type MIS transistors in above-mentioned n-type trap 2N (Qp), p-channel type MIS transistors (Qp) have source region ps and drain region pd and on n-type trap 2N across gate insulating film pi And the gate electrode pg formed.
Partly led formed with connection on the top of above-mentioned n-channel type MIS transistors (Qn) and p-channel type MIS transistors (Qp) Body interelement, the wiring that is formed by metal film.In general wiring between connection semiconductor element has~10 layers of degree that have three layers Miltilayer wiring structure, but as an example of multilayer wiring, the metal film institute structure based on copper alloy is shown in Fig. 8 Into 2 layers of wiring layer (first layer Cu wiring 5, the second layer Cu wiring 7) and be made up of using Al alloys the metal film of main body 1 The wiring layer (third layer Al wirings 9) of layer.So-called wiring layer, in the blanket feelings represented of the multiple wirings that will be formed by each wiring layer Used under condition.On the thickness of wiring layer, the wiring layer of the second layer is than the wiring thickness of first layer, and the wiring layer of third layer is than Two layers of wiring thickness.
Between n-channel type MIS transistors (Qn) and p-channel type MIS transistors (Qp) and first layer Cu wiring 5, first Between layer Cu connects up 5 and second layer Cu wirings 7, and second layer Cu is connected up between 7 and third layer Al connects up 9 and is respectively formed with by oxygen The interlayer dielectric 4,6,8 of the compositions such as SiClx film, and connector p1, p2, the p3 that will be electrically connected between 3 layers of wiring.
Above-mentioned interlayer dielectric 4 is formed on semiconductor substrate 1 in a manner of for example covering semiconductor element, first layer Cu Formed in the 5 dielectric film 5a on above-mentioned interlayer dielectric 4 of wiring.First layer Cu wirings 5 are via for example in interlayer dielectric 4 The connector p1 of formation and with the source region ns, drain region nd, grid of the n-channel type MIS transistors (Qn) as semiconductor element electricity Pole ng is electrically connected.In addition, first layer Cu wiring 5 via the connector p1 formed in interlayer dielectric 4 and with as semiconductor element The source region ps of the p-channel type MIS transistors (Qp) of part, drain region pd, gate electrode pg electrical connections.Gate electrode ng, pg and first The connection of layer Cu wirings 5 is not illustrated.Connector p1, p2, p3 are made up of metal film, such as W (tungsten) film.First layer Cu is connected up 5 are formed by inlaying (damascene) method in dielectric film 5a wiring groove, first layer Cu wirings 5 by barrier electrically conductive film and The stepped construction of the electrically conductive film based on copper on its upper strata is formed.Electrically conductive film is obstructed by tantalum (Ta), titanium (Ti), ruthenium (Ru), tungsten (W), manganese (Mn) and their nitride and/or silicon nitride compound, or their stacked film are formed.Conductor based on copper Film by copper (Cu) or copper alloy (copper (Cu) and aluminium (Al), magnesium (Mg), titanium (Ti), manganese (Mn), iron (Fe), zinc (Zn), zirconium (Zr), The alloy of niobium (Nb), molybdenum (Mo), ruthenium (Ru), palladium (Pd), silver (Ag), gold (Au), In (indium), lanthanide series metal or actinide metals etc.) Formed.
Second layer Cu wirings 7 are electrically connected via the connector p2 formed in such as interlayer dielectric 6 with first layer Cu wirings 5 Connect.Third layer Al wirings 9 electrically connect via the connector p3 formed in such as interlayer dielectric 8 with second layer Cu wirings 7.Insert Plug p3 is made up of metal film (such as W (tungsten) film).
Second layer Cu wirings 7 and connector p2 is integratedly formed in interlayer dielectric 6, and second layer Cu connects up 7 and connector p2 It is made up of the stepped construction of barrier electrically conductive film and its electrically conductive film based on copper on upper strata.Also, obstruct electrically conductive film and with copper Formed for the electrically conductive film of main body by connecting up 5 same materials with first layer Cu.
In addition, first layer Cu wiring 5 and interlayer dielectric 6 between, and the second layer Cu wiring 7 with interlayer dielectric 8 it Between be preferably provided for preventing the barrier dielectric film that copper spreads to interlayer dielectric 6 or 8, and obstruct dielectric film and can use SiCN The stacked film of film or SiCN films and SiCO films.
In addition, third layer Al wirings 9 are made up of aluminium alloy film (for example, Al films added with Si and Cu), but can also set Connected up for Cu.
In addition, interlayer dielectric 4 is by silicon oxide film (SiO2) form, but it is of course also possible to by the silicon oxide film comprising carbon (SiOC films), the silicon oxide film (SiCON films) comprising nitrogen and carbon, the monofilm of silicon oxide film (SiOF films) comprising fluorine or stacking Film is formed.
It is the top of above-mentioned third layer Al wiring 9 formed with (as most in the wiring layer of the superiors as multilayer wiring Whole passivating film) monofilm such as silicon oxide film, silicon nitride film, or the surface protection film (protection being made up of their 2 tunics Film, dielectric film) 10.Moreover, the superiors that bonding pad opening (opening) 10a formed in the surface protection film 10 bottom is exposed Wiring layer be third layer Al wiring 9 form pad electrode (pad, electrode pad) PA.
Then, as shown in figure 9, forming diaphragm (organic insulating film) 11 (Fig. 7 step S2) on surface protection film 10. It should be noted that after Fig. 9, omitted than pad electrode PA wiring layers on the lower, transistor etc..Used as diaphragm 11 Photosensitive polyimide resin.Being coated with, being exposed and developed for photosensitive polyimide is carried out on surface protection film 10, so that After opening 10a and pad electrode PA exposes, (cure) (heat treatment) is solidified so as to be solidified.That is, by right Photosensitive polyimide resin film is patterned, so as to form the guarantor with the opening 11a bigger than opening 10a and pad electrode PA Cuticula 11.In vertical view, opening 10a and 11a is square.It should be noted that opening 10a and 11a can also be set to circular.
Then, as shown in Figure 10, crystal seed layer 12 (Fig. 7 step S3) is formed on diaphragm 11.Crystal seed layer 12 is by obstructing The stepped construction of layer and the plating crystal seed film on barrier layer is formed.Barrier layer is for example by sputtering method or CVD (Chemical Vapor Deposition) method forms titanium film (Ti films), titanium nitride film (TiN film) and titanium film (Ti films), its thickness be set to 10nm, 50nm, 10nm, plating crystal seed film for example form copper (Cu) film by sputtering method, and its thickness is set to 200nm.Crystal seed layer 12 and pad electrode PA Upper surface, formed form opening 10a and 11a the side wall of surface protection film 10 and the side wall of diaphragm 11 and The upper surface of surface protection film 10 and the upper surface of diaphragm 11.
Then, as shown in Figure 10, mask layer (dielectric film, organic insulating film) 13a (Fig. 7 steps are formed on crystal seed layer 12 Rapid S4).As mask layer 13a, liquid resist or dry film photoresist can be used, its thickness is, for example, 10~30 μm.Mask Layer 13a has an opening 13aa, bagmouths open 11a and 10a in mask layer 13a opening 13aa.In the opening exposed from mask layer 13a 13aa's is internally formed conductor layer RM.
Then, as shown in Figure 10, plated film 14 and 15 (Fig. 7 step S5) is formed.Using electrolytic plating method, in mask layer Plated film 14 and 15 is formed in 13a opening 13aa.By the electrolytic coating process, crystal seed layer 12 plays work(as crystal seed layer Energy.Plated film 14 is set to copper facing (Cu) film, and plated film 15 is set to nickel plating (Ni) film.The first filming 14 wraps opening 10a and 11a completely Bury.By mask layer 13a after the formation of plated film 15.
Then, as shown in figure 11, mask layer (dielectric film, organic insulating film) 13b (Fig. 7 steps are formed on conductor layer RM Rapid S6).As mask layer 13b, liquid resist or dry film photoresist can be used, the thickness is, for example, 30~40 μm.Mask There is layer 13b opening 13bb, mask layer 13b opening 13bb will not be wrapped in opening 11a and 10a.
Then, as shown in figure 11, conductor pin CP and barrier layer BF (Fig. 7 step S7) is formed.Using electrolytic plating method, As opening 13bb it is inside, from a part for the mask layer 13b conductor layer RM exposed upper surface, sequentially form conductor Post CP copper facing (Cu) film, and barrier layer BF nickel plating (Ni) film and plating palladium (Pd) film.It is brilliant in the electrolytic coating process Kind layer 12 plays function as crystal seed layer.After barrier layer BF plated film is formed, mask layer 13b is removed.
Then, as shown in figure 12, crystal seed layer 12 (Fig. 7 step S8) is removed.To by foregoing mask layer 13b remove so as to The crystal seed layer 12 exposed carries out such as wet etch process, so as to be removed from the crystal seed layer 12 in the region that plated film 14 and 15 exposes Go.Thus, the conductor layer RM being made up of plated film 15, plated film 14 and crystal seed layer 12 is formed.In the process, in order to will be from plated film 14 And 15 the region exposed crystal seed layer 12 completely remove, it is necessary to overetch (overetch).Therefore, formed and corroded in crystal seed layer 12 UC.That is, the end of crystal seed layer 12 retreats to (pad electrode PA direction) to inward side from the end of plated film 14 and 15, Therefore the eaves of plated film 14 and 15 is formed on diaphragm 11.The erosion UC of crystal seed layer 12 is throughout conductor layer RM whole periphery In the range of formed.
Then, as shown in figure 13, diaphragm 16 (Fig. 7 step S9) is formed.It should be noted that the details of above-mentioned operation Illustrated using Figure 14 process chart.As shown in figure 13, diaphragm 16 covers conductor layer RM upper surface and side wall.Protect Cuticula 16 has the opening 16a of a part for the upper surface for exposing conductor layer RM.In addition, in the formation process of diaphragm 16, Diaphragm SW is formed in conductor pin CP side wall.Conductor pin CP upper surface is covered by barrier layer BF, therefore conductor pin CP Upper surface does not form diaphragm SW on (barrier layer BF upper surface).
First, in a manner of covering conductor layer RM and conductor pin CP, photosensitive polyimide is coated with semiconductor substrate 1 Varnish (Figure 14 step S9a).Then, photosensitive polyimide layer of varnish is formed.Photosensitive polyimide varnish is as poly- The polyamic acid solution of imido precursor.
Then, front baking process (Figure 14 step S9b) is implemented to photosensitive polyimide layer of varnish.On front baking, carry out 90~100 DEG C, the heat treatment of 270~300 seconds.
Then, exposure process (Figure 14 step S9c) is implemented to photosensitive polyimide layer of varnish.For example, carry out pair with The exposure process of Figure 13 opening area illumination light corresponding to 16a.
Then, process (Figure 14 step S9d) is dried after implementing to photosensitive polyimide layer of varnish.On rear baking, carry out 100~110 DEG C, the heat treatment of 60~70 seconds.
Then, developing procedure (Figure 14 step S9e) is implemented to photosensitive polyimide layer of varnish., will in developing procedure The photosensitive polyimide varnish of exposure area removes.
Then, solidification baking operation (Figure 14 step S9f) is implemented to photosensitive polyimide layer of varnish.Dried on solidification It is dry, carry out 340~350 DEG C, the heat treatment of 180~200 seconds.
Thus, diaphragm 16 formed by polyimides, that there is opening 16a is formed.It should be noted that by photosensitive Property polyimide varnish in contained carboxyl effect, in the process dried in front baking and afterwards, conductor pin CP copper ionizes, So as to photosensitive polyimide varnish dissolution, be consequently formed and the complex compound of polyamic acid (Cu carboxylate complexes).Aobvious In shadow process, Cu carboxylate complexes are remained in conductor pin CP side wall.Thus, made by solidifying the dehydration in baking operation With being decomposed into acid imide and Cu2O, so as to form the mixed layer being modified, turn into diaphragm SW.
It should be noted that on diaphragm SW, it is able to confirm that, even if implementing O after solidification is dried2Ashing (ashing) it will not also be removed and remain, in the process of solder Reflow Soldering described later, it can hinder solder (Sn) with forming The reaction of conductor pin CP copper.
In addition, in the formation process of diaphragm 16, conductor pin CP upper surface is due to by by reactionless to polyamic acid The barrier layer BF coverings that form of noble metal, therefore conductor pin CP upper surface does not form diaphragm SW.This is because, pass through Barrier layer prevents front baking and the dissolution of copper in the process dried afterwards.
Then, as shown in figure 15, implement probe and check (Fig. 7 step S10).Make the barrier layer formed on conductor pin CP BF contact probe PB, so as to check the electrical characteristics required by semiconductor devices.In addition, before solder ball electrode SBC is formed, due to Implement probe to check, therefore for example, the storage that implemented for long periods is dried under 250~300 DEG C of hot environment can be realized Keep test (memory retention test) etc..
Then, as shown in figure 16, solder ball electrode SBC (Fig. 7 step S11) is formed.To supplying ball on barrier layer BF After the solder ball of shape, such as by implementing 275 DEG C of reflow process (heat treatment), solder ball is melted, so as in conductor pin CP is upper to form solder ball electrode SBC across barrier layer BF.Thus, conductor pin CP, barrier layer BF are formed, and by solder ball electrode The salient pole BE1 that SBC is formed.
Then, as shown in FIG. 17 and 18, substrate encapsulation (Fig. 7 step S12) is implemented.First, as shown in figure 17, with The salient pole BE1 formed on semiconductor chip CHP main surface and the terminal TA phases formed on wiring board WB surface To mode, the configuring semiconductor chip CHP on wiring board WB.Formed with pre- on wiring board WB terminal TA surface Solder 19.As pre-welding material 19, the lead-free solder being made up of 3 yuan of tin for being (Sn)-silver (Ag)-copper (Cu) can be used.Also, The pre-welding material 19 on terminal TA is set to be contacted with salient pole BE1.
Then, such as 270~280 DEG C of Reflow Soldering is implemented to the semiconductor chip CHP in Figure 18 and wiring board WB, will Salient pole BE1 and pre-welding material 19 are melted so as to form solder layer 20.Thus, formed by conductor pin CP, barrier layer BF and solder Conductor layer RM, is connected by the salient pole BE2 that layer 20 is formed by salient pole BE2 with terminal TA.That is, by convex Semiconductor chip CHP is connected to wiring board WB by block electrode B E2.
Because conductor pin CP side wall is covered by diaphragm SW, therefore the guide scapus CP of solder layer 20 side wall can be prevented Roundabout entrance.In addition, solder can be prevented (conductor pin CP copper (Cu) forms alloy with solder).
Then, as shown in figure 19, packing matcrial UF (Fig. 7 step S13).To semiconductor chip CHP main surface Between wiring board WB surface and between multiple salient pole BE2 flow into encapsulant UF, afterwards, plus heat treatment from And solvent volatilizees, it will be embedded by encapsulant UF between semiconductor chip CHP and wiring board WB.Encapsulant UF is with partly leading The whole surface of body chip CHP diaphragm 16 and the conductor layer RM exposed from opening 16a, and wiring board WB resistance Weld film SR1 whole surface contact.Moreover, encapsulant UF contacts with salient pole BE2 whole surrounding, and to embed projection Electrode B E2 mode covers.Wherein, conductor pin CP whole periphery is covered across diaphragm SW by encapsulant UF.Leading Around scapus CP, diaphragm SW contacts with encapsulant UF.That is, salient pole BE2 is completely covered in encapsulant UF Side.Encapsulant UF will be by semiconductor chip CHP, wiring board WB and salient pole in a manner of very close to each other or hole The space embedding that BE2 is formed.
Here, conductor pin CP side wall is due to the diaphragm SW coverings being made up of organic film, therefore can improve conductor pin CP and encapsulant UF cementability.
Through above-mentioned preparation method, the semiconductor devices SA of present embodiment is completed.
The semiconductor devices of ＜ present embodiments and its feature ＞ of manufacture method
Conductor pin CP side wall is covered by diaphragm SW, therefore can prevent the solder ball in the formation of conductor pin CP top Electrode SBC or the roundabout side wall into conductor pin CP of solder 20.In addition, the solder of conductor pin CP side wall can be prevented. Thus, it is possible to prevent caused by the roundabout side wall into conductor pin CP of solder semiconductor chip surface protection film or The broken string for cracking and connecting up in interlayer dielectric etc..
Conductor pin CP is formed on the thicker conductor layer RM of the thickness than pad electrode PA, and conductor pin CP lower surface Whole region is located on conductor layer RM, therefore the stress that salient pole BE2 is subject to can be alleviated by conductor layer RM.
Further, since conductor pin CP lower surface whole region and conductor layer RM upper surface, therefore can reduce Contact resistance between conductor pin CP and conductor layer RM.
In addition, conductor pin CP lower surface whole region and conductor layer RM upper surface, and do not formed on interface Crystal seed layer.Crystal seed layer 12 is formed under conductor layer RM.Therefore, it is possible to prevent from existing at conductor layer RM and conductor pin CP interface The problem that in the case of crystal seed layer point, i.e. " width (diameter) of the conductor pin CP as caused by the erosion of crystal seed layer subtracts Contracting ".
In addition, the diaphragm 11 being made up of polyimide film between conductor layer RM and surface protection film 10 be present, and In vertical view, conductor pin CP whole region is located on diaphragm 11, therefore the stress that salient pole BE2 is subject to can pass through protection Film 11 relaxes.
Conductor pin CP side wall is covered by diaphragm SW, is covered by encapsulant UF around it.That is, due to leading The diaphragm SW being made up of organic film between scapus CP and encapsulant UF be present, therefore conductor pin CP and sealing material can be improved Expect the bonding force between UF, and the stripping at conductor pin CP and encapsulant UF interface can be reduced.
Conductor layer RM upper surface and side wall are covered by the diaphragm 16 being made up of organic film, thus can improve its with it is close Closure material UF cementability, and reduce the stripping at conductor layer RM and encapsulant UF interface.
The barrier layer BF coverings that conductor pin CP upper surface is made up of noble metal, therefore include copper (Cu) without being formed The diaphragm SW formed by organic film, solder ball electrode SBC or the wetability of solder 20 improve.
In addition, barrier layer BF includes the layer for the diffusion for being used to prevent solder, therefore conductor pin CP and solder ball can be improved Adhesive strength between electrode SBC or solder 20.
In the formation process of diaphragm 16, due to forming diaphragm SW in conductor pin CP side wall, therefore it can subtract Few manufacturing process number, the cost of semiconductor devices can be reduced.
After conductor pin CP is formed, before solder ball electrode SBC formed, implement probe and check, therefore solder can be realized High-temperature probe inspection more than melting temperature.In addition, make the barrier layer BF on conductor pin CP upper surface or conductor pin CP with visiting Pin contact checks so as to implement probe.That is, because probe does not contact with solder ball electrode SBC, thus can prevent by Semiconductor chip CHP and wiring board caused by the deviation of the height of solder ball electrode SBC in semiconductor chip CHP surface Bad connection between WB.If probe contacts solder ball electrode SBC, damage, deformation occur for solder ball electrode SBC, therefore more The deviation of height is produced between individual solder ball electrode SBC, in substrate packaging process, produces and the problem of bad connection is such occurs.
In addition, in the formation process of diaphragm 16, in conductor layer RM end (the 3rd region P3), by making circle Conductor layer RMThan conductor pin CP'sIt is big more than 10 μm, it can fully ensure to be open 16a allowance.That is, in vertical view, due to conductor pin CP being completely exposed, so even being formed has than conductor Post CP is also bigOpening 16a, conductor layer RM end and side wall can be also covered by diaphragm 16.Change For it, in vertical view, conductor pin CP configurations are inside more than 5 μm from conductor layer RM end of inner side.
It should be noted that in above-mentioned embodiment, conductor pin CP is formed at the position separated with pad electrode PA, but Also conductor pin CP can be formed in the position overlapped with pad electrode PA.That is, can also be to overlap with pad electrode PA Mode sets conductor layer RM, conductor pin CP is configured in a manner of being overlapped with conductor layer RM.
The ＞ of ＜ variations 1
Variation 1 is the variation of above-mentioned embodiment, and to form metal level instead of barrier layer and being checked in probe Implement the variation of heat treatment step afterwards.By the process common with above-mentioned embodiment and form the same mark of mark.
Figure 20 is the process chart of a part for the manufacturing process for the semiconductor devices for showing variation 1.Figure 21 is change Major part profile in the manufacturing process of the semiconductor devices of shape example 1.
After step S1~S6 shown in Figure 20 is implemented, implement Figure 20 step S71.As shown in figure 21, plated using electrolysis Method is covered to sequentially form in a part for the conductor layer RM exposed from mask layer 13b upper surface in opening 13bb inside, i.e. Conductor pin CP copper facing (Cu) film and the metal level ML11 being made up of tin plating (Sn) film and the gold being made up of silver-plated (Ag) film Belong to layer ML12.
After the step S8 and S9 that implement Figure 20, checked in probe in (step S10), make probe contact in the upper of conductor pin CP The metal level ML11 and ML12 of formation, checked so as to implement probe.
Then, heat treatment step (Figure 20 step S111) is implemented.It is real on heat treatment temperature, such as below 200 DEG C Apply, by the heat treatment, formed on conductor pin CP by Cu3Sn form the first alloy-layer and by Ag3The second alloy that Sn is formed Layer.
Then, Figure 20 step S12 and S13 is implemented, so as to complete the semiconductor devices of variation 1.
Before substrate encapsulates (step S12), implement heat treatment step (step S111) so as in conductor pin CP upper table Face forms alloy-layer, so as to improve the oxidative resistance on surface and heat resistance, therefore can obtain pre- relative to wiring board WB sides The excellent structure of the high-fire resistance of the connecting portion as good solder barrier layer after the wetability and solder connection of solder, And the structure that can also stablize in the experiment of 200 DEG C of resistance to long-term preservabilities required by vehicle-mounted product can be made.
The ＞ of ＜ variations 2
Variation 2 is the variation of above-mentioned embodiment, and to form metal level instead of barrier layer and being checked in probe Implement the variation of heat treatment step afterwards.By the process common with above-mentioned embodiment and form the same mark of mark.
Figure 22 is the process chart of a part for the manufacturing process for the semiconductor devices for showing variation 2.Figure 23 and 24 For the major part profile in the manufacturing process of the semiconductor devices of variation 2.
After step S1~S6 shown in Figure 22 is implemented, implement Figure 22 step S72.As shown in figure 23, plated using electrolysis Cover method, so as to as opening 13bb it is inside, from a part for the mask layer 13b conductor layer RM exposed upper surface, Sequentially form conductor pin CP copper facing (Cu) film and be made up of nickel plating (Ni) film metal level ML21, by Tinplated copper alloy (Sn0.5Cu) the metal level M22 that film is formed, and the metal level ML23 being made up of silver-plated (Ag) film.
After the step S8 and S9 that implement Figure 22, checked in probe in (step S10), make probe contact conductor pin CP upper shape Into metal level ML23, so as to implement probe check.
Then, heat treatment step (Figure 22 step S112) is implemented.It is real on heat treatment temperature, such as more than 300 DEG C Apply.By the heat treatment, as shown in figure 24, solder ball electrode SBC1 is formed across metal level ML21 on conductor pin CP.Weldering Pellet electrode SBC1 is metal level ML22 and ML23 alloy-layer, consisting of SnXAg0.5Cu.Flat for probe checks Implement on smooth face, contribute to pre-welding material and the weldering of its substrate side by carrying out heat treatment step so as to form bump structure afterwards The stabilisation of encapsulation between pellet electrode SBC1, facilitation.In addition, without additional new welding sequence, can be in two-step It is middle to produce appropriate surface texture.
Then, Figure 22 step S12 and S13 is implemented, so as to complete the semiconductor devices of variation 2.
More than, the utility model done by the utility model people of the application is carried out based on the embodiment of utility model Illustrate, but the utility model is not limited to the embodiment, certainly, can be carried out in the range of without departing from its purport various Change.

Claims (9)

1. a kind of semiconductor devices, has：
Semiconductor substrate,
Conductor layer, the conductor layer form on the semiconductor substrate and have the first upper surface and the first lower surface,
Conductor pin, the conductor pin are formed on first upper surface of the conductor layer, and with the second upper surface, second Lower surface and side wall,
First dielectric film, first dielectric film cover first upper surface of the conductor layer, and have and expose described lead Second upper surface of scapus and the opening of the side wall, and
Diaphragm, the diaphragm cover the side wall of the conductor pin,
In vertical view, the opening is more than second upper surface, and exposes the whole region of second upper surface.
2. semiconductor devices according to claim 1, wherein,
The conductor pin is the metal film based on copper,
The diaphragm is made up of the organic film containing copper.
3. semiconductor devices according to claim 1, the semiconductor devices further has：
The pad electrode on the Semiconductor substrate and formed under the conductor layer is formed,
First lower surface of the conductor layer is connected to the pad electrode.
4. semiconductor devices according to claim 1, wherein,
The conductor layer is made up of crystal seed layer and the copper plating film formed on the crystal seed layer.
5. semiconductor devices according to claim 4, wherein,
The end of the crystal seed layer retreats relative to the end of the copper plating film.
6. semiconductor devices according to claim 1, wherein,
First upper surface of second lower surface of the conductor pin in its whole region and the conductor layer.
7. semiconductor devices according to claim 6,
The semiconductor devices further has the second dielectric film, second dielectric film with vertical view with the conductor pin The mode that whole region overlaps is formed under the conductor layer.
8. semiconductor devices according to claim 7, wherein,
First dielectric film and second dielectric film are made up of polyimide film.
9. semiconductor devices according to claim 1, the semiconductor devices further has：
The barrier layer of second upper surface of the conductor pin is covered,
The barrier layer is made up of noble metal film.
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