CN205680672U - 微间距封装结构 - Google Patents

微间距封装结构 Download PDF

Info

Publication number
CN205680672U
CN205680672U CN201620548615.2U CN201620548615U CN205680672U CN 205680672 U CN205680672 U CN 205680672U CN 201620548615 U CN201620548615 U CN 201620548615U CN 205680672 U CN205680672 U CN 205680672U
Authority
CN
China
Prior art keywords
chip
edge
micro
covering portion
width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201620548615.2U
Other languages
English (en)
Chinese (zh)
Inventor
吴非艰
谢庆堂
徐佑铭
吴国玄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chipbond Technology Corp
Original Assignee
Chipbond Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipbond Technology Corp filed Critical Chipbond Technology Corp
Application granted granted Critical
Publication of CN205680672U publication Critical patent/CN205680672U/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
CN201620548615.2U 2016-03-24 2016-06-07 微间距封装结构 Active CN205680672U (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW105109267A TW201735277A (zh) 2016-03-24 2016-03-24 微間距封裝結構
TW105109267 2016-03-24

Publications (1)

Publication Number Publication Date
CN205680672U true CN205680672U (zh) 2016-11-09

Family

ID=57435239

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201610399692.0A Pending CN107230665A (zh) 2016-03-24 2016-06-07 微间距封装结构
CN201620548615.2U Active CN205680672U (zh) 2016-03-24 2016-06-07 微间距封装结构

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201610399692.0A Pending CN107230665A (zh) 2016-03-24 2016-06-07 微间距封装结构

Country Status (4)

Country Link
JP (1) JP2017175097A (ja)
KR (1) KR20170112866A (ja)
CN (2) CN107230665A (ja)
TW (1) TW201735277A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107230665A (zh) * 2016-03-24 2017-10-03 颀邦科技股份有限公司 微间距封装结构
CN110265381A (zh) * 2018-03-12 2019-09-20 颀邦科技股份有限公司 半导体封装结构及其线路基板

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113725169B (zh) * 2021-04-22 2024-06-14 成都芯源系统有限公司 倒装芯片封装单元及相关封装方法
CN113327899A (zh) * 2021-04-22 2021-08-31 成都芯源系统有限公司 倒装芯片封装单元及封装方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09139450A (ja) * 1995-11-13 1997-05-27 Sony Corp ヒートシンクの固定方法
JPH11163494A (ja) * 1997-11-28 1999-06-18 Toshiba Corp 表面実装デバイスの実装方法、ｂｇａパッケージの実装構造、及び電子機器
JP2000156460A (ja) * 1998-11-20 2000-06-06 Mitsui High Tec Inc 半導体装置
JP4709813B2 (ja) * 2003-12-05 2011-06-29 三井金属鉱業株式会社 プリント配線基板、回路装置およびプリント配線基板の製造方法
KR20120053332A (ko) * 2010-11-17 2012-05-25 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
TW201735277A (zh) * 2016-03-24 2017-10-01 頎邦科技股份有限公司 微間距封裝結構

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107230665A (zh) * 2016-03-24 2017-10-03 颀邦科技股份有限公司 微间距封装结构
CN110265381A (zh) * 2018-03-12 2019-09-20 颀邦科技股份有限公司 半导体封装结构及其线路基板

Also Published As

Publication number Publication date
KR20170112866A (ko) 2017-10-12
TW201735277A (zh) 2017-10-01
JP2017175097A (ja) 2017-09-28
CN107230665A (zh) 2017-10-03

Similar Documents

Publication Publication Date Title
CN205680672U (zh) 微间距封装结构
CN102593072B (zh) 倒装封装中用于提高可靠性的盖式设计
EP0747952B1 (en) Thermally enhanced ball grid array package
KR101827215B1 (ko) 반도체 장치
CN101752327B (zh) 具有散热结构的半导体封装件
CN205789928U (zh) 散热封装构造
WO2016140793A1 (en) Electronic package that includes multi-layer stiffener
CN113097162A (zh) 散热片、芯片及电路板
CN102522380A (zh) 一种PoP封装结构
CN203165882U (zh) 堆叠封装结构
CN205211739U (zh) 引线框架
US9257358B2 (en) Chip stacking packaging structure
US20140209285A1 (en) Method for manufacturing cooling device, cooling device and electronic component package equipped with cooling device
CN208753317U (zh) 集成电路布图结构
CN109936971A (zh) 一种用于降低接触热阻的方法、结构及元器件散热设备
CN105575934A (zh) 一种ccga焊接模拟芯片
CN111306970A (zh) 热交换器
US8441134B2 (en) Chip stacking structure
CN106158816A (zh) 封装基板
CN205789112U (zh) 电路板及应用该电路板的存储器
CN221079998U (zh) 双面散热封装结构以及电子元器件
TWI836695B (zh) 用於窗口型球柵陣列封裝的基板結構
CN203721955U (zh) 电连接器
CN212034450U (zh) Csp类型的封装结构
US11129299B2 (en) Heat sink

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant