CN205680672U - Micro-space packaging structure - Google Patents
Micro-space packaging structure Download PDFInfo
- Publication number
- CN205680672U CN205680672U CN201620548615.2U CN201620548615U CN205680672U CN 205680672 U CN205680672 U CN 205680672U CN 201620548615 U CN201620548615 U CN 201620548615U CN 205680672 U CN205680672 U CN 205680672U
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- chip
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- covering portion
- width
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- 238000004806 packaging method and process Methods 0.000 title abstract 3
- 239000000758 substrate Substances 0.000 abstract description 7
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 239000011241 protective layer Substances 0.000 description 5
- 238000000059 patterning Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 150000002343 gold Chemical class 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
The utility model relates to a fine-pitch packaging structure, it contains circuit substrate, chip and fin, and this circuit substrate has a plurality of circuits, the thickness of circuit is between 4-8 mu m, just width between the circuit is between 10-18 mu m, and this chip sets up in this circuit substrate, the front of this chip towards this circuit substrate's surface and with circuit electric connection, this fin sets up in this surface of the back of this chip and this circuit substrate to guide the produced heat energy of this chip to air and this circuit substrate, this fine-pitch packaging structure borrows by circuit and this fin reach the micronization and quick radiating efficiency simultaneously.
Description
Technical field
The utility model is with regard to a kind of encapsulating structure, particularly a kind of encapsulating structure with micro-pitch lines.
Background technology
In order to meet electronic goods microminiaturization and dynamical demand, it will usually make chip volume microminiaturization, and pass through IC
Design promotes chip usefulness to meet demand, therefore the lead piece in microminiaturization chip (such as connection pad or projection) and lead piece it
Between spacing also must be with microminiaturization.
Existing known circuit base plate is to be for electrically connecting to chip, and this circuit base plate has multiple circuit, described circuit
Via made by patterned metal layer, therefore the thickness of this metal level will affect in patterning processes adjacent lines it
Between spacing, say, that when the thickness of this metal level is thicker, the spacing between adjacent lines is bigger, and works as adjacent lines
Between spacing bigger when, the circuit on this circuit base plate can be caused cannot to coordinate the lead piece in microminiaturization chip so that should
Circuit base plate cannot be electrically connected with microminiaturization chip.
Content of the invention
Main purpose of the present utility model is, provides a kind of micro-pitch packages structure, to be solved technical problem is that
Reduce line thicknesses to shorten the spacing between adjacent lines so that circuit base plate forms micro-spacing (fine pitch) circuit,
It is for electrically connecting to microminiaturization chip.
The purpose of this utility model and solve it and technical problem is that and realize by the following technical solutions.The utility model
One micro-pitch packages structure, it comprises circuit base plate, chip and fin, and this circuit base plate has multiple circuit, described
The thickness of circuit, between 4-8 μm, has micro-spacing between two adjacent this circuits, and the width of this micro-spacing is between 10-
Between 18 μm, the surface of this circuit base plate has chip setting area and at least one connects district, and this connects district and is positioned at this chip and sets
Putting outside district, this chip is arranged at this chip setting area and appears this and connect district, and this chip has front and the back side, and this just faces
To this surface of this circuit base plate, this chip and described circuit are electrically connected with, this fin be arranged at this chip this back side and
This connects district.
The purpose of this utility model and solve its technical problem and also can be applied to the following technical measures to achieve further.
Aforesaid micro-pitch packages structure, wherein this fin at least has integrally formed covering portion, the first side cladding
Portion and the first junction, this first side covering portion is positioned between this covering portion and this first junction, and this covering portion is arranged at this
This back side of chip, this first side covering portion covers the first side of this chip, and this first junction is arranged at this and connects district.
Aforesaid micro-pitch packages structure, wherein this fin separately has the second side covering portion and the second junction, and this is years old
Two side covering portion are positioned between this covering portion and this second junction, and this second side covering portion covers the second side of this chip,
This second side is the opposite face of this first side, and this second junction is arranged at this and connects district.
Aforesaid micro-pitch packages structure, wherein has the first width between the 3rd side of this chip and the 4th side,
4th side is the opposite face of the 3rd side, and this covering portion has the first edge and the second edge, and this first edge is neighbouring
3rd side, this second edge, adjacent to the 4th side, has the second width between this first edge and this second edge, should
There is between this front of chip and this back side thickness, and have between this front of this chip and this surface of this circuit base plate
Gap, this second width is not more than the summation in this first width, this thickness of twice and this gap of twice.
Aforesaid micro-pitch packages structure, wherein this second width is substantially equal to this first width.
Aforesaid micro-pitch packages structure, wherein this covering portion at least has main part and the first outside portion, this main part
Being arranged at this back side of this chip, this first outside portion covers the 3rd side, and this second width is more than this first width.
Aforesaid micro-pitch packages structure, wherein this first edge is the edge of this first outside portion, and this first edge is not
Contact this circuit base plate.
Aforesaid micro-pitch packages structure, wherein this covering portion separately has the second outside portion, this main body section in this first
Between outside portion and this second outside portion, this second outside portion covers the 4th side.
Aforesaid micro-pitch packages structure, wherein this first side covering portion has the 3rd edge and the 4th edge, and the 3rd
Edge is adjacent to this first edge, and the 4th edge, adjacent to this second edge, has between the 3rd edge and the 4th edge
Three width, the 3rd width is less than this second width.
Aforesaid micro-pitch packages structure, it additionally comprises primer, and this primer is filled in this front and this circuit of this chip
Between this surface of substrate, this first side covering portion hides this primer.
The utility model compared with prior art has clear advantage and beneficial effect.The utility model is by restriction institute
State the thickness of circuit between 4-8 μm, make the width of patterned this formed micro-spacing between 10-18 μm, with
Improve the miniaturization degree of described circuit.
Described above is only the general introduction of technical solutions of the utility model, in order to better understand skill of the present utility model
Art means, and can be practiced according to the content of specification, and in order to allow above and other purpose of the present utility model, feature
Can become apparent with advantage, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, describe in detail as follows.
Brief description
Fig. 1: according to first embodiment of the present utility model, the exploded perspective view of a kind of micro-pitch packages structure.
Fig. 2: according to first embodiment of the present utility model, the combination stereogram of this micro-pitch packages structure.
Fig. 3: according to first embodiment of the present utility model, the upward view of circuit base plate and chip.
Fig. 4: according to first embodiment of the present utility model, the sectional view of this micro-pitch packages structure.
Fig. 5: according to first embodiment of the present utility model, the sectional view of this micro-pitch packages structure.
Fig. 6: according to the second embodiment of the present utility model, the exploded perspective view of a kind of micro-pitch packages structure.
Fig. 7: according to the second embodiment of the present utility model, the combination stereogram of this micro-pitch packages structure.
Fig. 8: according to the second embodiment of the present utility model, the upward view of fin.
Fig. 9: according to the second embodiment of the present utility model, the sectional view of this micro-pitch packages structure.
Figure 10: chip temperature test analysis figure.
[main element symbol description]
100: micro-pitch packages structure 110: circuit base plate
111: surface 111a: chip setting area
111b: connect district 112: circuit
113: support plate 114: protective layer
120: chip 121: front
122: the back side 123: the first side
124: the second sides 125: the three side
126: the four sides 127: connector
130: fin 131: covering portion
131a: the first the 131b: the second edge, edge
131c: main part the 131d: the first outside portion
131e: the second outside portion 132: the first side covering portion
132a: the three the 132b: the four edge, edge
133: the first junction 134: the second side covering portion
134a: the five the 134b: the six edge, edge
135: the second junctions 140: primer
D: thickness F P: micro-spacing
G: gap the W1: the first width
W2: the second width the W3: the three width
W4: the four width
Detailed description of the invention
Referring to Fig. 1 and Fig. 2, which is first embodiment of the present utility model, a kind of micro-pitch packages structure 100 comprises line
Base board the 110th, chip 120 and fin 130, this chip 120 is positioned between this circuit base plate 110 and this fin 130, this line
The surface 111 of base board 110 has chip setting area 111a and at least one connects district 111b, and this connects district 111b and is positioned at this core
Outside the 111a of piece setting area, this chip 120 is arranged at this chip setting area 111a and appears this and connect district 111b, this chip 120
Having front 121 and the back side 122, this front 121, towards this surface 111 of this circuit base plate 110, has this fin flexual
130 are arranged at this back side 122 and this connects district 111b, and this fin 130 is in order to guide this produced heat energy of chip 120 to empty
Gas and this circuit base plate 110, reaching effect of quick heat radiating, it is preferred that the material of this fin 130 can be selected from containing gold,
Copper or the Heat Conduction Material of aluminium, in the present embodiment, this circuit base plate 110 is copper clad laminate.
Referring to Fig. 3 and Fig. 4, this circuit base plate 110 has multiple circuit 112, this chip 120 and described circuit 112 electricity
Property connect, in the present embodiment, this chip 120 is with multiple connectors 127 being arranged at this front 121 and described circuit 112
Being electrically connected with, it is preferred that this circuit base plate 110 additionally comprises support plate 113 and protective layer 114, described circuit 112 is positioned at this support plate
Between 113 and this protective layer 114, this protective layer 114 covers described circuit 112 and appears this chip setting area 111a, in this reality
Executing in example, this chip setting area 111a is positioned at the surface of this support plate 113, and this connects the surface that district 111b is positioned at this protective layer 114.
Refer to Fig. 3, there is between adjacent two this circuits 112 micro-spacing FP, described circuit 112 and described micro-spacing
FP is to be formed via the metal level (figure is not drawn) patterning this circuit base plate 110, owing to the thickness of this metal level is between 4-8
Between μm, therefore in patterning processes, can control the width of described micro-spacing FP between described circuit 112 between
Between 10-18 μm, to reach the purpose of circuit miniaturization, in the present embodiment, the thickness of described circuit 112 is substantially equal to this gold
Belonging to the thickness of layer, the thickness of i.e. described circuit 112 is between 4-8 μm.
Referring to Fig. 1, Fig. 2 and Fig. 4, this chip 120 separately has the first side 123 and the second side 124, this second side
The opposite face that 124 is this first side 123, in the present embodiment, this fin 130 at least has integrally formed covering portion
131st, the first side covering portion 132 and the first junction 133, this first side covering portion 132 is positioned at this covering portion 131 and this first is led
Connecing between portion 133, it is preferred that this fin 130 separately has the second side covering portion 134 and the second junction 135, this second side is wrapped
Covering portion 134 to be positioned between this covering portion 131 and this second junction 135, this covering portion 131 is arranged at this back of the body of this chip 120
Face 122, this first side covering portion 132 covers this first side 123 of this chip 120, and this second side covering portion 134 covers this core
This second side 124 of piece 120, this first junction 133 and this second junction 135 are respectively arranged at this and connect district 111b.
Referring to Fig. 4, in the present embodiment, this micro-pitch packages structure 100 separately has primer 140, and this primer 140 is filled
Between this front 121 of this chip 120 and this surface 111 of this circuit base plate 110, this first side covering portion 132 and this
Two side covering portion 134 hide this primer 140, so that this fin 130 is fitted with this chip 120 and this circuit base plate 110.
Referring to Fig. 1 and Fig. 5, in the present embodiment, this chip 120 separately has the 3rd side 125 and the 4th side 126,
The opposite face that 4th side 126 is the 3rd side 125, has first between the 3rd side 125 and the 4th side 126
Width W1, this first width W1 are the beeline between the 3rd side 125 and the 4th side 126, and this covering portion 131 has
Having the first edge 131a and the second edge 131b, this first edge 131a is adjacent to the 3rd side 125, and this second edge 131b is adjacent
This four side 126 nearly, has the second width W2 between this first edge 131a and this second edge 131b, this second width W2
For the beeline between this first edge 131a and this second edge 131b.
Refer to Fig. 5, in the present embodiment, between this front 121 of this chip 120 and this back side 122, there is thickness D,
This thickness D is the beeline between this front 121 and this back side 122, and this front 121 of this chip 120 and this circuit base
Having clearance G between this surface 111 of plate 110, wherein, this surface 111 is the surface of this support plate 113, and this clearance G is this front
Beeline between 121 and this surface 111, it is preferred that this second width W2 is not more than this first width W1, this thickness of twice
D and the summation of this clearance G of twice, in the present embodiment, this second width W2 is substantially equal to this first width W1, or at it
In his embodiment, this second width W2 is greater than the half of this first width W1 and is less than this first width W1.
Refer to Fig. 6, Fig. 7 and Fig. 8, which is the second embodiment of the present utility model, this second embodiment and this first reality
The difference executing example is that this covering portion 131 has main part 131c and the first outside portion 131d, it is preferred that this covering portion 131 is another
Having the second outside portion 131e, this main part 131c is positioned between this first outside portion 131d and this second outside portion 131e, should
Main part 131c is arranged at this back side 122 of this chip 120, and this first outside portion 131d covers the 3rd side of this chip 120
Face 125, this second outside portion 131e covers the 4th side 126 of this chip 120, in the present embodiment, this covering portion 131
This first edge 131a is the edge of this first outside portion 131d, and this second edge 131b of this covering portion 131 is that this is outside second
The edge of sidepiece 131e, therefore this second width W2 is more than this first width W1.
Referring to Fig. 8, in the present embodiment, this first side covering portion 132 has the 3rd edge 132a and the 4th edge
132b, the 3rd edge 132a adjacent to this first edge 131a, the 4th edge 132b adjacent to this second edge 131b, the 3rd
Between edge 132a and the 4th edge 132b, there is the 3rd width W3, the 3rd width W3 be the 3rd edge 132a and this
Beeline between four edge 132b, this second side covering portion 134 has the 5th edge 134a and the 6th edge 134b, and this is years old
Five edge 134a are adjacent to this first edge 131a, and the 6th edge 134b is adjacent to this second edge 131b, the 5th edge 134a
And the 6th have the 4th width W4 between edge 134b, the 4th width W4 is the 5th edge 134a and the 6th edge
Beeline between 134b, wherein, the 3rd width W3 be less than this second width W2, and the 4th width W4 less than this second
Width W2.
Refer to Fig. 9, in the present embodiment, when this fin 130 fits in this chip 120 and this circuit base plate 110,
This first edge 131a of this covering portion 131 and this second edge 131b will not contact this circuit base plate 110, therefore this fin
Between 130 and this circuit base plate 110, there is space, in this first embodiment of the present utility model or this second embodiment, by
Confined space will not be formed between this fin 130 and this circuit base plate 110, therefore when heat energy produced by this chip 120
When causing volume of air to expand, the air of expansion can be discharged by the space between this fin 130 and this circuit base plate 110, with
Avoid causing this fin 130 buckling deformation to depart from this circuit base plate 110 or this chip 120 because air expands.
Referring to Figure 10 and following table, which is chip temperature test analysis figure, control group does not have this fin 130, by
Change line thicknesses, to observe the chip temperature in this control group, this first embodiment and this second embodiment, works as line thicknesses
When thinner, the resistance value of circuit can be bigger, then chip temperature can be caused higher, compare control group and this first embodiment and this
Two embodiments can clearly find, this fin 130 of the present utility model can effectively slow down really to be made because line resistance value is excessive
The high temperature becoming, for example, when line thicknesses is 4 μm, the chip temperature of control group is 161.6 DEG C, this first embodiment
Chip temperature is 121.0 DEG C, and the chip temperature of this second embodiment is 109.9 DEG C, and this fin 130 can make chip temperature reduce
About 40-50 DEG C, damage because of high temperature to be prevented effectively from chip.
| Line thicknesses (μm) | 4 | 6 | 8 | 12 |
| Control group | 161.6℃ | 141.1℃ | 130.3℃ | 119.5℃ |
| First embodiment | 121.0℃ | 112.7℃ | 106.9℃ | 99.6℃ |
| Second embodiment | 109.9℃ | 103.2℃ | 98.7℃ | 92.8℃ |
Referring again to Figure 10, there is this first embodiment chip temperatures (121.0 DEG C) of 4 μm of circuits close to having 12 μm of lines
This control group chip temperature (119.5 DEG C) on road, and this second embodiment chip temperature (109.9 DEG C) with 4 μm of circuits is low
In this control group chip temperature (119.5 DEG C) with 12 μm of circuits, it follows that this micro-pitch packages of the present utility model knot
Structure 100 can be reached miniaturization (fine pitch) simultaneously by the thickness of this circuit 112 of control and this fin 130 and quickly dissipate
Effect of heat, to effectively improve the usefulness of product.
The above, be only preferred embodiment of the present utility model, not the utility model is done any in form
Restriction, although the utility model is disclosed above with preferred embodiment, but is not limited to the utility model, any ripe
Know professional and technical personnel, in the range of without departing from technical solutions of the utility model, when in the technology of available the disclosure above
Hold and make a little Equivalent embodiments changing or be modified to equivalent variations, as long as without departing from technical solutions of the utility model
Hold, according to technical spirit of the present utility model to any simple modification made for any of the above embodiments, equivalent variations and modification, all still
In the range of belonging to technical solutions of the utility model.
Claims (10)
1. a micro-pitch packages structure, it is characterised in that it comprises:
Circuit base plate, has multiple circuit, and the thickness of described circuit, between 4-8 μm, has between two adjacent this circuits
Having micro-spacing, the width of this micro-spacing is between 10-18 μm, and the surface of this circuit base plate has chip setting area and at least
Individual connecting district, this connects district and is positioned at outside this chip setting area；
Chip, is arranged at this chip setting area and appears this and connect district, and this chip has front and the back side, and this is just facing to this line
This surface of base board, this chip is electrically connected with described circuit；And
Fin, is arranged at this back side of this chip and this connects district.
2. micro-pitch packages structure according to claim 1, it is characterised in that: wherein this fin at least has one one-tenth
The covering portion of shape, the first side covering portion and the first junction, this first side covering portion is positioned at this covering portion and this first junction
Between, this covering portion is arranged at this back side of this chip, and this first side covering portion covers the first side of this chip, and this first is led
The portion of connecing is arranged at this and connects district.
3. micro-pitch packages structure according to claim 2, it is characterised in that: wherein this fin separately has the second side bag
Covering portion and the second junction, this second side covering portion is positioned between this covering portion and this second junction, this second side covering portion
Covering the second side of this chip, this second side is the opposite face of this first side, and this second junction is arranged at this and connects
District.
4. micro-pitch packages structure according to claim 2, it is characterised in that: wherein the 3rd side and the 4th of this chip
Having the first width between side, the 4th side is the opposite face of the 3rd side, and this covering portion has the first edge and
Two edges, this first edge adjacent to the 3rd side, this second edge adjacent to the 4th side, this first edge and this second limit
There is between edge the second width, there is between this front of this chip and this back side thickness, and this front of this chip and this line
Having gap between this surface of base board, this second width is not more than this first width, this thickness of twice and this gap of twice
Summation.
5. micro-pitch packages structure according to claim 4, it is characterised in that: wherein this second width is substantially equal to be somebody's turn to do
First width.
6. micro-pitch packages structure according to claim 4, it is characterised in that: wherein this covering portion at least has main part
And first outside portion, this main part is arranged at this back side of this chip, and this first outside portion covers the 3rd side, and this is second wide
Degree is more than this first width.
7. micro-pitch packages structure according to claim 6, it is characterised in that: wherein this first edge is that this is outside first
The edge in portion, this first edge does not contact this circuit base plate.
8. micro-pitch packages structure according to claim 6, it is characterised in that: wherein this covering portion separately has outside second
Portion, this main body section is between this first outside portion and this second outside portion, and this second outside portion covers the 4th side.
9. the micro-pitch packages structure according to claim 4 or 6, it is characterised in that: wherein this first side covering portion has
3rd edge and the 4th edge, the 3rd edge adjacent to this first edge, the 4th edge adjacent to this second edge, the 3rd limit
Having the 3rd width between edge and the 4th edge, the 3rd width is less than this second width.
10. micro-pitch packages structure according to claim 2, it is characterised in that: it additionally comprises primer, and this primer is filled in
Between this front of this chip and this surface of this circuit base plate, this first side covering portion hides this primer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105109267 | 2016-03-24 | ||
| TW105109267A TW201735277A (en) | 2016-03-24 | 2016-03-24 | Fine pitch package structure |
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| CN205680672U true CN205680672U (en) | 2016-11-09 |
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| CN201620548615.2U Active CN205680672U (en) | 2016-03-24 | 2016-06-07 | Micro-space packaging structure |
| CN201610399692.0A Pending CN107230665A (en) | 2016-03-24 | 2016-06-07 | Micro-space packaging structure |
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| JP (1) | JP2017175097A (en) |
| KR (1) | KR20170112866A (en) |
| CN (2) | CN205680672U (en) |
| TW (1) | TW201735277A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107230665A (en) * | 2016-03-24 | 2017-10-03 | 颀邦科技股份有限公司 | Micro-space packaging structure |
| CN110265381A (en) * | 2018-03-12 | 2019-09-20 | 颀邦科技股份有限公司 | Semiconductor package and its circuit base plate |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113327899A (en) * | 2021-04-22 | 2021-08-31 | 成都芯源系统有限公司 | Flip chip packaging unit and packaging method |
| CN113725169A (en) * | 2021-04-22 | 2021-11-30 | 成都芯源系统有限公司 | Flip chip packaging unit and related packaging method |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09139450A (en) * | 1995-11-13 | 1997-05-27 | Sony Corp | Fixing method for heat sink |
| JPH11163494A (en) * | 1997-11-28 | 1999-06-18 | Toshiba Corp | Mounting method of surface-mounting device, mounting structure of bga package and electronic device |
| JP2000156460A (en) * | 1998-11-20 | 2000-06-06 | Mitsui High Tec Inc | Semiconductor device |
| JP4709813B2 (en) * | 2003-12-05 | 2011-06-29 | 三井金属鉱業株式会社 | Printed wiring board, circuit device, and printed wiring board manufacturing method |
| KR20120053332A (en) * | 2010-11-17 | 2012-05-25 | 삼성전자주식회사 | Semiconductor package and method of forming the same |
| TW201735277A (en) * | 2016-03-24 | 2017-10-01 | 頎邦科技股份有限公司 | Fine pitch package structure |
-
2016
- 2016-03-24 TW TW105109267A patent/TW201735277A/en unknown
- 2016-06-07 CN CN201620548615.2U patent/CN205680672U/en active Active
- 2016-06-07 CN CN201610399692.0A patent/CN107230665A/en active Pending
- 2016-06-08 JP JP2016114287A patent/JP2017175097A/en active Pending
- 2016-06-16 KR KR1020160074950A patent/KR20170112866A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107230665A (en) * | 2016-03-24 | 2017-10-03 | 颀邦科技股份有限公司 | Micro-space packaging structure |
| CN110265381A (en) * | 2018-03-12 | 2019-09-20 | 颀邦科技股份有限公司 | Semiconductor package and its circuit base plate |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20170112866A (en) | 2017-10-12 |
| CN107230665A (en) | 2017-10-03 |
| JP2017175097A (en) | 2017-09-28 |
| TW201735277A (en) | 2017-10-01 |
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