CN204516758U - 具低电感配置内部负载和辅助连接装置的功率半导体模块 - Google Patents

具低电感配置内部负载和辅助连接装置的功率半导体模块 Download PDF

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CN204516758U
CN204516758U CN201520108738.XU CN201520108738U CN204516758U CN 204516758 U CN204516758 U CN 204516758U CN 201520108738 U CN201520108738 U CN 201520108738U CN 204516758 U CN204516758 U CN 204516758U
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load
power
switch
sub
potential region
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M·施庞
E·法勒
L·罗伊瑟
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Semikron GmbH and Co KG
Semikron Elektronik GmbH and Co KG
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Semikron GmbH and Co KG
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    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/0979—Redundant conductors or connections, i.e. more than one current path between two points
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
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    • H—ELECTRICITY
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    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10174—Diode

Abstract

提供一种具低电感配置内部负载和辅助连接装置的功率半导体模块。基片具有多个负载电势区域和辅助电势区域，其中功率开关安排在第一负载电势区域上，所述功率开关实施为串联安排的多个可控功率子开关。功率子开关具有负载接合连接，该负载接合连接由到第二负载电势区域的多个负载接合线构成，其中第一接合基部安排在该第二负载电势区域上并且对应的负载接合线的相邻的第二接合基部安排在该功率子开关的接触区域上。特别地，控制接合线使两个分配的辅助电势区域彼此电连接并且平行接合线是平行于所述控制接合线安排的，所述平行接合线仅电连接到负载电势区域中的一个负载电势区域。

Description

具低电感配置内部负载和辅助连接装置的功率半导体模块
技术领域
本实用新型描述了一种功率半导体模块，特别是半桥安排的功率半导体模块，该功率半导体模块包括现有技术中常规配置的负载端子元件和辅助端子元件，并且还包括低电感配置的模块内部负载连接装置和辅助连接装置。
背景技术
通过举例，DE 39 37 045 A1中披露的现有技术披露了一种功率半导体模块，该功率半导体模块包括至少一个半桥，包括用于在三个模块主端子与半导体开关之间运送电流的三条主端子线，并且包括陶瓷基片，该陶瓷基片上存在有用于连接并联功率晶体管的连接导体轨道。在这种情况下，为减小模块内部电感，这三条主端子线由彼此相距小距离的宽条带构成。
此外，DE 100 37 533 A1披露了一种具有低内部寄生电感的半桥拓朴结构的电路安排。为此目的，提出了串联地安排两个功率开关各自的功率晶体管并且在单独的功率晶体管之间安排指状接触元件。通过这种压力接触式安排，在这类电路安排中实现了非常低的寄生电感。
这两个文献的共同之处在于它们针对的是负载端子元件的配置及其在功率半导体模块内部中的安排，而不进一步考虑其上安排有功率半导体部件的基片以及其连接装置的配置。
实用新型内容
通过对所述情况的认识，贯穿本实用新型所基于的目的是配置一种功率半导体模块，以使得特别是在预先限定的标准尺寸和通过技术上常规的对负载端子元件和辅助端子元件定位的范围内，以特别均匀的低电感方式实现实施为线式接合连接的模块内部连接装置。
根据本实用新型的这个目标是通过包括以下的特征的功率半导体模块实 现的。对应的从属权利要求中描述了优选的实施例。
在根据本实用新型包括有用于产生外部接触的负载端子元件和辅助端子元件的功率半导体模块情况下，模块内部负载连接装置以及优选同时或可替代地辅助连接装置具有低电感配置。模块内部负载连接装置特别是在负载端子元件、基片的导体轨道与功率半导体部件的接触区域之间的或者到其上的线式接合连接。
在这种情况下，基片具有多个负载电势区域和辅助电势区域，其中辅助电势区域特别是被实施为控制电势区域或传感器电势区域，并且负载电势区域具有正的或负的直流电压电势或交流电压电势。
在这种第一负载电势区域上安排功率开关，所述功率开关被实施为多个可控功率子开关，这些可控功率子开关是串联安排的并且在各自情况下特别是被实施为场效应晶体管、特别是MOS-FET，或者实施为双极晶体管、特别是带有并联的反向连接的续流二极管的IGBT。
功率子开关在各自情况下具有负载接合连接，该负载接合连接由到第二负载电势区域的多个平行安排的负载接合线构成，其中第一接合基部安排在第二负载电势区域上，并且对应的负载接合线的相邻的第二接合基部安排在该功率子开关的接触区域上。模块内部均匀、低电感的配置是凭借以下事实产生的：
功率半导体模块，包括负载端子元件和辅助端子元件，包括具有低电感配置的模块内部负载连接装置和辅助连接装置，包括带有多个负载电势区域和辅助电势区域的基片，其中，功率开关安排在第一负载电势区域上，所述功率开关实施为多个可控功率子开关，这些可控功率子开关是串联安排的并且在各自情况下通过分配的负载接合连接连接到第二负载电势区域，该分配的负载接合连接由多个平行安排的负载接合线构成，其中第一接合基部安排在该第二负载电势区域上并且对应的负载接合线的相邻的第二接合基部安排在该功率子开关的接触区域上，其中
a)控制接合线使两个分配的辅助电势区域彼此电连接并且平行接合线与所述控制接合线平行地安排，所述平行接合线仅电连接到负载电势区域中的一 个负载电势区域，并且
b)功率子开关的多个分配的负载接合线的对应的第一接合基部朝向串联的功率子开关的中心以与分配的负载接合线的直线路线偏置的方式安排，其中功率子开关串联非居中安排，所述直线路线垂直于该对应的功率子开关的边缘，并且
c)该第二负载电势区域具有电流方向并且负载接合线的从第一接合基部到最近的第二接合基部的那些接合线区段的长度从一个功率子开关到另一个功率子开关增大，该另一个功率子开关在该电流方向上与该一个功率子开关相邻。
在这种情况下，负载接合线的路线应该理解为是指其从对应的第二负载电势区域到其末端的整个路线，还特别是，功率子开关(包括带有其接触区域的触点)上方的路线。
在这种情况下，有利的是平行接合线具有的长度是分配的控制接合线的长度的80％至120％，特别是90％至110％。在这种情况下，这种接合线或接合线区段的长度(从第一接合基部到相邻的第二接合基部的长度)应该理解为始终是指在接合线的路线上从该第一接合基部的中心到相邻的第二接合基部的中心测量出的该段接合线的几何长度。
在一个优选配置中，平行接合线与分配的控制接合线相距的最大距离是最小安全距离的1.5倍。在这种情况下，安全距离应该理解成始终是指安全标准限定的必要的几何距离，特别是就绝缘强度或人员安全性而言的。在这方面，典型的测试电压比功率半导体模块的额定操作电压大出例如3至5倍。当然在这种情况下还考虑的是，平行接合线与控制接合线之间介质的相对介电常数，所述介质是以技术上常规的方式实现的，通常是硅胶。
在控制接合线的电势与平行接合线的电势之间有低电势差，特别是至多50V的情况下，优选的是控制接合线和平行接合线被安排成按该基片的机械边界条件所允许地尽可能紧密地彼此相邻。
附图说明
从如图1至图6或者这些附图的部分中所展示的根据本实用新型的功率半 导体模块的示例性实施例的以下说明中，本实用新型的进一步的说明、有利的细节和特征是清楚的。
图1至图3通过总体视图即图1和通过细节视图即图2和图3示出了根据本实用新型的功率半导体模块。
图4示意性地示出了根据本实用新型的功率半导体模块的三维局部视图。
图5示出了根据本实用新型的功率半导体模块的电路安排。
图6示出了功率半导体模块的细节视图，以用于展示与本实用新型相关的特征。
具体实施方式
图1至图3示出了根据本实用新型的功率半导体模块1。在此，图1示出了总体视图，而图5示出了其中所实现的电路安排。图2和图3中的图示是根据图1的功率半导体模块1的放大的细节。
根据本实用新型的功率半导体模块1是以半桥拓朴结构实施的，并且因此以技术上常规的形式具有上部功率开关3和下部功率开关4。功率开关3、4二者在各自情况下是通过三个功率子开关30、32、34、40、42、44来实施的，这些功率子开关在此又在各自情况下被实施成带有分配的续流二极管302、322、342的绝缘栅双极晶体管(IGBT)300、320、340。不言而喻，对应地带有三个IGBT和三个续流二极管的这种配置还可以通过技术上常规的方式来改进而通用性不受限制。
对应的功率开关3、4被安排在第一基片2上，该第一基片由电绝缘主体构成，该电绝缘主体上安排有彼此电绝缘的导体轨道形式的多个负载电势区域20、22、24和辅助电势区域630、631。分配给上部功率开关3的基片2具有带正直流电压电势的第一负载电势区域20，功率开关3自身也安排在第一负载电势区域上。负载接合连接9从上部功率开关3的功率子开关30、32、34的背离该基片2的那些接触区域延伸到第二负载电势区域22，该第二负载电势区域在此具有交流电压电势。除此之外，基片2还具有带负直流电压电势的负载电势区域24。
第二基片(下部功率开关4的基片)原则上是以与上部功率开关3的基片 相对应的方式实施的。下部功率开关4的功率子开关40、42、44在此安排在具有交流电压电势的负载电势区域22上，该负载电势区域导电性地连接到该第一基片的具有交流电压电势的负载电势区域22。负载接合连接从下部功率开关4的功率子开关的背离该基片2的那些接触区域延伸至具有负直流电压电势的第二负载电势区域24，该第二负载电势区域连接到该第一基片的具有负直流电压势的负载电势区域24。直流电压负载端子元件10、14导电性地连接到第一基片的分配的负载电势区域20、24，同时成双实现的交流电压负载端子元件12导电性地连接到第二基片的分配的负载电势区域22。
上部功率开关3的和下部功率开关4的对应的功率子开关30、32、34、40、42、44因而在第一负载电势区域20、22上是串联安排的并且通过负载接合连接9而连接到第二负载电势区域22、24。于是所述第二负载电势区域22、24具有与这些串联的功率子开关平行延伸的电流方向220、240。这种配置为各功率子开关30、32、34、40、42、44产生了电流围绕其流动的不同的区域，所述区域直接就是其引起的寄生电感的原因。为了使这些对应的寄生电感的值尽可能接近彼此，在此根据本实用新型提出了功率半导体模块1的两种配置，这两种配置优选旨在联合实现。
首先，负载接合线90、92、94的第一接合基部950是以朝这些串联的功率子开关30、32、34、40、42、44的中心移位的方式安排的。在这种情况下，每个负载接合线90、92、94都具有安排在第二负载电势区域22、24上的第一接合基部950。负载接合线90、92、94，更准确地说是其接合线区段900、920、940从所述第一接合基部950延伸至分配的功率子开关30、32、34、40、42、44的接触区域上的第二接合基部951。对应的功率子开关在此在各自的情况下被实施成IGBT 300、320、340、400、420、440和分配的续流二极管302、322、342、402、422、442，其中原则上绝缘栅双极晶体管和续流二极管在第一负载电势区域20、22上的安排中的次序是任意的。因此，第二接合基部951可以安排在IGBT的接触区域上或安排在续流二极管的接触区域上。
以技术上常规的方式，每个负载接合线90、92、94在其路线上在第二接合基部951之后、甚至在例如IGBT的相同接触区域上具有另外的接合基部，并且在另外的路线中在续流二极管的接触区域上还具有另外的接合基部。如已 经提到的，在这种情况下IGBT和续流二极管的次序还可以互换。
凭借这个事实，即这种措施的结果是，在电流方向220、240上是功率子开关34、44处于第一位置的情况下，电流路径被缩短，而在该电流方向上功率子开关30、40是处于最后的在此为第三位置的情况下该电流路径220、240被加长，这些对应的寄生电感是彼此相匹配的，从而导致一种均匀的、低电感配置。图2通过举例在各自情况下突出显示了每个功率子开关30、32、34的从负载接合线90、92、94的第一接合基部950到第二接合基部951的接合线区段900、920、940的路线。
其次，负载接合线90、92、94的从第一接合基部950延伸到最近的第二接合基部951的接合线区段900、920、940的长度从功率子开关中的一个功率子开关到在电流方向上相邻的功率子开关增大。负载接合线90、92、94的在从对应的第二接合基部951前进的路线中的接合线区段900、920、940的长度通常是在技术上控制的，其结果是有可能仅对负载接合线的在第一接合基部950与第二接合基部951之间的长度产生影响。功率半导体模块1的第二种配置，也就是说在电流方向220、240上从功率子开关到功率子开关的电流路径长度加长，因此在更均匀配置的意义上带来了上述对应的寄生电感相对彼此的适配。
功率半导体模块1此外包括辅助端子元件，辅助端子元件在此被实施为辅助发射器端子50、温度传感器端子51和用于对可控功率子开关30、32、34、40、42、44进行驱动的控制端子53、54，以用于在此对作为功率子开关的组成部分的IGBT 300、320、340、400、420、440进行驱动。控制端子53、54特别是在基片2上被分配了多个辅助电势区域630、631。所述辅助电势区域在各自情况下是通过控制接合线70而彼此相连接的。
与所述控制接合线70平行地安排所谓的平行接合线80，所述平行接合线以通过仿真展现出的方式使控制接合线70中出现的寄生电感明显减少。平行接合线80在负载电势区域22上具有第一接合基部850、与分配给路线730的控制接合线70相平行的路线830、以及在同一个负载电势区域22(该负载电势区域上还安排第一接合基部850)上的第二接合基部851。如图4中以三维方式展示的，在控制接合线70与平行接合线80的整个路线上，距离800是相 同的。这个距离应该是最小的，但必须具有考虑到不同电势的最小安全距离，所述安全距离是由功率半导体模块1的电参数限定的。在图3中在各自情况下通过举例突出显示了从控制接合线70的第一接合基部750到第二接合基部751的路线与分配的平行接合线80的路线。
图4示意性地示出了根据本实用新型的功率半导体模块1的对应的三维局部视图，其中在此展示了控制接合线70和分配的平行接合线80，并且还展示了接合基部750、751、850、851。
图6示出了功率半导体模块的示意性细节视图，以用于展示与本实用新型相关的特征。在此展示了四个功率半导体子开关30、32、34、36和相应分配的到第二负载电势区域的负载接合线90、92、94、96。根据本实用新型的一种配置，负载接合线90、92、94、96的从第一接合基部950到最近的第二接合基部951的那些接合线区段900、920、940、960的长度从一个功率子开关到在电流方向220上相邻的功率子开关增大。

Claims (12)

1.功率半导体模块(1)，包括负载端子元件(10，12，14)和辅助端子元件(50，51，53，54)，包括具有低电感配置的模块内部负载连接装置(9)和辅助连接装置(7)，包括带有多个负载电势区域(20，22，24)和辅助电势区域(630，631)的基片(2)，其中，功率开关(3，4)安排在第一负载电势区域(20，22)上，所述功率开关实施为多个可控功率子开关(30，32，34，36，40，42，44)，这些可控功率子开关是串联安排的并且在各自情况下通过分配的负载接合连接(9)连接到第二负载电势区域(22，24)，该分配的负载接合连接由多个平行安排的负载接合线(90，92，94，96)构成，其中第一接合基部(950)安排在该第二负载电势区域(22，24)上并且对应的负载接合线(90，92，94，96)的相邻的第二接合基部(951)安排在该功率子开关的接触区域上，其中
a)控制接合线(70)使两个分配的辅助电势区域(630，631)彼此电连接并且平行接合线(80)与所述控制接合线(70)平行地安排，所述平行接合线仅电连接到负载电势区域(22)中的一个负载电势区域，并且
b)功率子开关(30，34)的多个分配的负载接合线(90，92，94，96)的对应的第一接合基部(950)朝向串联的功率子开关(30，32，34，36)的中心以与分配的负载接合线(90，92，94，96)的直线路线偏置的方式安排，其中功率子开关(30，34)串联非居中安排，所述直线路线垂直于对应的功率子开关(30，34)的边缘，并且
c)该第二负载电势区域(22，24)具有电流方向(220，240)并且负载接合线(90，92，94，96)的从第一接合基部(950)到最近的第二接合基部(951)的那些接合线区段(900，920，940，960)的长度从一个功率子开关到另一个功率子开关增大，该另一个功率子开关在该电流方向(220，240)上与该一个功率子开关相邻。
2.根据权利要求1所述的功率半导体模块，其中
分配的负载接合线(90，92，94，96)的第一接合基部(950)全部是以朝向串联的功率子开关(30，32，34)的中心偏置的方式安排的。
3.根据权利要求1所述的功率半导体模块，其中
可控功率子开关(30，32，34，36，40，42，44)实施为场效应晶体管，或者双极晶体管。
4.根据权利要求3所述的功率半导体模块，其中
所述场效应晶体管是MOS-FET。
5.根据权利要求3所述的功率半导体模块，其中
所述双极晶体管是带有并联的反向连接的续流二极管(302，322，342)的IGBT(300，320，340)。
6.根据权利要求1所述的功率半导体模块，其中
负载电势区域(20，22，24)具有正直流电压电势或负直流电压电势或交流电压电势。
7.根据权利要求1所述的功率半导体模块，其中
辅助电势区域(630，631)具有驱动电势。
8.根据权利要求1所述的功率半导体模块，其中
平行接合线(80)具有的长度是分配的控制接合线(70)长度的80％至120％。
9.根据权利要求8所述的功率半导体模块，其中
平行接合线(80)具有的长度是分配的控制接合线(70)长度的90％至110％。
10.根据权利要求1所述的功率半导体模块，其中
在控制接合线(70)的电势与平行接合线(80)的电势之间有低电势差，该控制接合线和该平行接合线被安排成按该基片(2)的机械边界条件所允许地尽可能紧密地彼此相邻。
11.根据权利要求10所述的功率半导体模块，其中
所述低电势差至多为50V。
12.根据权利要求1所述的功率半导体模块，其中
平行接合线(80)与分配的控制接合线(70)相距的最大距离(800)是最小安全距离的1.5倍。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104851879A (zh) * 2014-02-18 2015-08-19 赛米控电子股份有限公司 具低电感配置内部负载和辅助连接装置的功率半导体模块

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102014111931B4 (de) 2014-08-20 2021-07-08 Infineon Technologies Ag Niederinduktive Schaltungsanordnung mit Laststromsammelleiterbahn
CN104576588B (zh) * 2015-01-20 2017-07-28 深圳希格玛和芯微电子有限公司 电器设备及其集成电路回路以及电路连接方法
DE102015120157A1 (de) 2015-11-20 2017-05-24 Semikron Elektronik Gmbh & Co. Kg Leistungselektronische Schalteinrichtung mit einer Mehrzahl von Potentialflächen
CN105470249A (zh) * 2015-11-23 2016-04-06 扬州国扬电子有限公司 一种功率模块
CN105374810A (zh) * 2015-11-23 2016-03-02 扬州国扬电子有限公司 一种功率模块
EP3246945B1 (en) * 2016-05-19 2018-10-03 ABB Schweiz AG Power module with low stray inductance
CN105914199B (zh) * 2016-06-17 2018-08-03 扬州国扬电子有限公司 一种并联芯片均流的功率模块
CN108074917B (zh) * 2016-11-16 2019-12-13 南京银茂微电子制造有限公司 一种多芯片并联的半桥型igbt模块
WO2018202620A1 (en) 2017-05-02 2018-11-08 Abb Schweiz Ag Half-bridge module with coaxial arrangement of the dc terminals
CN107731768B (zh) * 2017-09-08 2019-11-15 全球能源互联网研究院有限公司 一种igbt模块封装结构
CN107958905A (zh) * 2017-12-11 2018-04-24 臻驱科技（上海）有限公司 功率半导体模块衬底
CN108447846A (zh) * 2018-06-06 2018-08-24 臻驱科技（上海）有限公司 一种功率半导体模块衬底及功率半导体模块
CN108447847A (zh) * 2018-06-06 2018-08-24 臻驱科技（上海）有限公司 一种功率半导体模块衬底及功率半导体模块
EP3761361A4 (en) 2018-10-05 2021-11-17 Fuji Electric Co., Ltd. SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE AND VEHICLE
JP6875588B1 (ja) * 2020-09-18 2021-05-26 住友電気工業株式会社 半導体装置
EP4160677A1 (de) 2021-09-30 2023-04-05 Siemens Aktiengesellschaft Halbleiteranordnung mit mindestens zwei halbleiterelementen
JP2023090151A (ja) 2021-12-17 2023-06-29 三菱電機株式会社 半導体パワーモジュールおよび電力変換装置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3937045A1 (de) * 1989-11-07 1991-05-08 Abb Ixys Semiconductor Gmbh Leistungshalbleitermodul
JP2725952B2 (ja) * 1992-06-30 1998-03-11 三菱電機株式会社 半導体パワーモジュール
US6954368B1 (en) * 1996-07-22 2005-10-11 HYDRO-QUéBEC Low stray interconnection inductance power converting molecule for converting a DC voltage into an AC voltage, and a method therefor
US6249024B1 (en) * 1998-12-09 2001-06-19 International Rectifier Corp. Power module with repositioned positive and reduced inductance and capacitance
DE10037533C1 (de) * 2000-08-01 2002-01-31 Semikron Elektronik Gmbh Induktivitätsarme Schaltungsanordnung
DE10143932B4 (de) * 2001-09-07 2006-04-27 eupec Europäische Gesellschaft für Leistungshalbleiter mbH & Co. KG Shunt-Widerstandanordnung
US20030107120A1 (en) * 2001-12-11 2003-06-12 International Rectifier Corporation Intelligent motor drive module with injection molded package
US7327024B2 (en) * 2004-11-24 2008-02-05 General Electric Company Power module, and phase leg assembly
JP4426955B2 (ja) * 2004-11-30 2010-03-03 株式会社ルネサステクノロジ 半導体装置
JP4459883B2 (ja) * 2005-04-28 2010-04-28 三菱電機株式会社 半導体装置
JP2009512994A (ja) * 2005-06-24 2009-03-26 インターナショナル レクティファイアー コーポレイション 低インダクタンスの半導体ハーフブリッジモジュール
DE102007013186B4 (de) * 2007-03-15 2020-07-02 Infineon Technologies Ag Halbleitermodul mit Halbleiterchips und Verfahren zur Herstellung desselben
JP5107839B2 (ja) * 2008-09-10 2012-12-26 ルネサスエレクトロニクス株式会社 半導体装置
CN101593655B (zh) * 2009-07-17 2011-11-23 威海新佳电子有限公司 一种pdp功率集成模块及其制作方法
DE102010030317B4 (de) * 2010-06-21 2016-09-01 Infineon Technologies Ag Schaltungsanordnung mit Shuntwiderstand
EP2725609B1 (en) * 2011-06-27 2019-11-13 Rohm Co., Ltd. Semiconductor module
US8637964B2 (en) * 2011-10-26 2014-01-28 Infineon Technologies Ag Low stray inductance power module
JP5805513B2 (ja) * 2011-12-14 2015-11-04 三菱電機株式会社 電力用半導体装置
DE102014102018B3 (de) * 2014-02-18 2015-02-19 Semikron Elektronik Gmbh & Co. Kg Leistungshalbleitermodul mit niederinduktiv ausgestalteten modulinternen Last- und Hilfsverbindungseinrichtungen

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104851879A (zh) * 2014-02-18 2015-08-19 赛米控电子股份有限公司 具低电感配置内部负载和辅助连接装置的功率半导体模块
CN104851879B (zh) * 2014-02-18 2018-11-09 赛米控电子股份有限公司 具低电感配置内部负载和辅助连接装置的功率半导体模块

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