CN106252335B - 半导体模块、半导体模块装置和操作半导体模块的方法 - Google Patents
半导体模块、半导体模块装置和操作半导体模块的方法 Download PDFInfo
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- CN106252335B CN106252335B CN201610399304.9A CN201610399304A CN106252335B CN 106252335 B CN106252335 B CN 106252335B CN 201610399304 A CN201610399304 A CN 201610399304A CN 106252335 B CN106252335 B CN 106252335B
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Abstract
本发明涉及一种半导体模块,具有第一和第二半导体开关,其中每个具有第一和第二负载接口,在第一和第二负载接口之间形成的负载线路电串联在第一和第二电路节点之间。还包括电路载体装置,具有:介电的第一绝缘载体区段,具有第一顶面和第一底面;介电的第二绝缘载体区段,具有第二顶面和第二底面;施加到第一顶面上的第一上部金属化层;施加到第二顶面上的第二和第三上部金属化层;施加到第一底面上的第一下部金属化层;施加到第二底面上的第二下部金属化层;所述半导体模块具有非陶瓷介电绝缘层,被施加到第一以及第二下部金属化层上,并且非陶瓷介电绝缘层具有背向第一和第二下部金属化层的底面,该底面形成半导体模块的导热接触面。
Description
技术领域
本发明涉及电路领域,更具体地涉及一种半导体模块、半导体模块装置和操作半导体模块的方法。
背景技术
在半导体模块中,其具有两个可控的功率半导体开关,所述大功率半导体开关电串联成半电桥,串联电路在负载线路之间具有电路节点,所述电路节点通常处于输出端的电势上。与半电桥的正电源电势连接的功率半导体芯片则通常称为“High-Side Chip(高边芯片)”,与半电桥的负电源电势连接的功率半导体芯片相应地作为“Low-Side Chip(低边芯片)”。当在第一接通状态中使High-Side Chip导通并且使Low-Side Chip阻断时,电路节点基本上处于正电源电势上。当反之在第二接通状态中使High-Side Chip阻断并且使Low-Side Chip导通时,电路节点基本上处于负电源电势上。因此,通过适合地控制功率半导体芯片可以或者将正电源电势或者将负电源电势传导到输出端。在从第一接通状态变换到第二接通状态或者从第二接通状态变换到第一接通状态时,这在具有半电桥和与半电桥连接的包括相应的接口电路的中间电路电容器的系统中与系统的对称性相关地导致形成不可避免的共模电流和推挽电流,所述共模电流和推挽电流可以相互影响并且结果随之导致发射寄生辐射。例如DE 10 2013 210 146 A1公知的是,可以减少所述寄生发射,其方式是,一方面在正电源电势和接地线之间的电容与另一方面在负电源电势和接地线之间的电容选择为尽可能相等的。
当半导体模块应借助于冷却体来冷却时,冷却体通常与地连接。在此必须确保,冷却体相对于电源电势被充分地绝缘。为此,通常使用两侧金属化的陶瓷衬底,在所述陶瓷衬底中,陶瓷层布置在陶瓷层的两个电绝缘的金属化层之间。
在DE 10 2013 210 146 A1中,为此,两个分别金属化的陶瓷层布置在冷却体和通过冷却体散热的半导体芯片之间。在此,最紧邻冷却体安置的陶瓷层在其朝向冷却体的侧上具有下部金属化层,所述下部金属化层不仅确定了正电源电势和地线之间的电容,而且确定了负电源电势和地线之间的电容。
因为两个陶瓷层布置在每个半导体芯片和下部金属化层之间,以及由于需要的所述陶瓷层的厚度,这种布置具有在半导体芯片和安装在半导体模块上的冷却体之间高的热传递阻值。此外,这种基于各两个陶瓷层的布置由于其与此相关的材料使用并且以及与此相关的生产耗费的原因,成本非常高的。
发明内容
本发明的目的在于,提供一种半导体模块和一种半导体模块装置,其在操作中发射少的寄生辐射,以及提供一种用于操作所述半导体模块的方法。该目的通过根据权利要求1所述的半导体模块、通过根据权利要求15所述的半导体模块装置或者通过根据权利要求16所述的用于操作半导体模块的方法来实现。
第一方面涉及一种半导体模块。该半导体模块具有第一半导体开关、第二半导体开关、电路载体装置和非陶瓷介电绝缘层。所述第一半导体开关和第二半导体开关中的每一个具有一个第一负载接口和一个第二负载接口,在所述第一负载接口和所述第二负载接口之间形成负载线路。第一半导体开关的负载线路和第二半导体开关的负载线路电串联在第一电路节点和第二电路节点之间。电路载体装置具有:介电的第一绝缘载体区段,所述介电的第一绝缘载体区段具有第一顶面以及与所述第一顶面对置的第一底面;介电的第二绝缘载体区段,所述介电的第二绝缘载体区段具有第二顶面以及与所述第二顶面对置的第二底面;第一上部金属化层,所述第一上部金属化层被施加到第一顶面上;第二上部金属化层和第三上部金属化层,所述第二上部金属化层和第三上部金属化层被施加到第二顶面上;第一下部金属化层,所述第一下部金属化层被施加到第一底面上;以及第二下部金属化层,所述第二下部金属化层被施加到第二底面上。非陶瓷介电绝缘层被施加到第一下部金属化层上并且被施加到第二下部金属化层上,并且所述非陶瓷介电绝缘层的背向第一下部金属化层和第二下部金属化层的底面形成半导体模块的导热接触面。
第二方面涉及一种半导体模块装置,其具有根据第一方面所构造的半导体模块以及冷却体,所述冷却体能拆卸地或者材料配合地与半导体模块的介电绝缘层的底面连接。
第三方面涉及一种用于操作半导体模块的方法。为此,提供根据第一方面所构造的半导体模块。将第一电路节点连接到第一电源电势,并且将第一电路节点连接到不同于第一电源电势的第二电源电势连接。
附图说明
下面根据实施例参考附图说明本发明。在附图中,相同的附图标记表示相同的元件。附图中:
图1示出具有半导体模块和冷却体的半导体模块装置的电路图。
图2示出根据第一实例的半导体模块装置的竖直剖面图。
图3示出根据第二实例的半导体模块装置的竖直剖面图。
图4示出根据第三实例的半导体模块装置的竖直剖面图。
图5示出根据第四实例的半导体模块装置的竖直剖面图。
图6示出根据第五实例的半导体模块装置的竖直剖面图。
图7示出根据第六实例的半导体模块装置的竖直剖面图。
图8示出半导体模块的区段的竖直剖面图,其中,绝缘载体的上部金属化层和绝缘载体的下部金属化层之间的电连接围绕绝缘载体的侧向边缘。
图9示出半导体模块的俯视图,由所述俯视图得出第一下部金属化层的基面和第二下部金属化层的基面。
为了对相应的构造加以说明,附图中所示的布置不是按比例尺示出的。
具体实施方式
图1示出半导体模块装置的电路图,其具有半导体模块100和金属冷却体200。示出了第一半导体开关1和第二半导体开关2,所述第一半导体开关和第二半导体开关仅仅示例性地构造为n沟道IGBT。原则上,第一半导体开关1和第二半导体开关2彼此无关地并且彼此任意组合地构造为p沟道元件或n沟道元件,和/或构造为自导通的或自关断的元件。
在任何情况中,第一半导体开关1具有第一负载接口11和第二负载接口12,在所述第一负载接口和所述第二负载接口之间半导体开关1形成第一负载线路,并且第二半导体开关2具有第一负载接口21和第二负载接口22,在所述第一负载接口和所述第二负载接口之间形成第二负载线路。第一负载线路和第二负载线路电串联在第一电路节点71’和第二电路节点72’之间。为此,第一半导体开关1的第二负载接口12与第二半导体开关2的第一负载接口21电连接。
第一电路节点71’可以例如与半导体模块100的第一外部电接口71连接,或者所述第一电路节点可以通过半导体模块100的第一外部电接口71产生。相应地,第二电路节点72’可以例如与半导体模块100的第二外部电接口72连接,或者所述第二电路节点可以通过半导体模块100的第二外部电接口72产生。半导体模块100的“外部电接口”一般理解为下述的接口,半导体模块100可以从外部与所述接口电连接。
下述元件类型可以考虑用于第一半导体开关1和第二半导体开关2、特别是可控的半导体开关,这些开关具有控制接口,借助于所述控制接口可以使相关的半导体开关1,2的负载线路根据施加到控制接口上的控制电势可选地处于导通状态中(半导体开关被接通)或者处于关断状态中(半导体开关被关断)中。在图1中所示的电路图中,第一半导体开关1具有控制接口13,第二半导体开关2具有控制接口23。
适用于第一半导体开关1和第二半导体开关2的元件类型例如是MOSFET(MetalOxide Semiconductor Field-Effect Transistor,金属氧化物半导体场效应晶体管),IGBT(Insulated Gate Bipolar Transistor,绝缘栅双极型晶体管)、JFET(JunctionField-Effect Transistor,结型场效应晶体管)、HEMT(High Electron MobilityTransistor,高电子迁移率晶体管)、晶闸管或者这一类的晶体管。
根据元件类型,所述元件类型可以是相同的半导体开关1,2的第一/第二负载接口11/12,21/22、例如漏极/源极接口或源极/漏极接口或发射极/集电极接口或集电极/发射极接口或阳极/阴极接口或阴极/阳极接口,控制接口13,23是栅极接口或基极接口。
元件类型可以是横向元件或竖直元件,然而在HEMT的情况中仅仅是横向元件。
所述半导体开关1,2中的每一个可以通过恰好一个半导体芯片实现,然而或者通过两个或多个电并联的半导体芯片实现。通过所述并联电路可以例如提高载流量,和/或可以对于下述情况提供备用装置,即在并联电路的一个或多个半导体芯片故障的情况下也可以保持功能性和/或半导体开关1,2所需的载流量。
在根据图1的电路图中,分别将一个可选的空载二极管反向并联到每个半导体开关1,2的负载线路。这些(或至少两个同一方向地电并联的)空载二极管可以如同对应的半导体开关1或2那样地集成在相同的半导体芯片中,或者所述空载二极管可以作为独立的半导体芯片存在。原则上也可能的是,空载二极管布置在半导体模块100外部。
通过第一和第二半导体开关1,2的负载线路在第一电路节点71’和第二电路节点72’之间的串联电路产生具有第三电路节点73’的半电桥,所述第三电路节点导电地位于第一和第二半导体开关1,2的负载线路之间。在根据图1的实例中,第三电路节点73’与半导体模块100的外部接口73电连接。
为了给半电桥供给电压,向第一电路节点71’(例如通过外部接口71)输送第一电源电势DC+,并且向第二电路节点72’(例如通过外部接口72)输送与第一电源电势DC+不同的第二电源电势DC-。第一电源电势DC+可以例如大于第二电源电势DC-。例如第一电源电势DC+和第二电源电势DC-之间的差值可以是至少10V、至少100V或者甚至至少1000V。在将电压、即DC+和DC-之间的电势差施加在第一电路节点71’和第二电路节点72’之间的情况下,所述电压可以是直流电压或者至少是具有显著的直流电压分量的电压。
当在半电桥的第一接通状态中通过将适合的控制电势施加到第一控制接口13上使第一半导体开关1接通(也就是说,第一半导体开关1的负载线路导通)并且通过将适合的控制电势施加到第二控制接口23上使第二半导体开关2关断(也就是说,第二半导体开关2的负载线路断开)时,第三电路节点73’(并且由此在所述实例中也是外部接口73)处于第一电源电势DC+上(忽略第一负载上和低欧姆的电连接线路上的小的电压降)。
此外,当在半电桥的第二接通状态中通过将适合的控制电势施加到第一控制接口13上使第一半导体开关1关断(也就是说,第一半导体开关1的负载线路断开)并且通过将适合的控制电势施加到第二控制接口23上使第二半导体开关2接通(也就是说,第二半导体开关2的负载线路导通)时,第三电路节点73’(并且由此在所述实例中外部接口73也)处于第二电源电势DC-上(忽略第一负载上和低欧姆的电连接线路上的小的电压降)。
因此,通过在第一接通状态和第二接通状态切换可以使第三电路节点73’上的(输出)电势(并且由此在所述实例中也为外部接口73上的电势)VOUT(忽略所述小的电压降)在第一电源电势DC+和第二电源电势DC-之间切换。特别是输出电势VOUT通过在第一接通状态和第二接通状态高频地和重复地切换形成为交流电势。
此外,在图1中还示出不可避免的电容C1和C2,所述电容在半导体模块100或半导体模块装置的操作中在第一电路节点71’和地线之间或者在第二电路节点72’和地线之间产生。例如与半导体模块100热耦合的金属冷却体200处于接地电势上。此外,通过印制导线和导体面导致不可避免的电容C1和C2。
如同在前参考图1所述的那样,半导体模块100或者具有半导体模块100和冷却体的半导体模块装置的电路连接可以适用于每个根据本发明的半导体模块100或者适用于每个根据本发明的具有半导体模块100和冷却体的半导体模块装置,特别是适用于根据下述的实施例所述的半导体模块或者半导体模块装置。
图2示出具有半导体模块100和冷却体200的半导体模块装置的竖直剖面图。半导体模块100具有第一半导体开关1和第二半导体开关2。所述第一半导体开关1和第二半导体开关2中的每一个如同所述地通过恰好一个半导体芯片或者通过至少两个并联的半导体芯片实现。所述第一半导体开关1和第二半导体开关2中的每一个具有一个第一负载接口11,21和一个第二负载接口12,22。
半导体开关1,2布置在电路载体装置上。所述电路载体装置具有:介电的第一绝缘载体区段301,所述介电的第一绝缘载体区段具有第一顶面(301t)以及与所述第一顶面对置的第一底面301b;介电的第二绝缘载体区段302,所述介电的第二绝缘载体区段具有第二顶面302t以及与所述第二顶面对置的第二底面302b;第一上部金属化层311,所述第一上部金属化层被施加到第一顶面301t上;第二上部金属化层312,所述第二上部金属化层被施加到第二顶面302t上;第三上部金属化层313,所述第三上部金属化层同样被施加到第二顶面302t上;第一下部金属化层321,所述第一下部金属化层被施加到第一底面301b上;以及第二下部金属化层322,所述第二下部金属化层被施加到所述第二底面302b上。
在所示的实例中,介电的第一绝缘载体区段301和介电的第二绝缘载体区段302是电绝缘的绝缘载体30的彼此隔开间距的区段。绝缘载体30并且由此区段301,302也由电绝缘材料构成。非常适合的例如是电绝缘陶瓷、例如氧化铝(Al2O3)、氮化铝(AlN)、氧化铍(BeO)、氧化锆(ZrO2)、氮化硅(Si3N4),然而也非常适合的是其他陶瓷。
第一上部金属化层311、第二上部金属化层312、第三上部金属化层313、第一下部金属化层321和第二下部金属化层322由良好导电的材料、例如同或铜合金或者铝或铝合金构成。
第一上部金属化层311和第一下部金属化层321布置在第一绝缘载体区段301的彼此对置的侧上,并且直接地和材料配合地与所述第一绝缘载体区段连接。相应地,一方面第二上部金属化层312和第三上部金属化层313以及另一方面第二下部金属化层322布置在第二绝缘载体区段302的彼此对置的侧上,并且直接地和材料配合地与所述第二绝缘载体区段连接。
电路载体装置可以例如构造为DCB衬底,在所述DCB衬底中,绝缘载体30构造为氧化铝陶瓷薄板,并且在所述绝缘载体中,第一上部金属化层311、第一下部金属化层321、第二上部金属化层312、第二下部金属化层322以第三上部金属化层313分别构造为铜箔,所述铜箔借助于公知的DCB方法(DCB=Direct Copper Bonding,直接铜熔结)与绝缘载体30平面地连接。
第一上部金属化层311和第一下部金属化层321通过至少一个导电的连接元件51彼此导电地连接。第二上部金属化层312和第二下部金属化层322通过至少一个导电的连接元件52彼此导电地连接。导电的连接元件51可以例如构造为在第一绝缘载体区段301中的通孔敷镀。与此无关地,导电的连接元件52可以例如构造为在第二绝缘载体区段302中的通孔敷镀。
为了防止第一下部金属化层321和第二下部金属化层322与冷却体200接触,设置一个非陶瓷的介电绝缘层4,该非陶瓷的介电绝缘层被施加到第一下部金属化层321和第二下部金属化层322上并且材料配合地与所述第一下部金属化层和第二下部金属化层连接,并且所述非陶瓷的介电绝缘层不仅覆盖第一下部金属化层321的背向第一绝缘载体区段301的侧面,而且覆盖第二下部金属化层322的背向第二绝缘载体区段302的侧面并且与所述侧面电绝缘。为了实现在一方面下部金属化层321,322和另一方面冷却体200之间的良好的电绝缘,绝缘层4在20℃的温度下具有大于10GΩ·cm(1E10Ohm·cm)和/或大于10kV/mm的绝缘强度。
介电绝缘层4具有背向第一下部金属化层321和第二下部金属化层322的底面4b,所述底面形成半导体模块100的导热接触面。冷却体200与底面4b处于热接触的状态,从而在半导体模块100操作时在半导体开关1,2中产生的余热可以经过上部金属化层311,312,313、绝缘载体区段301,302、下部金属化层321,322和绝缘层4通过底面4b导出到冷却体200上。在冷却体200未安装在半导体模块100上的情况下,底面4b形成半导体模块100的外表面。
半导体模块100的内部的电路连接可以借助于任意导电的连接元件81,82例如压焊金属线、压焊细带、金属带等实现。
外部接口71与第一上部金属化层311持久地导电连接并且由此基于导电的连接元件51也与第一下部金属化层321持久地导电连接,并且外部接口72与第二上部金属化层312持久地导电连接并且由此基于导电的连接元件52也与第二下部金属化层322持久地导电连接。此外,外部接口73与第三上部金属化层313持久地导电连接。在此,“持久地导电连接”意味着,即彼此导电连接在时间上不间断地彼此导电连接。
在所示的实例中,第一半导体开关1布置在第一上部金属化层311上,并且第二半导体开关2布置在第三上部金属化层313上。然而在此仅仅涉及一个实例。例如第二半导体开关2同样也可以布置在第二上部金属化层312上。通常不仅第一半导体开关1而且第二半导体开关2可以布置在(必要时也多于仅仅三个)上部金属化层311,312,313的整体上,只要如同参考图1所述的那样由此可以实现一个半电桥。
如同根据图2可以看到的那样,半导体模块100可以具有至少三个彼此隔开间距的上部金属化层311,312,313。该上部金属化层311,312,313中的一个(在此为第一上部金属化层311)具有第一电路节点71’的电势(在此:第一电势DC+),所述上部金属化层311,312,313中的另外一个(在此为第二上部金属化层312)具有第二电路节点72’的电势(在此:第二电势DC-),并且所述上部金属化层311,312,313中的还另外一个(在此为第三上部金属化层313)具有第三电路节点73’的电势(在此:输出电势VOUT)。
用于电路载体装置的上部金属化层311,312,313的面积需要量主要通过用于安装半导体开关1和2所需的面积来确定。原则上有利的是,电路载体装置具有尽可能小的结构尺寸,并且由此导致,上部金属化层311,312,313的总基面是尽可能小的。此外,处于其他不同的原因可以值得期望的是,所述第一或第二半导体开关1,2中的一个安装在所述上部金属化层311,312,313中的具有半电桥的输出电势VOUT的那一个(必要时那几个)上(在此:在第三上部金属化层313上),并且另一个安装在上部金属化层311,312的具有电源电势(即所述第一电源电势DC+和第二电源电势DC-中的一个)的一个(必要时也多个)上(在此:在具有第一电源电势DC+的第一上部金属化层311上),而上部金属化层311,312,313中的剩余的那个(在此:第二上部金属化层312)可以装配有第一半导体开关1,还装配有第二半导体开关2,剩余的那个具有所述电源电势DC+,DC-中的另一个(在此:负电源电势DC-)。
作为结果,所述的范围条件导致,具有第一电路节点71’的电势的第一上部金属化层311和具有第二电路节点72’的电势的第二上部金属化层312中的一个装配有第一半导体开关1或者第二半导体开关2,而另一个装配有第一半导体开关1或者第二半导体开关2。基于此,第一上部金属化层311的那一个(那几个)的总基面尺寸与第二上部金属化层312那一个(那几个)的总基面尺寸明显不同,所述第一上部金属化层311具有第一电源电势(在此:DC+)、即第一电路节点71’的电势,所述第二上部金属化层312具有第二电源电势(在此:DC-)、即第二电路节点72’的电势。这又导致,电容C1和C2(见图1)会是明显不同的,这如同所述地是不期望的。
本发明通过以下方式应对所述问题,即第一下部金属化层321通过第一电连接51与第一电路节点71’的电势导电地连接,并且第二下部金属化层322通过第二电连接52与第二电路节点72’的电势导电地连接,第二下部金属化层的基面与第一下部金属化层321的基面的差别不是很大。由此,相对于地线(即例如相对于冷却体200)的电容C1和C2主要通过两个下部金属化层321和322的基面来确定。
电路载体装置在传统的半导体模块的情况下分别具有仅仅一个下部金属化层,所述下部金属化层与上部金属化层电绝缘,而根据本发明的半导体模块100具有至少两个下部金属化层321,322,所述至少两个下部金属化层电隔离,并且在半导体模块100操作时将由电源电势DC+,DC-的差值得出的电源电压施加在所述至少两个下部金属化层之间。
图9为此示出半导体模块100(出于简明的目的省去外部接口71,72,73)的示意性的俯视图,其中,第一下部金属化层321和第二下部金属化层322根据虚线示出。第一下部金属化层321具有第一基面尺寸A321,并且第二下部金属化层322具有第二基面尺寸A322。在本发明的意义中,最大面积视作金属化层的基面尺寸,所述最大面积可以具有其在平面上的垂直的投影(也就是说,如果对于所有可考虑的平面确定面积尺寸,面积尺寸具有金属化层在相应的平面上垂直的投影,那么金属化层的基面尺寸是所有这些面积尺寸中最大可能的面积尺寸)。
第一下部金属化层321的第一基面尺寸A321和第二下部金属化层322的第二基面尺寸A322这样选择,第一基面尺寸A321相对于第二基面尺寸A322的比例A321÷A322处于0.95至1/0.95(大约1.05)的范围内。第一特别是基面尺寸A321和第二基面尺寸A322也可以选择为相同的。所述标准不是仅仅适用于根据图2的半导体模块100或半导体模块装置100,200,而是所述标准可以应用到本发明的所有半导体模块100或半导体模块装置100,200上。
为了实现绝缘层4的底面4b和冷却体200之间良好的热接触,冷却体200可以直接与底面4b接触。在此,冷却体200可以直接材料配合地或材料齐平地接触。替换地,底面4b和冷却体200之间的热接触也可以构造为间接的接触,例如其方式是,构造为薄层的、置入底面4b和冷却体200之间的导热介质(未示出)连续地从冷却体200延伸直到底面4b。导热介质可以例如是导热膏或者是相态转换介质,所述相态转换介质在室温下是固体的或软膏状的并且其粘性由于其通过半导体模块100的操作所决定的加热而减小。
此外,半导体模块100具有壳体6。壳体6可以例如是塑料壳体例如热固塑料、热塑性塑料壳体、陶瓷壳体或金属壳体。在壳体6的内部中可以例如填充有介电的填料60、例如硅胶,所述填料从上部金属化层311,312和313延伸直到至少越过半导体开关1和2。在此,填料60完全地或者仅仅部分地填满壳体6的内部。在所述的设计方案中,壳体6的材料和填料60的材料可以是不同的材料。
非陶瓷的介电绝缘层4可以在将冷却体200安装在半导体模块100上之前已经是半导体模块100的构件,也就是说,绝缘层4的底面4b形成(还未安装在冷却体200上的)半导体模块100的外表面。绝缘层4例如可以被施加到具有绝缘载体区段301,302、上部金属化层311,312,313和下部金属化层321,322的电路载体装置上并且接着与所述电路载体装置一起以壳体6来设置。只要将填料60填充到壳体6中,则可以接着实现所述填充。
将已具有绝缘层4的半导体模块100安装在冷却体200上则可以在使用热传递介质、例如导热膏或相态转换介质(图中未示出)的情况下实现,所述热传递介质被置入底面4b和冷却体200之间,并且所述热传递介质连续地从底面4b延伸直到冷却体200。因为导热膏或相态转换介质又可以容易地去除,所以半导体模块100和冷却体200之间的连接可以构造为可拆卸、材料齐平的然而非材料配合的连接。被填充的或不可填充的聚合物(例如聚酰亚胺或环氧树脂)可以用作绝缘层4的材料。
替换地,将已具有绝缘层4的半导体模块100安装在冷却体200上也可以这样实现,即在绝缘层4和冷却体200之间存在材料配合的连接,例如其方式是,已形成半导体模块100的构件的绝缘层4直接被按压到充分加热冷却体200上,从而绝缘层4至少在其与冷却体200接触的底面4b上熔化,并且所述绝缘层在保持压力的情况下又被冷却直到所述绝缘层凝固并且与冷却体200材料配合地连接。在此,例如被填充的或不可填充的聚合物(例如聚酰亚胺或环氧树脂)适合作为绝缘层4的材料。
预制的塑料层(例如聚酰亚胺或环氧树脂层)同样可以用作绝缘层4,所述预制的塑料层不仅与冷却体200粘接而且与第一和第二下部金属化层321,322粘接。
底面4b和第一下部金属化层321之间或者底面4b和第二下部金属化层322之间的间距例如可以大于或等于20μm和/或小于或等于200μm。然而原则上也可以是较大或较小的值。
如同进一步在图2中所示的那样,绝缘层4也可以覆盖第一和第二下部金属化层321,322的窄面并且延伸直到第一和第二绝缘载体区段301,302。如同进一步在图3中所示的那样,绝缘层4也可以替换地构造为平面的层。此外,图2和3的半导体模块100或半导体模块装置100,200是相同的。
图5还示出一个设计方案的竖直剖面图,其中,壳体6通过以下方式制造,即与第一半导体开关1,2装配的电路载体装置利用塑胶注塑成型。在此,塑胶也形成绝缘层4。
注塑成型可以这样实现,即与第一半导体开关1,2装配的电路载体装置布置在注射成型模中并且利用成型材料注塑成型,从而首先产生具有注射成型的绝缘层4的半导体模块100。接着以所述方式预制的、具有绝缘层4的半导体模块100通过已述方法之一安装在冷却体200上。
注塑成型也可以替换地这样实现,即与第一半导体开关1,2装配的电路载体装置邻近于冷却体200布置,以使得在第一和第二下部金属化层321,322与冷却体200之间分别保留有一个间隙。在接着将已装配的电路载体装置注塑成型时,不仅制造壳体6,而且所述间隙被填充有塑胶。间隙宽度并且由此底面4b和第一下部金属化层321之间或者底面4b和第二下部金属化层322之间的间距例如可以大于或等于100μm和/或小于或等于500μm。然而原则上也可以是较大或较小的值。在注塑成型的所述变体中,形成绝缘层4的塑胶不仅与电路载体装置粘接,而且与冷却体200粘接,从而在绝缘层4的底面4b和冷却体200之间存在材料配合的连接。因此,半导体模块100则也与冷却体200材料配合地连接。
在图2,3和4所示的实例中,介电的第一绝缘载体区段301和介电的第二绝缘载体区段302是电绝缘的(例如陶瓷的)绝缘载体30的彼此隔开间距的区段。
以此相反,在根据图5,6和7的布置中,介电的第一绝缘载体区段301和介电的第二绝缘载体区段302分别是一个单独的电绝缘的(例如陶瓷的)绝缘载体。此外,根据图5,6和7的布置相应于根据图2,3和4的布置。根据图5,6和7的布置的建立能够以如同参考根据图2,3和4的对应的布置所述的那样地实现。
在根据图2至7所示的设计方案中,导电的连接元件51和52构造为第一绝缘载体区段301中或第二绝缘载体区段302中的通孔敷镀。如同在图8中所示的那样,第一导电连接51也构造为,所述第一电连接围绕第一绝缘载体区段301的侧向边缘,并且第一上部金属化层311与第一下部金属化层321持久地导电连接。替换地或附加地,第二导电连接52也构造为,所述第二导电连接围绕第二绝缘载体区段302的侧向边缘,并且第二上部金属化层312和所述第二下部金属化层322持久地导电连接。
利用本发明可以实现半导体模块100和冷却体200之间良好的热耦合,而在第一半导体开关1和绝缘层4的底面4b之间未布置有两个或更多个陶瓷层,并且在第二半导体开关2和绝缘层4的底面4b之间未布置有两个或更多个陶瓷层。
换言之,在第一半导体开关1和绝缘层4的底面4b之间可以不布置或者布置恰好一个(第一绝缘载体区段301)陶瓷层,并且在第二半导体开关2和绝缘层4的底面4b之间可以不布置或者布置恰好一个(第二绝缘载体区段302)陶瓷层。
绝缘层4的厚度可以选择为非常小的,从而所述绝缘层可以使半导体开关1,2向底面4b或者向冷却体200良好地散热。第一下部金属化层321和底面4b之间的间距和/或第二下部金属化层322和底面之间的间距例如可以是至少20μm或至少100μm。替换地或附加地,第一下部金属化层321和底面4b之间或者第二下部金属化层322和底面之间的间距例如可以小于或等于500μm或者小于或等于200μm。
在根据本发明的全部的设计方案中,绝缘层4可以这样设计或者说半导体模块100或半导体模块装置100,200这样被驱动,绝缘层4不软化或者根本不熔化。所述绝缘层可以例如构造为,即所述绝缘层在小于或等于80℃下始终具有至少20或者甚至至少50的肖氏-A硬度(根据DIN ISO 7619-1测量)。
Claims (19)
1.一种半导体模块,所述半导体模块具有:
第一半导体开关(1)和第二半导体开关(2),所述第一半导体开关和所述第二半导体开关中的每一个具有一个第一负载接口(11、21)和一个第二负载接口(12、22),在所述第一负载接口和所述第二负载接口之间形成负载线路,其中所述第一半导体开关(1)的负载线路和所述第二半导体开关(2)的负载线路电串联在第一电路节点(71’)和第二电路节点(72’)之间;
电路载体装置(3),所述电路载体装置具有:
介电的第一绝缘载体区段(301),所述介电的第一绝缘载体区段具有第一顶面(301t)以及与所述第一顶面对置的第一底面(301b);
介电的第二绝缘载体区段(302),所述介电的第二绝缘载体区段具有第二顶面(302t)以及与所述第二顶面对置的第二底面(302b);
第一上部金属化层(311),所述第一上部金属化层被施加到所述第一顶面(301t)上;
第二上部金属化层(312)和第三上部金属化层(313),所述第二上部金属化层和所述第三上部金属化层被施加到所述第二顶面(302t)上;
第一下部金属化层(321),所述第一下部金属化层被施加到所述第一底面(301b)上;
第二下部金属化层(322),所述第二下部金属化层被施加到所述第二底面(302b)上;以及
非陶瓷介电绝缘层(4),所述非陶瓷介电绝缘层被施加到所述第一下部金属化层(321)上并且被施加到所述第二下部金属化层(322)上,并且所述非陶瓷介电绝缘层具有背向所述第一下部金属化层(321)和所述第二下部金属化层(322)的底面(4b),所述底面形成所述半导体模块(100)的导热接触面。
2.根据权利要求1所述的半导体模块,其中,
所述第一半导体开关(1)的第一负载接口(11)与所述第一上部金属化层(311)持久地导电连接;以及
所述第二半导体开关(2)的第二负载接口(22)与所述第二上部金属化层(312)持久地导电连接。
3.根据权利要求1或2所述的半导体模块,其中,
所述第一上部金属化层(311)和所述第一下部金属化层(321)借助于第一导电连接(51)持久地导电连接,所述第一导电连接被构造为在所述第一绝缘载体区段(301)中的通孔敷镀,或者所述第一导电连接围绕所述第一绝缘载体区段(301)的侧向边缘;和/或
所述第二上部金属化层(312)和所述第二下部金属化层(322)借助于第二导电连接(52)持久地导电连接,所述第二导电连接被构造为所述第二绝缘载体区段(302)的通孔敷镀,或者所述第二导电连接围绕所述第二绝缘载体区段(302)的侧向边缘。
4.根据权利要求1或2所述的半导体模块,其中,
所述第一下部金属化层(321)具有第一基面尺寸(A321);
所述第二下部金属化层(322)具有第二基面尺寸(A322);并且
其中,所述第一基面尺寸(A321)与所述第二基面尺寸(A322)之间的比例处于0.95至1/0.95的范围内。
5.根据权利要求4所述的半导体模块,其中,第一基面尺寸(A321)等于所述第二基面尺寸(A322)。
6.根据权利要求1或2所述的半导体模块,其中,所述第一绝缘载体区段(301)和所述第二绝缘载体区段(302)由陶瓷构成。
7.根据权利要求1或2所述的半导体模块,其中,所述第一绝缘载体区段(301)和所述第二绝缘载体区段(302)是相连的陶瓷绝缘载体的区段。
8.根据权利要求1或2所述的半导体模块,其中,所述第一绝缘载体区段(301)和所述第二绝缘载体区段(302)被构造为彼此间隔开的单独的陶瓷绝缘载体。
9.根据权利要求1或2所述的半导体模块,其中,
在所述第一半导体开关(1)和所述非陶瓷介电绝缘层(4)的底面(4b)之间未布置或者仅布置恰好一个陶瓷层(301);和/或
在所述第二半导体开关(2)和所述非陶瓷介电绝缘层(4)的底面(4b)之间未布置或者仅布置恰好一个陶瓷层(302)。
10.根据权利要求1或2所述的半导体模块,其中,所述非陶瓷介电绝缘层(4)被构造为聚合物层。
11.根据权利要求1或2所述的半导体模块,其中,
所述非陶瓷介电绝缘层(4)的底面(4b)和所述第一下部金属化层(321)之间的间距是至少20μm;和/或
所述非陶瓷介电绝缘层(4)的底面(4b)和所述第二下部金属化层(322)之间的间距是至少20μm。
12.根据权利要求1或2所述的半导体模块,其中,
所述非陶瓷介电绝缘层(4)的底面(4b)和所述第一下部金属化层(321)之间的间距是至少100μm;和/或
所述非陶瓷介电绝缘层(4)的底面(4b)和所述第二下部金属化层(322)之间的间距是至少100μm。
13.根据权利要求1或2所述的半导体模块,其中,
所述非陶瓷介电绝缘层(4)的底面(4b)和所述第一下部金属化层(321)之间的间距小于或等于500μm;和/或
所述非陶瓷介电绝缘层(4)的底面(4b)和所述第二下部金属化层(322)之间的间距小于或等于500μm。
14.根据权利要求1或2所述的半导体模块,其中,
所述非陶瓷介电绝缘层(4)的底面(4b)和所述第一下部金属化层(321)之间的间距小于或等于200μm;和/或
所述非陶瓷介电绝缘层(4)的底面(4b)和所述第二下部金属化层(322)之间的间距小于或等于200μm。
15.根据权利要求1或2所述的半导体模块,其中,所述非陶瓷介电绝缘层(4)在小于或等于80℃的温度下总是具有至少20的肖氏-A硬度。
16.根据权利要求1或2所述的半导体模块,其中,所述非陶瓷介电绝缘层(4)在小于或等于80℃的温度下总是具有至少50的肖氏-A硬度。
17.根据权利要求1或2所述的半导体模块,其中,所述非陶瓷介电绝缘层(4)的底面(4b)是可自由接触的。
18.一种半导体模块装置,所述半导体模块装置具有:
根据前述权利要求中任一项构造的半导体模块(100);以及
冷却体(200),所述冷却体能拆卸地或者材料配合地与所述非陶瓷介电绝缘层(4)的底面(4b)连接。
19.一种用于操作半导体模块(100)的方法,其中所述方法具有:
提供根据权利要求1至17中任一项所述的半导体模块(100);
将第一电路节点(71’)连接到第一电源电势(DC+);
将第二电路节点(72’)连接到不同于所述第一电源电势(DC+)的第二电源电势(DC-)。
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