CN201898135U - 一种mosfet器件 - Google Patents

一种mosfet器件 Download PDF

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CN201898135U
CN201898135U CN2010202030615U CN201020203061U CN201898135U CN 201898135 U CN201898135 U CN 201898135U CN 2010202030615 U CN2010202030615 U CN 2010202030615U CN 201020203061 U CN201020203061 U CN 201020203061U CN 201898135 U CN201898135 U CN 201898135U
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吉扬永
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Abstract

本实用新型公开了一种MOSFET器件，涉及金属氧化物半导体场效应晶体管，目的在于提出一种高压横向MOSFET，提高性能，包括一半导体衬底；第一型掺杂阱，位于所述半导体衬底上；高浓度第一型掺杂的漏极接触区，位于所述第一型掺杂阱中；第二型掺杂阱，位于所述半导体衬底上；第二型基区，位于所述第二型掺杂阱中，掺杂深度比所述第二型掺杂阱浅；高浓度第一型掺杂的源极区，位于所述第二型基区中；栅极区，和所述第一型掺杂阱和第二型基区部分重叠；以及场氧区，位于栅极区和漏极接触区之间。其中，位于栅极区下方的第二型基区中的沟道呈水平结构。

Description

一种MOSFET器件
技术领域
本实用新型涉及金属氧化物半导体场效应晶体管(MOSFET)，具体涉及低阻高压N型MOSFET(NMOS)。
背景技术
对于采用BiCMOS或BCDMOS工艺制造的横向高压MOSFET，低导通电阻和高压是两个主要的设计因素。图1示出了一种传统的横向型高压NMOS。图2A、2B示出了制造过程中的两个工艺步骤用于描述传统高压N型MOSFET(NMOS)的结构特点。如图1所示，高压NMOS包含一P型衬底，在P型衬底上含一P阱和一N阱。NMOS进一步包含由氧化层11和多晶硅层12组成的栅极G，N+源极区S和N+漏极区。如图2A所示，在传统的工艺中，P阱由N阱氧化层20作阻挡层掺杂而成，同时横向扩散至N阱氧化层20下方。如图2B所示，当N阱氧化层20去除后，P阱上部呈现一个台阶。由于掩膜匹配误差的存在，栅极和P阱的重叠长度需要适当拉长以保证沟道长度，从而保证器件性能。这样，该台阶将位于NMOS的沟道之上，沟道在图1上即P阱与栅极重叠的虚线区域，这个台阶使得沟道呈弯曲状，将妨碍沟道中电子的流通，因此，导通电阻将增大。此外，拉长的NMOS的沟道也进一步增大导通电阻。
因此，需要提出一种新的工艺，消除高压MOSFET沟道中存在的台阶现象。
实用新型内容
本实用新型的目的在于提出一种高压横向MOSFET，该高压MOSFET采用体区双次掺杂方式，其中第二次掺杂以栅极自对准，并向栅极区扩散，该扩散部分形成MOSFET的沟道，消除了沟道中存在的台阶现象，提高了器件的性能。
具体来说，本实用新型的目的在于提出一种MOSFET器件，包括一半导体衬底；第一型掺杂阱，位于所述半导体衬底上；漏极接触区，位于所述第一型掺杂阱中，为高浓度的第一型掺杂；第二型掺杂阱，位于所述半导体衬底上；第二型基区，位于所述第二型掺杂阱中，掺杂深度比所述第二型掺杂阱浅；源极区，位于所述第二型基区中，为高浓度的第一型掺杂；栅极区，和所述第一型掺杂阱和第二型基区部分重叠；以及场氧区，位于栅极区和漏极接触区之间；其中，位于栅极区下方的第二型基区中的沟道呈水平结构。在一个实施例中，第一型为N型，第二型为P型。在另一个实施例中，第一型为P型，第二型为N型。
在一个实施例中，该MOSFET器件的半导体表面含有半导体半导体台阶，该台阶通常在制作体掺杂区时形成，该MOSFET器件的栅极区尺寸小，和半导体台阶不重叠。其中P型掺杂阱和N型掺杂阱接触。P型基区与所述P型掺杂阱边缘对齐，所述P型基区掺杂浓度高于所述P型掺杂阱。衬底为P型。N型掺杂阱包含至少两种层次的掺杂浓度。
N型掺杂包含采用磷、砷或锑之中的至少一种进行掺杂。P型掺杂包含采用硼、铝或镓之中的至少一种进行掺杂。
本实用新型的目的还在于提出一种横向MOSFET器件，包括栅极区；漏极区，位于栅极区第一侧；体区，位于栅极区第二侧，包含第一个层次的 掺杂区和第二个层次的掺杂区，其中第二个层次的掺杂区浓度比第一个掺杂区的浓度大，第二个掺杂区的深度比第一个掺杂区深度浅，第二个掺杂区靠近栅极区与栅极区重叠的部分构成LDMOS器件的沟道；源极区，位于体区；以及场氧区，位于栅极区和漏极接触区之间；其中，沟道呈水平结构。在一个实施例中，该MOSFET器件进一步包含半导体衬底，其中漏极区包含位于半导体衬底上的第一型掺杂阱和与所述第一型掺杂阱接触的高浓度第一型漏极接触区；体区为位于半导体衬底上的第二型掺杂区；源极区为与体区接触的高浓度第一型掺杂区。在一个实施例中其中第一个层次的掺杂区以第一型掺杂阱氧化物层自对准制作。在另一个实施例中，第一个层次的掺杂区通过光刻技术采用一掩膜制作。
一个实施例中，栅极区包含氧化物层和多晶硅层。
一个实施例中，所述氧化物层位于多晶硅层下面。
本实用新型采用上述结构的MOSFET器件，消除了半导体台阶带来的沟道弯曲结构，降低了导通电阻，提高了器件性能。
附图说明
图1示出了一个现有的高压NMOS的横截面结构。
图2A和图2B示出了形成现有技术中的高压NOMS沟道台阶的工艺步骤。
图3A和3B示出了本实用新型的一个含短沟道的高压MOSFET实施例的横截面示意图。
图4所示为本实用新型的另一个高压MOSFET实施例的横截面示意图。
具体实施方式
图3A示出了本实用新型的一个高压横向N型MOSFET(NMOS)30实施 例，其中高压NMOS 30的栅极区31与现有技术相比比较短，栅极区31和半导体台阶21不重叠，半导体台阶21位于栅极区31边沿外侧，使得沟道区域309为水平结构。如图3A所示，在图示的实施例中，高压NMOS 30包含衬底300、漏极区D、源极区S和栅极区G。图示的衬底300为P型掺杂。漏极区D和源极区S制作于P型衬底300上，分别位于栅极区G两侧。从P型衬底300的上表面，在漏极区D一侧制作有N阱301。在N阱301中含一高浓度的N+漏极接触区308，在另一个实施例中，N+漏极接触区308不完全位于N阱301中，但和N阱301直接接触。在一个实施例中，N阱301可包含至少两种浓度，例如，如图3B所示，N阱被分成在靠近栅极31的区域有一低浓度的N阱区310，在远离栅极31的区域有一浓度较高的N阱区312。
继续对图3A的描述，NMOS 30的源极区S位于体区(body)，其中体区包含第一个层次的掺杂区P阱302和第二个层次的掺杂区P型基区303，由两次掺杂形成，形成不同的浓度梯度。由于在制作N阱后制作N阱氧化层，所以在去除该N阱氧化层后形成半导体台阶21，该半导体台阶21位于栅极区31和源极区307之间的半导体表面。在衬底300上掺杂形成P阱302，它通过N阱氧化层自对准掺杂并向N阱301横向扩散，使P阱302与N阱301接触。“自对准”作为本领域的公知常识，通常指不通过光刻工艺中的掩膜而是通过半导体器件制作过程中产生的一结构作为阻挡层进行掺杂、刻蚀等步骤的工艺。高压NMOS 30包含栅极31，在N阱301和P阱302之上，该栅极31尺寸较小，不和台阶21重叠。在P阱302中进一步包含P型基区303，它以栅极31自对准进行P型掺杂并进行高温推进，使得P型基区303横向扩散至P阱302边缘。这样P型基区303的横向扩散区域， 即靠近栅极区31并与栅极区31重叠的部分构成NMOS 30的沟道309。在一个实施例中，P型基区303的浓度比P阱302浓度高，深度比P阱302浅。P阱302作为NMOS的基础体(body)区，P型基区303作为NMOS的主要体区。在P型基区303，制作有高浓度N+源极区307。在N阱表面有场氧区304，位于漏极接触区308和栅极区31之间，用于可靠隔离栅极31和漏极接触区308，提高耐压。在N阱301，制作有N+漏极接触区308。此外，图示的栅极31和P型基区303的横向扩散区域、N阱301和部分场氧区304重叠。栅极31包含氧化层305和导体层306，在一个典型的实施例中，导体层306为多晶硅层。其中在一个实施例中N+源极区307和N+漏极区308与栅极31及场氧304自对准实现。图3A中的从沟道309边缘到N+漏极区的N阱301(或3B中的N-阱310)构成漂移区，漂移区长度和杂质浓度影响器件的耐压(breakdown voltage)和导通电阻(Ron)。当漂移区越长，耐压和导通电阻越大，漂移区越短，耐压和导通电阻越低，同时漂移区的掺杂浓度越高，耐压和导通电阻越低，掺杂浓度越低，耐压和导通电阻越大。对于一固定的耐压，导通电阻越低越好，因此，耐压和导通电阻呈相互消长关系。
继续图3A的描述，由于该实施例中的体区采用了两次掺杂，包括P阱302和P型基区303，其中第二次掺杂303以栅极31自对准并横向控制扩散距离实现制作P型基区303，不需考虑掩膜匹配误差，因此栅极31尺寸可制造的很小，不延伸至台阶21之上，即栅极31不和台阶21重叠，沟道309变短且呈水平结构，导电微粒容易通过，导通电阻降低。为了消除短沟道带来的击穿电压降低的情况，高压NMOS 30包含一较高浓度的P基区303 作为主要体区。P基区303在栅极31形成后掺杂形成，并和栅极31自对准，掺杂后在一定温度下横向扩散。在一个实施例中，P基区303横向扩散至与P阱302边缘对齐。P基区303浓度比P阱302低，深度比302浅。沟道309由P基区303的横向扩散区域形成。由于P基区303深度较浅，单纯的P基区303至N阱301的耐压不够高，因此在高压器件领域，高压NMOS还需要进一步包括P阱302作为支持性的基础体区。P阱302上制作P基区303的结构使得高压NMOS在拥有较短沟道的同时具有高的耐压。
图4示出了为本实用新型的另一个高压NMOS 40实施例示意图。在这个实施例中，高压NMOS 40的半导体材料表面没有台阶，即高压NMOS 40的沟道409为水平的。在图示的实施例中，N阱401和P阱402采用双阱工艺制作，制作N阱401和制作P阱402各用一张掩膜，通过额外的掩膜和光刻工艺制作P阱402，消除N阱氧化步骤。在掺杂N阱和P阱之后，采用同一个高温推进过程进行扩散。这样，半导体材料表面的台阶被消除了，因此高压NMOS沟道409也呈水平结构。
该高压NMOS 40的其它部分结构与图3A和图3B中的NMOS 40和40B相似。即在一个实施例中，高压NMOS 40包含P衬底400，N阱401，P阱402，P阱402中的P基区403，由氧化层405和多晶硅层406组成的栅极41，N+源极区407，N+漏极接触区408和场氧404。P在制作栅极41之后，以栅极41自对准进行P型掺杂，形成P基区403，然后对P基区403进行高温推进使P基区403边缘与P阱402边缘对齐。P基区403的制作使得高压NMOS 40不需要考虑掩膜对准误差，从而沟道409较短。
本实用新型中的N型掺杂可采用磷、砷、锑之中的至少一种或其它N型 杂质进行掺杂，P型掺杂可采用硼、铝、镓之中的至少一种或其它P型杂质进行掺杂。在一些实施例中，采用上述结构和制作方法的高压NMOS可应用于100-200伏的场合。在其它的场合，采用上述结构和制作方法的高压NMOS也可应用于20-100伏特的场合。
本领域普通技术人员可显而易见的得知，本实用新型不仅可用于N型半导体器件，也可以用于P型半导体器件。在P型半导体器件中，N阱、P阱、P基区、N+漏极接触区和N+源极接触区的掺杂相反，即将N型器件中的P型变为N型，N型改变为P型。为便于描述，将N型半导体器件中的N型和P型半导体器件中的P型称为第一型，N型半导体器件中的P型和P型半导体器件中的N型称为第二型。例如将NMOS中的N阱称为第一型掺杂阱，NMOS中的P阱称为第二型掺杂阱；将PMOS中的P阱称为第一型掺杂阱，PMOS中的N阱称为第二型掺杂阱。

Claims (13)

1.一种MOSFET器件，其特征在于，包括：
一半导体衬底；
第一型掺杂阱，位于所述半导体衬底上；
漏极接触区，位于所述第一型掺杂阱中，为高浓度的第一型掺杂；
第二型掺杂阱，位于所述半导体衬底上；
第二型基区，位于所述第二型掺杂阱中，掺杂深度比所述第二型掺杂阱浅；
源极区，位于所述第二型基区中，为高浓度的第一型掺杂；
栅极区，和所述第一型掺杂阱和第二型基区部分重叠；
场氧区，位于栅极区和漏极接触区之间；
其中，位于栅极区下方的第二型基区中的沟道呈水平结构。
2.如权利要求1所述的MOSFET器件，其特征在于，第一型为N型，第二型为P型。
3.如权利要求2所述的MOSFET器件，其特征在于，包含半导体表面上位于栅极区和源极区之间的半导体台阶，所述半导体台阶位于所述栅极区边沿外侧。
4.如权利要求3所述的MOSFET器件，其特征在于，P型掺杂阱和N型掺杂阱接触。
5.如权利要求4所述的MOSFET器件，其特征在于，所述P型基区与所述P型掺杂阱边缘对齐，所述P型基区掺杂浓度高于所述P型掺杂阱。
6.如权利要求5所述的MOSFET器件，其特征在于，所述栅极区位于所述P型掺杂阱的扩散区和部分N型掺杂阱上面。
7.如权利要求2所述的MOSFET器件，其特征在于，所述衬底为P型。
8.如权利要求1所述的MOSFET器件，其特征在于，所述栅极区包含一氧化物层和一多晶硅层。
9.一种横向MOSFET器件，其特征在于，包括
栅极区；
漏极区，位于栅极区第一侧；
体区，位于栅极区第二侧，包含第一个层次的掺杂区和第二个层次的掺杂区，其中第二个层次的掺杂区浓度比第一个掺杂区的浓度大，第二个掺杂区的深度比第一个掺杂区深度浅，第二个掺杂区靠近栅极区与栅极区重叠的部分构成LDMOS器件的沟道；
以及源极区，位于体区；
场氧区，位于栅极区和漏极区之间；
其中，所述沟道呈水平结构。
10.如权利要求9所述的MOSFET器件，其特征在于，栅极区包含氧化物层和多晶硅层。
11.如权利要求10所述的MOSFET器件，其特征在于，所述氧化物层位于多晶硅层下面。
12.如权利要求10所述的MOSFET器件，其特征在于，进一步包含半导体衬底，其中漏极区包含位于半导体衬底上的第一型掺杂阱和与所述第一型掺杂阱接触的高浓度第一型漏极接触区；体区为位于半导体衬底上的第二型掺杂区；源极区为与体区接触的高浓度第一型掺杂区。
13.如权利要求12所述的MOSFET器件，其特征在于，在栅极区和源极区之间的半导体表面包含半导体台阶。
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