CN104659103B - N型ldmos器件及工艺方法 - Google Patents

N型ldmos器件及工艺方法 Download PDF

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CN104659103B
CN104659103B CN201510080729.9A CN201510080729A CN104659103B CN 104659103 B CN104659103 B CN 104659103B CN 201510080729 A CN201510080729 A CN 201510080729A CN 104659103 B CN104659103 B CN 104659103B
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ldmos device
drain region
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traps
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CN104659103A (zh
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石晶
钱文生
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors

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Abstract

本发明公开了一种N型LDMOS器件，在P型衬底上的N型深阱中具有P阱及N阱，硅表面具有多晶硅栅极及侧墙结构。所述N阱中具有LDMOS器件的漏区，漏区上有金属电极将漏区引出；所述P阱中具有LDMOS器件的源区，以及重掺杂P型区，金属电极将重掺杂P型区及源区引出。所述LDMOS器件的表面为非平面的有台阶结构，漏区的位置高于LDMOS的沟道。本发明还公开了所述N型LDMOS器件的工艺方法。

Description

N型LDMOS器件及工艺方法
技术领域
本发明涉及半导体领域，特别是指一种N型LDMOS器件，本发明还涉及所述N型LDMOS器件的工艺方法。
背景技术
DMOS由于具有耐高压，大电流驱动能力和极低功耗等特点，目前在电源管理电路中被广泛采用。在BCD工艺中，DMOS虽然与CMOS集成在同一块芯片中，但由于高耐压和低导通电阻的要求，DMOS在本底区和漂移区的条件与CMOS现有的工艺条件共享的前提下，其导通电阻与击穿电压存在矛盾，往往无法满足开关管应用的要求。在LDMOS器件中，导通电阻是一个重要的指标。因此，为了制作高性能的LDMOS，需要采用各种方法优化器件的导通电阻及击穿电压。
目前常规的LDMOS的结构如图1所示，图中包含P型衬底101，N型深阱102，P阱103，N阱104，多晶硅栅极106，多晶硅栅极106两端还具有侧墙107。这种结构在漏端具有较高的电场强度，不利于击穿电压BV的提高。
发明内容
本发明所要解决的技术问题是提供一种N型LDMOS器件，使漏端电势分布均匀，提高器件的击穿电压BV。
本发明所要解决的另一技术问题是提供所述N型LDMOS器件的工艺方法。
为解决上述问题，本发明所述的N型LDMOS器件，在P型衬底上的N型深阱中具有P阱及N阱，衬底表面具有多晶硅栅极及侧墙结构；所述N阱中具有LDMOS器件的漏区，漏区上有金属电极将漏区引出；所述P阱中具有LDMOS器件的源区，以及重掺杂P型区，金属电极将重掺杂P型区及源区引出；所述LDMOS器件的表面为非平面的有台阶结构，漏区的位置高于LDMOS的沟道。
为解决上述问题，本发明所述的N型LDMOS器件的工艺方法，包含如下工艺步骤：
第1步，在P型硅衬底通过光刻掩膜形成局部场氧化(LOCOS)；
第2步，湿法腐蚀去掉局部场氧化，再进行N型深阱的注入；
第3步，通过光刻定义打开P阱和N阱的窗口，注入形成P阱和N阱；
第4步，生长栅氧化层及淀积多晶硅，刻蚀形成多晶硅栅极；
第5步，淀积氧化硅层，干法刻蚀形成多晶硅栅极的侧墙；
第6步，进行源区及漏区的离子注入，以及重掺杂P型区的离子注入；
第7步，形成金属电极，将源漏区分别引出。
所述第5步，淀积的氧化硅层厚度为
本发明所述的N型LDMOS器件，通过提高漏区位置，使漏区高于沟道，使得电场分布更加均匀，改善了漂移区的电势分布，降低电场强度，提高了器件的击穿电压。本发明所采用的工艺可集成在BCD工艺中，利用平台中原有的工艺条件，不额外增加光刻版并且利用原有注入条件，工艺简单易于实施。
附图说明
图1是传统N型LDMOS器件的结构示意图。
图2～8是本发明工艺步骤示意图。
图9～12是本发明与传统器件的仿真对比图。
图13是本发明工艺步骤流程图。
附图标记说明
101是P型衬底，102是N型深阱，103是P阱，104是N阱，105是栅氧化层，106是多晶硅栅极，107是栅极侧墙，108是源区，109是重掺杂P型区，110是金属电极,111是漏区,h是高度。
具体实施方式
本发明所述的N型LDMOS器件，如图8所示，在P型衬底上101的N型深阱102中具有P阱103及N阱104，衬底表面具有多晶硅栅极106及侧墙结构107；所述N阱104中具有LDMOS器件的漏区111，漏区111上有金属电极110将漏区111引出；所述P阱103中具有LDMOS器件的源区108，以及重掺杂P型区109，金属电极将重掺杂P型区109及源区108引出；所述LDMOS器件的表面为非平面的有台阶结构，漏区的位置高于LDMOS的沟道，两边的高度差h为
为解决上述问题，本发明所述的N型LDMOS器件的工艺方法，包含如下工艺步骤：
第1步，在P型硅衬底101通过光刻掩膜形成厚度为的LOCOS，如图2所示。
第2步，湿法腐蚀去掉LOCOS，硅片表面形成台阶，右边高于左边，再进行N型深阱102的注入，如图3所示。
第3步，通过光刻定义打开P阱和N阱的窗口，注入形成P阱103和N阱104，如图4所示。
第4步，生长栅氧化层105及淀积多晶硅，刻蚀形成多晶硅栅极106，如图5所示。
第5步，淀积厚度为的氧化硅层，干法刻蚀形成多晶硅栅极的侧墙107，如图6所示。
第6步，进行源区108及漏区111的离子注入，以及重掺杂P型区108的离子注入，如图7所示。
第7步，形成金属电极110，将源漏区分别引出，如图8所示。
以上工艺如源区及漏区的注入条件，都与BCD平台中的CMOS工艺共用，P型沟道区由CMOS工艺中的P阱构成，N型漂移区由CMOS工艺中的N型深阱构成，P型衬底引出端和N型源区及漏区的注入掺杂与常规N型LDMOS一致。
图9及图10所示为本发明与传统技术的电场分布仿真示意图，图11及图12是本发明与传统技术的电势分布的仿真示意图，对于电场分布，本发明在经过最高点后，下降的趋势缓于基本线，电场分布更加均匀，对于电势示意图，在更深处的电势高于基本线，表示器件的击穿电压有提高。
以上仅为本发明的优选实施例，并不用于限定本发明。对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (2)

1.一种N型LDMOS器件，在P型衬底上的N型深阱中具有P阱及N阱，衬底表面具有多晶硅栅极及侧墙结构；所述N阱中具有LDMOS器件的漏区，漏区上有金属电极将漏区引出；所述P阱中具有LDMOS器件的源区，以及重掺杂P型区，金属电极将重掺杂P型区及源区引出；其特征在于：所述LDMOS器件的表面为非平面的有台阶结构，漏区的位置高于LDMOS的沟道。
2.如权利要求1所述的N型LDMOS器件，其特征在于：所述漏区与沟道的高度差为1000～4000Å。
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CN111540785A (zh) * 2020-05-13 2020-08-14 上海华虹宏力半导体制造有限公司 Ldmos器件及其制造方法

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US6838731B1 (en) * 2003-04-09 2005-01-04 Sirenza Microdevices, Inc. Microwave transistor structure having step drain region
CN1734786A (zh) * 2004-08-11 2006-02-15 台湾积体电路制造股份有限公司 晶体管及其形成方法
CN101901835A (zh) * 2009-05-28 2010-12-01 成都芯源系统有限公司 一种低阻高压mosfet器件及其制造方法

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