CN104037225A - 具有延伸的栅极介电层的金属氧化物半导体场效应晶体管 - Google Patents
具有延伸的栅极介电层的金属氧化物半导体场效应晶体管 Download PDFInfo
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Abstract
本发明提供了一种金属氧化物半导体场效应晶体管(MOSFET),包括:衬底、衬底中的源极和漏极、在源极和漏极之间设置在衬底上方的栅电极以及设置在衬底和栅电极之间的栅极介电层。至少一部分的栅极介电层朝向源极和漏极中的至少一个延伸超过栅电极。本发明还提供了具有延伸的栅极介电层的金属氧化物半导体场效应晶体管。
Description
技术领域
本发明一般地涉及集成电路,更具体地,涉及金属氧化物半导体场效应晶体管(MOSFET)。
背景技术
一些MOSFET被设计为维持高工作电压。具有更宽范围Vbd(称作“拖尾”)的一些MOSFET的栅极介电层击穿电压(Vbd)具有可靠性问题。例如,具有多指结构的高电压(HV)MOSFET器件通常具有这种Vbd拖尾。先前设计的增加Vbd的一些器件会导致较大的器件间距、变大的阈值电压Vt或角部处的栅极氧化物薄化,从而导致不稳定或不希望的器件性能。
发明内容
为了解决现有技术中所存在的缺陷,根据本发明的一方面,提供了一种金属氧化物半导体场效应晶体管(MOSFET),包括:衬底;源极,位于所述衬底中;漏极,位于所述衬底中;栅电极,在所述源极和所述漏极之间设置在所述衬底上方;以及栅极介电层,设置在所述衬底和所述栅电极之间,其中,至少部分所述栅极介电层朝向所述源极和所述漏极中的至少一个延伸超过所述栅电极。
在该MOSFET中,所述栅极介电层延伸超过所述栅电极的长度至少为所述栅极介电层的厚度的0.5倍。
在该MOSFET中,所述栅极介电层延伸超过所述栅电极的长度在0.03μm至0.3μm的范围内。
在该MOSFET中,所述栅极介电层包括二氧化硅。
在该MOSFET中,所述栅电极包括多晶硅或金属。
该MOSFET进一步包括:邻近所述栅电极设置在所述衬底中的轻掺杂区。
该MOSFET进一步包括:邻近所述栅电极并且至少部分地位于所述栅极介电层上方的间隔件。
在该MOSFET中,所述间隔件包括氮化硅或二氧化硅。
在该MOSFET中,所述栅极介电层的朝向所述漏极的部分比朝向所述源极的部分厚。
根据本发明的另一方面,提供了一种制造金属氧化物半导体场效应晶体管(MOSFET)的方法,包括:在衬底上方形成栅极介电层;在所述栅极介电层上方形成栅电极,至少一部分所述栅极介电层没有被所述栅电极所覆盖;以及在所述衬底中形成源极和漏极,所述栅极介电层朝向所述源极和所述漏极中的至少一个延伸超过所述栅电极。
在该方法中,所述栅极介电层延伸超过所述栅电极的长度至少为所述栅极介电层的厚度的0.5倍。
在该方法中,所述栅极介电层延伸超过所述栅电极的长度在0.03μm至0.3μm的范围内。
在该方法中,所述栅极介电层包括二氧化硅。
在该方法中,所述栅电极包括多晶硅或金属。
该方法进一步包括:形成邻近所述栅电极设置在所述衬底中的至少一个轻掺杂区。
该方法进一步包括:形成邻近所述栅电极并且至少部分地位于所述栅极介电层上方的间隔件。
在该方法中,所述间隔件包括氮化硅或二氧化硅。
在该方法中,所述栅极介电层的朝向所述漏极的部分比朝向所述源极的部分厚。
根据本发明的又一方面,提供了一种金属氧化物半导体场效应晶体管(MOSFET),包括:衬底;源极,位于所述衬底中;漏极,位于所述衬底中;栅电极,在所述源极和所述漏极之间设置在所述衬底上方;栅极介电层,设置在所述衬底和所述栅电极之间;以及间隔件,被形成为邻近所述栅电极并且至少部分地在所述栅极介电层上方;其中,所述栅极介电层的至少一部分朝向所述源极和所述漏极中的至少一个延伸超过所述栅电极的长度至少为所述栅极介电层的厚度的0.5倍。
在该MOSFET中,所述栅极介电层延伸超过所述栅电极的长度在0.03μm至0.3μm的范围内。
附图说明
现在,将结合附图所进行的以下描述作为参考,其中:
图1是根据一些实施例的示例性MOSFET的原理图;
图2是根据一些实施例的另一个示例性MOSFET的原理图;
图3是根据一些实施例的图1中示例性MOSFET与其他MOSFET相比较的Vbd曲线图;
图4A至图4E是根据一些实施例的图1中的MOSFET的示例性制造方法的中间步骤;以及
图5A至图5E是根据一些实施例的图1中MOSFET的另一个示例性制造方法的中间步骤。
具体实施方式
以下详细讨论各种实施例的制造和使用。然而,应该理解,本发明提供了许多可以在各种具体环境中实现的可应用的创造性概念。所讨论的具体实施例仅仅说明制造和使用的具体方式,并且没有限定本发明的范围。
此外,本发明可在各个示例中重复参照数字和/或字母。该重复是为了简明和清楚,而且其本身没有规定所述各种实施例和/或结构之间的关系。而且,本发明中一个部件形成在另一个部件上、一个部件与另一个部件的连接和/或一个部件与另一个部件耦合包括其中以直接接触的方式形成部件的实施例,并且也可以包括其中附加部件形成在部件之间,使得部件不直接接触的实施例。另外,空间相对位置的术语,例如“下部”、“上部”、“水平”、“垂直”、“在…之上”、“在…上方”、“在…之下”、“在…下方”、“向上”、“向下”、“顶部”、“底部”等及其派生词(例如,“水平地”、“向下地”、“向上地”等)是用于简化本发明中一个部件和另一个部件的关系。这些空间相对术语旨在覆盖具有这些部件的器件的不同定向。
图1是根据一些实施例的示例性MOSFET的原理图。MOSFET100包括衬底102、栅极介电层104、源极/漏极110、轻掺杂区108、栅电极106以及间隔件112。
衬底102提供支撑并用作制造集成电路器件的基础。衬底102包括硅、二氧化硅、氧化铝、蓝宝石、锗、砷化镓(GaAs)、硅和锗合金、磷化铟(InP)、绝缘体上硅或任何其他合适的材料。
栅极介电层104包括二氧化硅或任何其他合适的介电材料。在一些高电压应用的实施例中,栅极介电层104在漏极侧上比在源极侧上更厚。在一些实施例中,栅极介电层104的厚度为
栅极介电层104朝向源极或漏极110中的至少一个延伸超过栅电极106。如图3所示,延伸的栅极介电层104能够减少Vbd拖尾问题。在一些实施例中,栅极介电层104延伸超过栅电极106边缘至少栅极介电层104的厚度的1/2。
在一个示例中,栅极介电层104从栅电极106边缘延伸的长度等于栅极介电层104的厚度。在一些实施例中,栅极介电层104从栅电极106边缘延伸0.03μm至0.3μm。
栅电极106包括多晶硅、金属或任何其他合适的材料。邻近栅电极106的轻掺杂区108用于避免短沟道效应。邻近栅电极106将轻掺杂区108设置在衬底102中的源极/漏极110侧。例如,轻掺杂区108通过离子注入掺杂有诸如磷或硼的N型或P型掺杂剂。虽然在图1中示出了位于一侧(例如,源极侧)的轻掺杂区108,但是如图2所示,轻掺杂区108也可能位于源极侧和漏极侧上。
当栅极介电层104延伸超过栅电极106时,邻近栅电极106形成间隔件112并且间隔件112至少部分地形成在栅极介电层104上方。间隔件112包括氮化硅、二氧化硅或任何其他合适的材料。在一些实施例中,间隔件112可以用于限定源极/漏极110并用作自对准形成的掩模。例如,源极/漏极110通过离子注入掺杂有诸如磷或硼的N型或P型掺杂剂。
图2是根据一些实施例的另一个示例性MOSFET200的原理图。MOSFET200类似于图1中的MOSFET100,栅极介电层104朝向源极和漏极110延伸超过栅电极106。在其他实施例中,栅电极106朝向源极侧和漏极侧中的一个延伸。在一个示例中,栅电极106朝向漏极侧延伸。与图1中MOSFET100相比,栅极介电层104具有均匀的厚度。在源极侧和漏极侧中都形成轻掺杂区108。
例如,可以在各种MOSFET结构中实现延伸的栅极介电层104,诸如图2所示的对称MOSFET、非对称MOSFET、横向扩散金属氧化物半导体(LDMOS)晶体管或任何其他MOSFET。
具有延伸的栅极介电层104的一些MOSFET可以用于高压应用中,其中,栅极电压Vg在6.75V至40V的范围内并且漏源电压在6.75V至250V的范围内。
图3是根据一些实施例的图1中的示例性MOSFET与其他MOSFET相比较的Vbd曲线图。与其他MOSFET的线304相比较,特别在区域306中,如图1和图2所示的具有延伸的栅极介电层104的MOSFET的线302没有Vbd拖尾问题(在较宽电压值范围上散布的Vbd)。
图4A至图4E是根据一些实施例的图1中MOSFET的示例性制造方法的中间步骤。
在图4A中,在衬底102上方形成栅极介电层104a和栅电极106。栅极介电层104a包括二氧化硅或任何其他合适的材料而栅电极106包括多晶硅、金属或任何其他合适的材料。
在一个示例中,在衬底102上生长栅极介电层104a的二氧化硅(氧化物)层并且在二氧化硅上方沉积栅电极106的多晶硅层并图案化该多晶硅层以形成栅电极106。
在一些实施例中,特别是对于一些高电应用,栅极介电层104a在漏极侧上比在源极侧上厚。例如,可以在晶圆上生长厚度为(即,期望的源极侧和漏极侧栅极介电层的厚度差)的氧化物层,并且可以通过使用掩模蚀刻位于源极侧上的氧化物层。然后,可以在晶圆上再次生长厚度为(即,期望的源极侧厚度)的附加氧化物层以形成在源极侧和漏极侧上具有不同厚度的栅极氧化物层。在其他实施例中,栅极介电层104a的厚度可以是均匀的。在一些实施例中,栅极介电层104的厚度为至
在图4B中,在一些实施例中,使用栅电极106作为掩模通过离子注入来形成轻掺杂区108,使得轻掺杂区108与栅电极106的边缘自对准。在一些实施例中,在离子注入步骤中,采用光掩模或硬掩模(未示出)以保护漏极区,使得仅源极区具有轻掺杂区。在其他实施例中,在源极侧和漏极侧中都形成轻掺杂区。
在图4C中,例如,通过化学汽相沉积和蚀刻来形成间隔件112。间隔件112包括氮化硅、二氧化硅或任何其他合适的材料。
在图4D中,在一些实施例中,使用间隔件112作为掩模通过(高电压)蚀刻工艺来蚀刻图4C中的栅极介电层104a,使得生成的栅极介电层104与间隔件112的边缘自对准。间隔件112至少部分地位于延伸的栅极介电层104上方。
在图4E中,在一些实施例中,使用栅电极106和间隔件112作为掩模通过离子注入形成源极/漏极110,使得源极/漏极110与间隔件112的边缘自对准。栅极介电层104朝向源极和漏极110的至少一个延伸超过栅电极106。在一个示例中,栅极介电层104朝向漏极110延伸。在另一个示例中,栅极介电层104朝向源极和漏极110两侧延伸。延伸的栅极介电层104可以减小如图3所述的Vbd拖尾问题。
在一些实施例中,栅极介电层104从栅电极106边缘延伸至少1/2的栅极介电层104的厚度。在一个示例中,栅极介电层104从栅电极106边缘延伸的长度等于栅极介电层104的厚度。在一些实施例中,栅极介电层104从栅电极106边缘延伸0.03μm至0.3μm。
图5A至图5E是根据一些实施例的图1中的示例性MOSFET的另一个示例性制造方法的中间步骤。
在图5A中,在衬底102上方形成栅极介电层104a和栅电极106。栅极介电层104a包括二氧化硅或任何其他合适的材料而栅电极106包括多晶硅、金属或任何其他合适的材料。
在一个示例中,在衬底102上生长栅极介电层104a的二氧化硅(氧化物)层并且在二氧化硅上方沉积栅电极106的多晶硅层并将该多晶硅图案化以形成栅电极106。
在一些实施例中,尤其是对于一些高电压应用,栅极介电层104a在漏极侧上比在源极侧上厚。例如,可以在晶圆上生长厚度为(即,期望的源极侧和漏极侧栅极介电层的厚度差)的氧化物层,并且可以通过使用掩模蚀刻掉源极侧上的氧化物层。然后,可以在晶圆上再次生长厚度为(即,期望的源极侧厚度)的附加氧化物层以在源极侧和漏极侧上形成具有不同厚度的栅极氧化物层。在其他实施例中,栅极介电层104a的厚度可以是均匀的。在一些实施例中,栅极介电层104的厚度为至
在图5B中,在一些实施例中,使用与延伸超过栅电极106期望长度的栅极介电层104a的边缘对准的掩模105,通过(高电压)蚀刻工艺蚀刻栅极介电层104a。
在图5C中,在一些实施例中,使用栅电极106和栅极介电层104a的较厚一侧作为掩模,通过离子注入形成轻掺杂区108。
在图5D中,例如,通过化学汽相沉积和蚀刻形成间隔件112。间隔件112包括氮化硅、二氧化硅或任何其他合适的材料。间隔件112至少部分地形成在延伸的栅极介电层104上方。
在图5E中,在一些实施例中,使用栅电极106和间隔件112作为掩模通过离子注入形成源极/漏极110,使得源极/漏极110与间隔件112的边缘自对准。栅极介电层104朝向源极和漏极110至少一个延伸超过栅电极106。在一个示例中,栅极介电层104朝向漏极110延伸。在另一个示例中,栅极介电层104朝向源极和漏极110两侧都延伸。延伸的栅极介电层104能够减小如图3所述的Vbd拖尾问题。
在一些实施例中,栅极介电层104从栅电极106边缘延伸至少1/2的栅极介电层104的厚度。在一个示例中,栅极介电层104从栅电极106边缘延伸的长度等于栅极介电层104的厚度。在一些实施例中,栅极介电层104从栅电极106边缘延伸0.03μm至0.3μm。
根据一些实施例,金属氧化物半导体场效应晶体管(MOSFET)包括衬底、衬底中的源极和漏极、在源极和漏极之间设置在衬底上方的栅电极,以及设置在衬底和栅电极之间的栅极介电层。至少一部分的栅极介电层朝向源极和漏极中的至少一个方向上延伸超过栅电极。
根据一些实施例,制造金属氧化物半导体场效应晶体管(MOSFET)的方法包括在衬底上方形成栅极介电层。在栅极介电层上方形成栅电极。至少一部分的栅极介电层未被栅电极覆盖。在衬底中形成源极和漏极。栅极介电层朝向源极和漏极中的至少一个上延伸超过栅电极。
本领域的技术人员应该意识到,可能存在本发明实施例的多个变型例。尽管已经详细地描述了本实施例及其部件,但应该理解,可以在不背离实施例的主旨和范围的情况下,做各种不同的改变、替换和更改。而且,本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解,通过本发明,现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造、材料组分、装置、方法或步骤根据本发明可以被使用。
以上方法示出了示例性步骤,但是不需要一定按照所示顺序实施。在本发明的实施例的精神和范围内,可以适当地增加、替换、改变顺序和/或删除步骤。结合不同权利要求和/或不同实施例的实施例在本发明的范围之内,这对阅读了本发明之后的本领域的技术人员来说是显而易见的。
Claims (10)
1.一种金属氧化物半导体场效应晶体管(MOSFET),包括:
衬底;
源极,位于所述衬底中;
漏极,位于所述衬底中;
栅电极,在所述源极和所述漏极之间设置在所述衬底上方;以及
栅极介电层,设置在所述衬底和所述栅电极之间,
其中,至少部分所述栅极介电层朝向所述源极和所述漏极中的至少一个延伸超过所述栅电极。
2.根据权利要求1所述的MOSFET,其中,所述栅极介电层延伸超过所述栅电极的长度至少为所述栅极介电层的厚度的0.5倍。
3.根据权利要求1所述的MOSFET,其中,所述栅极介电层延伸超过所述栅电极的长度在0.03μm至0.3μm的范围内。
4.根据权利要求1所述的MOSFET,其中,所述栅极介电层包括二氧化硅。
5.根据权利要求1所述的MOSFET,其中,所述栅电极包括多晶硅或金属。
6.根据权利要求1所述的MOSFET,进一步包括:邻近所述栅电极设置在所述衬底中的轻掺杂区。
7.根据权利要求1所述的MOSFET,进一步包括:邻近所述栅电极并且至少部分地位于所述栅极介电层上方的间隔件。
8.根据权利要求7所述的MOSFET,其中,所述间隔件包括氮化硅或二氧化硅。
9.一种制造金属氧化物半导体场效应晶体管(MOSFET)的方法,包括:
在衬底上方形成栅极介电层;
在所述栅极介电层上方形成栅电极,至少一部分所述栅极介电层没有被所述栅电极所覆盖;以及
在所述衬底中形成源极和漏极,所述栅极介电层朝向所述源极和所述漏极中的至少一个延伸超过所述栅电极。
10.一种金属氧化物半导体场效应晶体管(MOSFET),包括:
衬底;
源极,位于所述衬底中;
漏极,位于所述衬底中;
栅电极,在所述源极和所述漏极之间设置在所述衬底上方;
栅极介电层,设置在所述衬底和所述栅电极之间;以及
间隔件,被形成为邻近所述栅电极并且至少部分地在所述栅极介电层上方;
其中,所述栅极介电层的至少一部分朝向所述源极和所述漏极中的至少一个延伸超过所述栅电极的长度至少为所述栅极介电层的厚度的0.5倍。
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CN104037225B (zh) | 2019-03-08 |
US20140252499A1 (en) | 2014-09-11 |
US20160079368A1 (en) | 2016-03-17 |
KR20150114928A (ko) | 2015-10-13 |
KR101637852B1 (ko) | 2016-07-07 |
US9209298B2 (en) | 2015-12-08 |
KR20140111216A (ko) | 2014-09-18 |
US9997601B2 (en) | 2018-06-12 |
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