CN104157690B - 一种带槽型结构的应变nldmos器件及其制作方法 - Google Patents

一种带槽型结构的应变nldmos器件及其制作方法 Download PDF

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CN104157690B
CN104157690B CN201410401006.XA CN201410401006A CN104157690B CN 104157690 B CN104157690 B CN 104157690B CN 201410401006 A CN201410401006 A CN 201410401006A CN 104157690 B CN104157690 B CN 104157690B
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王向展
邹淅
黄建国
赵迪
张易
曾庆平
于奇
刘洋
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University of Electronic Science and Technology of China
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Abstract

本发明提供了一种带槽型结构的应变NLDMOS器件及其制作方法，属于半导体技术领域。技术方案为：带槽型结构的应变NLDMOS器件，包括半导体衬底、沟道掺杂区、漂移区、源重掺杂区、漏重掺杂区、栅氧、场氧、栅，还包括设置在漂移区的沿源漏方向的P型掺杂的槽型结构，所述槽型结构向漂移区宽度方向引入压应力、长度方向引入张应力。引入应力的方法为：向槽型结构区域淀积无定型材料，通过退火使无定型材料变成多晶材料过程中体积的膨胀引入应力，或者向槽型结构区域进行氧离子注入，退火使氧离子与硅反应生成二氧化硅，通过硅氧化过程中体积的膨胀引入应力。本发明器件在保证击穿电压的同时降低了漂移区的电阻，提升了器件的性能。

Description

一种带槽型结构的应变NLDMOS器件及其制作方法
技术领域
本发明涉及半导体技术，特别涉及一种N型横向扩散金属氧化物半导体场效应晶体管(NLDMOS)及其制作方法。
背景技术
无线通信系统、功率开关模块及其相关技术的飞速发展推动着功率集成电路的迅速发展，随着工作频率越来越高，其对电路及器件频率的要求越来越高。一方面，无线通信系统需要扩展信号的带宽，从而需要器件具有高的工作频率；另一方面，高的击穿电压需要长的漂移区和低的漂移区掺杂，这与降低漂移区电阻、提高频率和效率相矛盾。因此，在提高器件击穿电压的同时，降低漂移区电阻，提高其频率特性、输出效率、线性区特性等成为业界关注的焦点。
在射频功率器件中，LDMOS(横向扩散金属氧化物半导体场效应晶体管)器件凭借其良好的工艺兼容性和优良的性能，在射频功率器件中发挥着重要的作用。提高LDMOS击穿电压，降低漂移区电阻的方法主要有沟道工程和漂移区工程。沟道工程即通过对器件沟道长度的缩短、沟道的改进提高沟道载流子迁移率，进而提高器件的跨导和驱动能力，减小栅电容，从而提高器件频率。其中，提高沟道载流子迁移率的方法主要为改变沟道材料和向沟道中引入应力。漂移区工程主要是对漂移区结构和掺杂的改进以使漂移区全耗尽，漂移区电场分布更均匀以提高击穿，同时降低漂移区电阻以提高器件饱和特性，提高频率特性和输出效率等，主要有场板技术，卢瑟福技术和漂移区超晶结技术等。
向N型半导体材料中延载流子输运方向引入单轴张应力或在输运平面内引入双轴张应力可有效提升其电子迁移率，减小电阻。向P型半导体材料延载流子输运方向引入单轴压应力可有效提升其空穴迁移率，在载流子输运平面内的双轴张应力也可提升空穴迁移率，但效果相对较小。对于LDMOS，沟道应力主要通过氮化硅盖帽和锗硅虚拟衬底方式引入。然而锗硅虚拟衬底方式通常采用全局锗硅虚拟衬底方式，因为弛豫锗硅层上难以生长厚的应变硅层，而禁带宽度较窄的锗硅层在漂移区时其临界击穿电场较低，从而会导致漂移区可承受耐压降低，导致LDMOS击穿电压降低；而仅在沟道下方采用局部虚拟衬底技术则制作工艺复杂，成本较高。
现有的采用氮化硅盖帽向沟道中引入应力的LDMOS器件的结构如图1所示，包括半导体衬底1，沟道掺杂区2，漂移区3，源重掺杂区4，漏重掺杂区5，栅氧6，场氧7，栅8，应变氮化硅盖帽9。当整个器件只覆盖一种氮化硅薄膜时，对于小尺寸器件和栅厚度较大的大尺寸器件，可通过氮化硅的收缩使得沟道两侧衬底硅的收缩从而向沟道区引入张应力，但这种方式将会向漂移区中引入压应力；而对于栅厚度较小的大尺寸器件，沟道中心应力还受栅正上方氮化硅传下来的应力的影响，而栅向沟道传递的应力与源区和漂移区向沟道传递的应力类型相反，导致沟道应力减小，器件性能的提升受限。
对于传统MOS器件，由于源漏区高掺杂，自身电阻很小，故可以忽略源漏区应力对其电阻的影响。但对于LDMOS器件，由于漂移区掺杂较低且长度较长，漂移区电阻较大，这种情况下应力对漂移区电阻影响较大。LDMOS器件漂移区面积较大，受边界条件限制，难以通过直接覆盖应变氮化硅盖帽层方式向漂移区中引入有效应力以降低其电阻。
为了降低LDMOS漂移区电阻，采用的办法主要为提高漂移区掺杂浓度，但掺杂的增加将导致其耗尽区变窄，过高的漂移区掺杂会使漂移区不能全耗尽，从而使击穿电压降低。为了在增大漂移区掺杂，降低漂移区电阻的同时保证漂移区的全耗尽，卢瑟福技术的提出迅速获得广泛的推广，人们通过在漂移区的下方引入与漂移区相反类型的掺杂，从而在漂移区与漂移区下方之间形成P-N结，以N型LDMOS为列，漏端高压时，该P-N结反偏将促进漂移区的耗尽，从而可将漂移区掺杂提升，将其厚度减小，获得导通电阻降低与击穿电压的提升。但太薄的漂移区会使得漏端垂直方向击穿电压降低，故为保证击穿，漂移区厚度不能太小。于是又有研究者提出超晶结漂移区LDMOS器件，其结构如图2所示，包括半导体衬底1，沟道掺杂区2，漂移区3，源重掺杂区4，栅氧6，栅8，与漂移区掺杂类型相反的区域17。在N型掺杂的漂移区3中引入延源漏方向的P型掺杂的槽型条状区域17，通过P型掺杂的槽型条状区域17在关断时促进N型掺杂的漂移区3的耗尽，可实现漂移区全耗尽不受漂移区厚度的限制，有效避免垂直方向的击穿，从而提高器件的击穿电压。但P型掺杂的槽型条状区域17的存在减小了漂移区有效的导电区域，对降低漂移区寄生电阻不利，这也限制了器件性能的提高，尤其对RF(射频)、小尺寸LDMOS的性能影响较大。
发明内容
本发明针对背景技术存在的缺陷，提出了一种带槽型结构的应变NLDMOS器件及其制作方法。本发明在漂移区沿源漏方向引入P型掺杂的槽型结构，一方面，该槽型结构为应力源，可向漂移区宽度方向引入压应力和长度方向引入张应力，从而提高漂移区电子迁移率、降低漂移区电阻；另一方向，在槽型结构中引入与漂移区相反类型的掺杂，使关断时漂移区更容易实现全耗尽，从而提高器件的击穿电压。本发明提出的N型LDMOS器件(NLDMOS)在保证击穿电压的同时降低了漂移区的电阻，提升了器件的性能。
本发明的技术方案如下：
一种带槽型结构的应变NLDMOS器件，包括半导体衬底1、沟道掺杂区2、漂移区3、源重掺杂区4、漏重掺杂区5、栅氧6、场氧7、栅8，其特征在于，还包括设置在漂移区的沿源漏方向的P型掺杂的槽型结构10，所述槽型结构10向漂移区的宽度方向引入压应力，长度方向引入张应力。
其中，所述槽型结构的上表面到下表面的垂直距离大于漂移区厚度的一半。
进一步地，所述槽型结构的宽度小于0.2μm，所述槽型结构之间的间距小于0.3μm。所述槽型结构10的左边缘与场氧的右边缘重合，槽型结构10的右边缘与漏重掺杂区5左边缘的距离大于漂移区厚度的五分之一。
具体地，所述漂移区槽型结构为矩形、梯形、阶梯形或闭口U形。
具体地，所述漂移区槽型结构为梯形或阶梯形时，所述梯形或阶梯形的长边位于槽型结构的上表面；所述漂移区槽型结构为闭口U形时，闭口U形的闭口线位于槽型结构的上表面。
进一步地，所述槽型结构内的介质层为二氧化硅。
进一步地，所述槽型结构内的介质层为无定型硅、无定型锗或无定型锗硅热处理生成的多晶硅、多晶锗或多晶锗硅，或者其他热处理体积膨胀的介质材料。
一种带槽型结构的应变NLDMOS器件的制作方法，其特征在于，包括以下步骤：
步骤1：在半导体衬底1上按传统LDMOS工艺制作N型LDMOS器件的漂移区，沟道掺杂区，栅氧，场氧，栅，源重掺杂区，漏重掺杂区；
步骤2：在漂移区制作应变槽型结构10，同时对漂移区槽型结构进行P型离子掺杂，并通过对槽型结构进行热处理向漂移区3宽度方向引入压应力，长度方向引入张应力。
其中，步骤2的具体过程为：淀积刻蚀阻挡层掩膜14，在漂移区采用干法刻蚀的方法得到槽15，然后向槽内淀积无定型硅、无定型锗或无定型锗硅，并进行P型掺杂，然后退火使无定型硅、无定型锗或无定型锗硅变成多晶硅、多晶锗或多晶锗硅，发生体积膨胀从而向漂移区3宽度方向引入压应力，长度方向引入张应力；然后去除刻蚀阻挡层掩膜14。
其中，步骤2的具体过程还可以为：淀积刻蚀阻挡层掩膜14，对槽型结构进行P型离子注入和氧离子注入，然后退火处理以将硅氧化成二氧化硅，从而通过氧化过程中的体积膨胀向漂移区3宽度方向引入压应力，长度方向引入张应力；然后去除刻蚀阻挡层掩膜14。其中，氧离子的注入深度大于漂移区厚度的一半，氧离子的注入量小于槽型结构内一半的硅氧化成二氧化硅所需的量，所述槽型结构内包含硅和二氧化硅，P型离子掺杂在硅内。
其中，所述槽型结构的上表面到下表面的垂直距离大于漂移区厚度的一半。
进一步地，所述槽型结构的宽度小于0.2μm，所述槽型结构之间的间距小于0.3μm。所述槽型结构10的左边缘与场氧的右边缘重合，槽型结构10的右边缘与漏重掺杂区5左边缘的距离大于漂移区厚度的五分之一。
具体地，所述漂移区槽型结构为矩形、梯形、阶梯形或闭口U形。
具体地，所述漂移区槽型结构为梯形或阶梯形时，所述梯形或阶梯形的长边位于槽型结构的上表面；所述漂移区槽型结构为闭口U形时，闭口U形的闭口线位于槽型结构的上表面。
本发明的有益效果为：本发明在漂移区沿源漏方向引入与漂移区相反类型掺杂的槽型结构，一方面，通过对槽型结构热处理过程中体积的膨胀挤压漂移区，从而在漂移区宽度方向引入压应力，在漂移区长度方向引入张应力，从而提高漂移区电子迁移率、降低漂移区电阻；另一方面，在槽型结构中引入与漂移区相反类型的掺杂，使关断时漂移区更容易实现全耗尽，从而提高器件的击穿电压。本发明NLDMOS器件实现了在提高击穿电压的同时降低漂移区电阻、提高了器件的频率，提升了器件的性能。
附图说明
图1为现有的应变LDMOS器件剖面图。
图2为现有超晶结漂移区LDMOS器件的结构示意图。
图3为本发明提出的带槽型结构的应变NLDMOS器件剖面图。
图4为本发明提出的带槽型结构的应变NLDMOS器件的俯视图。
图5为传统无氮化硅盖帽的LDMOS器件沿源漏方向剖面图。
图6为本发明提出的带槽型结构的应变NLDMOS器件带刻蚀阻挡层时的俯视图。
图7为本发明中漂移区的槽型结构刻蚀后器件沿源漏方向的剖面图。
图8为本发明中漂移区的槽型结构刻蚀后器件沿漂移区宽度方向的剖面图。
图9为本发明中漂移区的槽型结构内填充无定型材料退火生成多晶材料后器件沿漂移区宽度方向的剖面图。
图10为本发明中漂移区的槽型结构区域氧离子注入和P型掺杂后器件沿源漏方向的剖面图。
图11为本发明中漂移区的槽型结构区域氧离子注入和P型掺杂后器件沿漂移区宽度方向的剖面图。
图12为本发明中器件漂移区的槽型结构区域氧离子注入并退火使氧离子与硅反应生成二氧化硅后器件沿源漏方向的剖面图。
图13为本发明中漂移区槽型结构为梯形时沿漂移区宽度方向器件的剖面图。
图14为本发明中漂移区槽型结构为阶梯形时沿漂移区宽度方向器件的剖面图。
图15为本发明中漂移区槽型结构为闭口U形时沿漂移区宽度方向器件的剖面图。
其中，1为半导体衬底，2为沟道掺杂区，3为漂移区，4为源重掺杂区，5为漏重掺杂区，6为栅氧，7为场氧，8为栅，9为应变氮化硅盖帽层，10为漂移区槽型结构，14为刻蚀阻挡层掩膜，15为漂移区槽被刻蚀区域，16为向漂移区槽型结构中注入的氧离子，17为向漂移区槽型结构中注入的P型离子，18为氧离子与漂移区槽型结构内硅反应生成的二氧化硅。
具体实施方式
下面结合附图及实施例，对本发明做进一步的介绍。
实施例1
本例采用向槽型结构区域淀积无定型材料，然后通过高温退火处理使无定型材料向多晶材料转化过程中体积的膨胀向漂移区宽度方向引入压应力，长度方向引入张应力；同时对槽型结构进行与漂移区相反的P型掺杂，使漂移区形成超晶结结构，提升器件击穿电压，同时降低导通电阻，提高频率。
一种带槽型结构的应变NLDMOS器件，包括半导体衬底1，沟道掺杂区2，漂移区3，源重掺杂区4，漏重掺杂区5，栅氧6，场氧7，栅8，位于漂移区的沿源漏方向的P型掺杂的槽型结构10，所述槽型结构10向漂移区的宽度方向引入压应力、长度方向引入张应力。
其中，所述槽型结构的上表面到下表面的垂直距离大于漂移区厚度的一半。
进一步地，所述槽型结构的宽度小于0.2μm，所述槽型结构之间的间距小于0.3μm。所述槽型结构10的左边缘与场氧的右边缘重合，槽型结构10的右边缘与漏重掺杂区5左边缘的距离大于漂移区厚度的五分之一。
具体地，所述漂移区槽型结构为矩形、梯形、阶梯形或闭口U形。
具体地，所述漂移区槽型结构为梯形或阶梯形时，所述梯形或阶梯形的长边位于槽型结构的上表面；所述漂移区槽型结构为闭口U形时，闭口U形的闭口线位于槽型结构的上表面。
本实施例的带槽型结构的应变NLDMOS器件的制作方法，包括以下步骤：
步骤1：按传统LDMOS工艺制作NLDMOS器件的漂移区，沟道掺杂区，栅氧，场氧，栅，源重掺杂区，漏重掺杂区，其沿源漏方向剖面图如图5所示；
步骤2：淀积刻蚀阻挡层掩膜14，在漂移区采用干法刻蚀的方法得到槽15，其俯视图如图6所示，沿漂移区长度方向过槽区域剖面图如图7所示，过槽区域沿漂移区宽度方向剖面图如图8所示；
步骤3：向漂移区槽15中淀积无定型硅、无定型锗或无定型锗硅，并进行P型掺杂(漂移区为N型掺杂)，然后退火使无定型硅、无定型锗或无定型锗硅变成多晶硅、多晶锗或多晶锗硅时，发生体积膨胀从而向漂移区3宽度方向引入压应力，长度方向引入张应力，其过槽区域沿漂移区宽度方向的剖面图如图9所示。
步骤4：去除刻蚀阻挡层掩膜14，然后按LDMOS工艺进行电极，互连线等的制作，得到所述的NLDMOS器件。
实施例2
本例采用向槽型结构区域进行氧离子注入，使氧离子与硅发生反应生成二氧化硅，通过硅氧化过程中体积的膨胀从而向漂移区宽度方向引入压应力，长度方向引入张应力；同时对槽型结构进行与漂移区相反的P型掺杂，使漂移区形成超晶结结构，提升器件击穿电压，同时降低导通电阻，提高频率。
一种带槽型结构的应变NLDMOS器件，包括半导体衬底1，沟道掺杂区2，漂移区3，源重掺杂区4，漏重掺杂区5，栅氧6，场氧7，栅8，位于漂移区的沿源漏方向的P型掺杂的槽型结构10，所述槽型结构10向漂移区的宽度方向引入压应力、长度方向引入张应力。
其中，所述槽型结构的上表面到下表面的垂直距离大于漂移区厚度的一半。
进一步地，所述槽型结构的宽度小于0.2μm，所述槽型结构之间的间距小于0.3μm。所述槽型结构10的左边缘与场氧的右边缘重合，槽型结构10的右边缘与漏重掺杂区5左边缘的距离大于漂移区厚度的五分之一。
具体地，所述漂移区槽型结构为矩形、梯形、阶梯形或闭口U形。
具体地，所述漂移区槽型结构为梯形或阶梯形时，所述梯形或阶梯形的长边位于槽型结构的上表面；所述漂移区槽型结构为闭口U形时，闭口U形的闭口线位于槽型结构的上表面。
本实施例的带槽型结构的应变NLDMOS器件的制作方法，包括以下步骤：
步骤1：按传统LDMOS工艺制作NLDMOS器件的漂移区，沟道掺杂区，栅氧，场氧，栅，源重掺杂区，漏重掺杂区，其沿源漏方向剖面图如图5所示；
步骤2：淀积刻蚀阻挡层掩膜14，对槽型结构区域进行P型离子17的注入和氧离子16的注入，氧离子注入的最大深度大于漂移区厚度的一半，氧离子的注入量小于槽型结构内一半的硅氧化生成二氧化硅所需的量，其沿源漏方向过槽区域的剖面图如图10所示，过槽区域沿漂移区宽度方向的剖面图如图11所示；
步骤3：退火使槽型结构区域内的氧离子与硅反应生成二氧化硅18，通过硅氧化过程中体积的膨胀从而向漂移区宽度方向引入压应力，长度方向引入张应力；
步骤4：去除刻蚀阻挡层掩膜14，其沿源漏方向的剖面图如图12所示，然后按LDMOS工艺进行电极，互连线等的制作，得到所述的NLDMOS器件。

Claims (8)

1.一种带槽型结构的应变NLDMOS器件，包括半导体衬底(1)、沟道掺杂区(2)、漂移区(3)、源重掺杂区(4)、漏重掺杂区(5)、栅氧(6)、场氧(7)、栅(8)，其特征在于，还包括设置在漂移区的沿源漏方向的P型掺杂的槽型结构(10)，所述槽型结构内的介质层为二氧化硅或热处理体积膨胀的介质材料，所述槽型结构(10)向漂移区的宽度方向引入压应力，长度方向引入张应力。
2.根据权利要求1所述的带槽型结构的应变NLDMOS器件，其特征在于，所述槽型结构(10)的上表面到下表面的垂直距离大于漂移区厚度的一半。
3.根据权利要求1所述的带槽型结构的应变NLDMOS器件，其特征在于，所述槽型结构的宽度小于0.2μm，所述槽型结构的槽间距小于0.3μm，所述槽型结构(10)的左边缘与场氧的右边缘重合，槽型结构(10)的右边缘与漏重掺杂区(5)左边缘的距离大于漂移区厚度的五分之一。
4.根据权利要求1所述的带槽型结构的应变NLDMOS器件，其特征在于，所述槽型结构(10)为矩形、梯形、阶梯形或闭口U形。
5.根据权利要求1所述的带槽型结构的应变NLDMOS器件，其特征在于，所述槽型结构(10)为梯形或阶梯形时，所述梯形或阶梯形的长边位于槽型结构的上表面；所述槽型结构(10)为闭口U形时，闭口U形的闭口线位于槽型结构的上表面。
6.一种如权利要求1所述的带槽型结构的应变NLDMOS器件的制作方法，其特征在于，包括以下步骤：
步骤1：在半导体衬底(1)上按传统LDMOS工艺制作N型LDMOS器件的漂移区，沟道掺杂区，栅氧，场氧，栅，源重掺杂区，漏重掺杂区；
步骤2：在漂移区制作应变槽型结构(10)，同时对漂移区槽型结构进行P型离子掺杂，并通过对槽型结构进行热处理向漂移区(3)宽度方向引入压应力，长度方向引入张应力。
7.根据权利要求6所述的带槽型结构的应变NLDMOS器件的制作方法，其特征在于，所述步骤2的具体过程为：淀积刻蚀阻挡层掩膜(14)，在漂移区采用干法刻蚀的方法得到槽(15)，然后向槽内淀积无定型硅、无定型锗或无定型锗硅，并进行P型掺杂，然后退火使无定型硅、无定型锗或无定型锗硅变成多晶硅、多晶锗或多晶锗硅，发生体积膨胀从而向漂移区(3)宽度方向引入压应力，长度方向引入张应力；然后去除刻蚀阻挡层掩膜(14)。
8.根据权利要求6所述的带槽型结构的应变NLDMOS器件的制作方法，其特征在于，所述步骤2的具体过程为：淀积刻蚀阻挡层掩膜(14)，对槽型结构区域进行P型离子注入和氧离子注入，然后退火处理以将硅氧化成二氧化硅，从而通过氧化过程中的体积膨胀向漂移区(3)宽度方向引入压应力，长度方向引入张应力；然后去除刻蚀阻挡层掩膜(14)。
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