CN1989604B - 功能元件及其制造方法、以及功能元件装配结构体 - Google Patents
功能元件及其制造方法、以及功能元件装配结构体 Download PDFInfo
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- CN1989604B CN1989604B CN2005800252232A CN200580025223A CN1989604B CN 1989604 B CN1989604 B CN 1989604B CN 2005800252232 A CN2005800252232 A CN 2005800252232A CN 200580025223 A CN200580025223 A CN 200580025223A CN 1989604 B CN1989604 B CN 1989604B
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- Wire Bonding (AREA)
Abstract
一种半导体元件,在半导体基板(1)上形成有规定图形的衬底电极层(2),并且,在衬底电极层(2)的局部上表面形成有表面电极层(3),其中,在表面电极层(3)正下方的衬底电极层(2)上表面形成有沿厚度方向延伸的孔部(2X),并且,孔部(2X)的深度比衬底电极层(2)的厚度浅。
Description
技术领域
本发明涉及一种功能元件及其制造方法、以及功能元件装配结构体。
背景技术
半导体元件等功能元件需要用于与电源连接或进行电信号的输入输出的电极。以前,作为在功能元件上形成的电极,公知的有在铝电极等衬底电极层上形成镍膜等表面电极层而构成的电极等。例如,专利文献1中公开了一种以下的构成,即,在半导体基板上作为衬底电极层形成铝电极,再在其上利用溶解了氢氧化钠与氧化锌的锌酸盐处理液析出锌后,通过无电场镀镍形成作为表面电极层的镍膜。
【专利文献1】特开平11-214421号公报
发明内容
发明所要解决的技术课题
但是,在以往的电极中,由于衬底电极层与基板的密接不充分,所以有时衬底电极层从基板上剥离。为此,本发明的目的在于提供一种可提高电极与基板的密接力的功能元件。
解决技术课题的手段
本发明的功能元件,具有:基板、形成在该基板一主面上的衬底电极层、按照使所述衬底电极层的局部露出的方式而形成的保护层和在从该保护层露出的部分的所述衬底电极层形成的表面电极层,其特征在于:所述衬底电极层与所述表面电极层的界面区域的所述衬底电极层的上表面比所述衬底电极层与所述保护层的界面区域的所述衬底电极层的上表面低,在所述衬底电极层内形成有从所述衬底电极层与所述表面电极层的界面区域沿所述衬底电极层厚度方向延伸的多个孔部,并且,所述多个孔部由贯通所述衬底电极层的孔部和没有贯通所述衬底电极层的孔部组成,从而所述孔部的平均深度比所述衬底电极层的厚度浅。
优选:所述孔部内填充有所述表面电极层的一部分。
并且优选:在上述衬底电极层上覆盖着包围在上述表面电极层周围的保护层,上述表面电极层的一部分填充到在上述保护层与衬底电极层的界面区域沿平面方向延伸的凹部中。
另外,优选在上述表面电极层上形成有钎料层。
并且优选在上述表面电极层上形成有金(Au)层。
另外,本发明的功能元件装配结构体,其特征在于:在具有电路布线的基体一主面上设有用于装配本发明的功能元件的焊盘部,通过电连接该焊盘部与上述功能元件的表面电极层(或在其上形成的钎料层或金层),而将上述功能元件装配在上述基体上。
另外,本发明的功能元件的制造方法,其特征在于,包括:在基板一主面上形成衬底电极层的第1工序;形成保护层且使所述衬底电极层的局部露出的第2工序;通过干蚀刻除去在所述衬底电极层的露出部形成的氧化膜,在所述露出部使所述衬底电极层的整个表面露出的第3工序;通过将所述基板浸渍在锌酸盐液中,而在所述露出部中的所述衬底电极层形成由贯通该衬底电极层的孔部和没有贯通所述衬底电极层的孔部组成的多个孔部的第4工序;通过将所述基板浸渍在无电解镀液中,从而在所述衬底电极层上形成表面电极层的第5工序。
优选:上述基板是半导体基板,在上述第3工序前,经过研磨所述半导体基板的另一主面且在研磨后露出的半导体基板材料的另一主面上形成氧化膜的工序。
发明效果
本发明人发现衬底电极层与基板的密接力低的原因之一是因为:如图5所示,在衬底电极层上形成有从上表面到下表面的许多贯通孔。在衬底电极层形成有许多贯通孔时,成为表面电极层的金属难以充分析出到衬底层的贯通孔最深部。因此,存在在衬底层的贯通孔的最深部附近形成空穴的情形。若具有这样的空穴,则基板与衬底电极层的密接区域相应减小,结果导致基板与衬底电极层的密接力降低。根据本发明的功能元件,虽然在衬底电极层形成有多个孔部,但是该孔部中的大多数并不贯穿到基板。因此,可抑制基板与衬底电极层的密接面积减小,能够提高两者的密接力。并且,如果表面电极层的一部分还填充到孔部内,则即使衬底电极层与表面电极层之间也难产生剥离。因此,装配在例如具有电路布线的基体上的 功能元件中,即使在表面电极层施加热应力等情况下、也不容易产生电极剥离。
另外,由于孔部的深度比贯通孔浅,所以表面电极层的一部分也可填充到孔部的最深部附近。从而,可防止在锌酸盐液、蚀刻液等各工序中使用的药液残留在孔部的最深部附近。并且,由于使表面电极层的一部分也填充到在与保护层交界的界面区域形成的衬底电极层凹部中,所以这样也能够防止药液残留。据此,也能够抑制药液对衬底电极层、表面电极层的腐蚀。
另外,通过采用本发明的制造方法制造功能元件,从而即使在形成于表面电极层上的钎料凸起上施加热应力等,也能够获得在基板与衬底电极层之间、以及衬底电极层与表面电极层之间不容易产生剥离的功能元件。
并且,如上所述,在上述基板为半导体基板时,优选在无电解镀工序前经过研磨上述半导体基板下表面、并且在研磨后露出的半导体基板材料表面形成氧化膜的工序。据此,即使在金属片附着于该半导体基板下表面的情况下,也能够除去该金属片且防止研磨后的半导体基板露出。从而,能够防止镀层材料向该金属片或半导体基板的露出部中析出。
而且,通过防止镀层材料向该金属片等中析出,能够只在本来作为镀层対象的衬底电极层上表面施予镀层。从而,在衬底电极层上表面析出镀层材料时,能够有效抑制析出时间变长及称为瘤的突起物的产生。据此,能够在规定的时间内在衬底电极层上表面稳定地形成理想的表面电极层。
附图说明
图1是本发明的一实施方式的半导体元件的局部断面图。
图2是用于说明图1的半导体元件的局部平面图。
图3A是说明图1的半导体元件的制造方法的工序的局部断面图。
图3B是表示图3A的下一工序的局部断面图。
图3C是表示图3B的下一工序的局部断面图。
图3D是表示图3C的下一工序的局部断面图。
图3E是表示图3D的下一工序的局部断面图。
图4是本发明的功能元件装配结构体的局部断面图。
图5是半导体元件的局部断面图。
图6A是说明图5的半导体元件的制造方法的工序的局部断面图。
图6B是表示图6A的下一工序的局部断面图。
图6C是表示图6B的下一工序的局部断面图。
图6D是表示图6C的下一工序的局部断面图。
图6E是表示图6D的下一工序的局部断面图。
图7是在本发明的实施例中使用的共负强度测定装置的示意侧视图。
图8是表示在本发明的实施例中进行的共负强度试验的情形的侧面图。
符号说明
1-半导体基板,2-衬底电极层,2X-孔部,2Y-凹部,3-表面电极层,4-保护层,5-Zn粒子,6-基体,7-电路图形,8-焊盘部,9-钎料层,10-密封树脂,21-球共负传感器(ball share sensor),22-共负刀具,23-工作台,S-氧化膜,K-空穴,M-共负强度测定装置。
实施发明的最佳方式
以下,基于附图以半导体元件为例详细地说明本发明的功能元件。
图1是本发明的功能元件一例的半导体元件的局部断面图。图1所示的半导体元件由半导体基板1、衬底电极层2、表面电极层3及保护层4构成。在构成该半导体元件的半导体基板1表面形成有用于实现半导体功能的衬底电极层2及与该衬底电极层2电连接的表面电极层3。在该半导体基板1上覆盖着保护层4,该保护层4覆盖衬底电极层2。而且,衬底电极层2的一部分从保护层4露出,在该露出部上形成表面电极层3。另外,在衬底电极层2的与表面电极层3交界的界面区域形成有多个孔部2X。表面电极层3填充到在该孔部2X中。
半导体基板1例如采用单晶硅等。在半导体基板1内部也可以根据需要集成有由P型区域、N型区域、绝缘区域等构成的晶体管等功能电路等,并形成有电连接这些功能电路之间的电极层等。而且,在基板一主面上覆盖着衬底电极层2、表面电极层3、保护层4等。
形成在半导体基板1上的规定图形的衬底电极层2优选由Al、Al-Cu、Al-Si、Al-Si-Cu等金属材料形成。另外,优选覆盖的厚度为0.5μm~2.0μm。衬底电极层2发挥作为用于供给电源电力、电信号等而与外部电路连接的连接电极的功能。而且,衬底电极层2的一部分从保护层4露出。此外,该露出部例如为圆形状,其直径优选为40μm~100μm左右。该露出部的衬底电极层2的上表面优选比保护层4正下方的衬底电极层2的上表面约低5nm~50nm。
另外,优选在位于包围上述露出部的保护层4下的衬底电极层2,从露出部侧沿与保护层4交界的界面区域的大致水平方向上形成凹部2Y,该凹部2Y的向内尺寸例如为5nm~50nm、厚度例如为5nm~50nm。如果从保护层4露出的衬底电极层2在俯视状态下为圆形,则该凹部2Y呈环状。
另一方面,在露出部的衬底电极层2上表面形成有多个孔部2X,该孔部2X从衬底电极层2的上表面向衬底电极层2内部延伸,但不会达到半导体基板1的上表面。因此,不会减小半导体基板1与衬底电极层2的密接面积,从而不会降低其密接力。据此,即使在为了例如将半导体元件装配在具有电路布线的基体等上而对衬底电极层2施加应力的情况下,也不容易在半导体基板1与衬底电极层2之间产生剥离。而且,即使孔部2X的一部分达到半导体基板1上表面,只要孔部2X的平均的深度比衬底电极层2的厚度小,也可获得上述效果。
并且,优选该孔部2X的深度约为50nm~200nm。另外,虽然孔部2X的延伸方向基本上朝下,但也可以有的地方弯曲。如果有一部分弯曲,则可提高衬底电极层2与表面电极层3的密接力。另外,该孔部2X在俯视状态下优选约设为1个/μm2~20个/μm2。并且,孔部2X的直径优选约为10nm~500nm。
然后,在该衬底电极层2上形成表面电极层3。与衬底电极层2电连接的表面电极层3通过覆盖Ni(镍)等金属材料而形成。该表面电极层3,使电极从保护层4突出,并且,在例如夹隔着钎料层将半导体基板1装配在电路基体上时,可起到防止衬底金属层2向钎料层中扩散的功能。
该表面电极层3优选覆盖衬底电极层2上表面、且其一部分填充到孔 部2X内的最深部附近。据此,可抑制在半导体元件制造工序中浸入的锌酸盐液或蚀刻液等药液残留在孔部2X的最深部附近。从而,能够抑制药液腐蚀衬底电极层2或表面电极层3。并且,优选在衬底电极层2的与保护层4的界面区域形成的沿水平方向延伸的凹部2Y也填充表面电极层3。这样也可抑制药液的残留。
另外,由于表面电极层3的一部分埋入衬底电极层2的孔部2X内,所以可使表面电极层3与衬底电极层2牢固密接在一起。从而,在将半导体元件安装在具有电路布线的基体等外部装置上时,即使表面电极层3受到某种外力而被向上或横向拉,表面电极层3也很难从衬底电极层2上被剥离。尤其,若使孔部2X的直径因位置不同而改变、或者还设有弯曲等,则表面电极层3更难从衬底电极层2上剥离。并且,如果在衬底电极层2的凹部2Y内也填充有表面电极层3,则即使表面电极层3被所述外力等拉,但由于保护层4的存在可进一步抑制剥离。
反之,如图5所示,如果穿过衬底电极层12的孔部12Z达到半导体基板11,则衬底电极层12与半导体基板11的密接力降低。在图5的半导体元件中,设置了多个从衬底电极层12的上表面到下表面的贯通孔12Z。而且,形成表面电极层13的局部进入该贯通孔12Z内的结构。另外,在位于露出部的衬底电极层12周围的保护层14的正下方区域存在沿保护层14与衬底电极层12的界面平面延伸的凹部12Y。
成为表面电极层13的金属不能充分地析出到衬底电极层12上形成的贯通孔12Z最深部附近,据此,有时会在贯通孔12Z的最深部附近形成空穴K。另外,有时形成在保护层14与衬底电极层12的界面区域的凹部12Y的前端部附近也不能充分地析出Ni、而形成空穴K。在这样具有空穴K时,半导体基板11与衬底电极层12的密接区域则因空穴K的存在而相应减少,结果导致它们之间的密接力降低。
另外,即使Ni析出到贯通孔12Z的最深部附近,也不能充分抑制半导体基板11上表面与衬底电极层12的密接力降低。这是因为:根据无电解镀析出产生的表面电极层13与半导体基板11的密接力比根据溅射、CVD真空镀膜等薄膜形成技术形成的衬底电极层12与半导体基板11的密接力弱。因此,例如在将半导体元件装配在具有电路布线的基体等上时, 如果对衬底电极层12施加来自外部的应力等,则容易在半导体基板11与衬底电极层12之间产生剥离。
另外,在贯通孔12Z的最深部附近存在空穴K时,锌酸盐液、蚀刻液等在各工序使用的药液会残留在该空穴K中,造成产生腐蚀的原因。并且,该药液残留问题也会在与保护层14的界面区域形成的衬底电极层12的凹部12Y产生。即,若在该凹部12Y前端部附近形成有空穴K,则有时药液残留在该空穴K中而产生腐蚀。
在图1所示的半导体元件,覆盖衬底电极层2上表面的保护层4形成在半导体基板1上并使上述表面电极层3露出。作为保护层4的具体材料可例示出氮化硅(Si3N4)、氧化硅(SiO2)、聚酰亚胺等电绝缘材料。该保护层4由于覆盖表面电极层3周围的衬底电极层2的一部分,所以形成该覆盖部与其他区域相比保护层4表面向上方鼓起的形状。而且,保护层4将半导体基板1上的功能电路、衬底电极层2等与大气良好地隔绝,从而可起到有效地防止这些部分与大气中所含的水分等接触而被腐蚀的作用。保护膜4可通过采用以往公知的薄膜加工方法而形成在半导体基板1上表面,优选厚度形成为0.5μm~2.0μm。
(功能元件的制造方法)
接着,参照图3A~E以半导体元件为例对本发明的功能元件的制造方法的一例进行说明。
工序(a)
首先,如图3A所示,在集成了功能电路的半导体基板1上形成规定图形的衬底电极层2。该衬底电极层2通过溅射等方法成膜,之后通过光刻技术形成为规定图形。
工序(b)
接着,如图3B所示,以采用溅射法覆盖衬底电极层2整个面的方式形成保护层4,并利用光刻技术在保护层4上设置规定开口,使衬底电极层2的一部分露出。在该露出部形成表面电极层3。另外,在该溅射时对半导体基板进行了加热。通过该保护层形成工序的热处理等在衬底电极层的露出部表面形成被称为小丘(hillock)的凸部。并且,由于在形成该保护层时经过进行包括热处理的工序,所以在如上述方式形成的凸部的衬底电 极层2的露出部表面,Al等处衬底电极层材料会氧化形成Al2O3(氧化膜)等氧化膜S。该状態下的衬底电极层2的露出部的表面状态粗糙,算术平均粗糙度为0.01μm~0.02μm。另外,氧化膜S的厚度也存在不均。
以下,对工序(c)~(e)中通过无电解镀法形成表面电极层13的形成工序进行说明。
工序(c)
接着,如图3C所示那样干蚀刻上述的衬底电极层的露出部。有时在该干蚀刻之前首先通过湿蚀刻除去附着在半导体元件上油脂等残留薄膜及形成氧化膜S的薄膜。本工序的干蚀刻目的在于除去上述的厚度不均的氧化膜S,据此,使衬底电极层2的形成材料Al在大致整个表面露出。
另外,在本工序(c)之后、下一工序(d)之前,在衬底电极层2上通过与空気中的氧接触而形成均匀厚度的自然氧化膜(未图示)。该自然氧化膜与上述的因热处理而形成的氧化膜S相比其厚度薄、且厚度不均也小。
工序(d)
接着,如图3D所示那样将上述的半导体元件浸渍在锌酸盐液中。这时在工序(c)结束后形成的大致均匀厚度的自然氧化膜,由于锌酸盐液的蚀刻作用会最行被除去。然后,在除去自然氧化膜的过程中衬底电极层2的大致整个面露出,同时,该露出的面上的衬底电极层2的材料Al与锌酸盐液中的催化剂金属Zn置换析出细小的Zn粒子5。
不过,在上述的衬底电极层的Al表面会有自然氧化膜残留。该自然氧化膜残留区域下的衬底电极层由于与上述的露出区域相比多少会迟一些在锌酸盐液中露出,所以该新的露出区域即上述自然氧化膜残留区域与自然氧化膜除去区域相比,因电池作用引起的Al的溶解比上述的Al与Zn的置换作用更显著,其结果在该露出区域局部形成孔部2X。
另外,该衬底电极层2的蚀刻不仅在厚度方向上进行、在沿保护层4与衬底电极层2的界面的水平方向上也进行,在与露出部相邻的保护层4下侧形成俯视状态下为环形的凹部2Y。
另一方面,在上述的孔部2X周围会有Zn粒子5析出,经过一定时间Zn粒子5的析出密度变高,覆盖衬底电极层的孔部2X上表面。据此,不容易向孔部2X中供给新鲜的锌酸盐液。从而,因电池作用引起的衬底电极层2的Al溶解也不容易进行,即使经过该锌酸盐处理工序,孔部2X也不会像以往那样形成贯通。另外,上述孔部2X、凹部2Y的内壁也局部有Zn粒子5析出。
工序(e)
最后,如图3E所示那样形成表面电极层3。在该工序(e)中,在衬底电极层2的露出部通过无电解镀法形成由Ni构成的表面电极层3。这时,在衬底电极层2的露出部大致整个面析出的Zn粒子5、在孔部2X、凹部2Y的内壁析出的Zn粒子5与Ni置换,在该置换作用之后,Ni层会基于Ni的自催化作用而生成,形成表面电极层3。据此,本发明的半导体元件完成。
根据该制造方法,与以往的制造方法相比孔部2X不容易贯通、或者除了不贯通之外与以下说明的方法相比可减少锌酸盐处理、蚀刻处理的次数。
图6A~E示出对于衬底电极层的露出部不干蚀刻而进行锌酸盐处理的制造方法。若采用这样的制造方法,则锌酸盐处理等次数增多,并且容易成为图5所示的状态。
首先,如图6A所示,在半导体基板11上形成规定图形的衬底电极层12,通过光刻技术形成为规定图形。然后,如图6B所示,以覆盖衬底金属层12整个面的方式形成保护层14,通过光刻技术在保护层14设置规定的开口。这之前的工序,与上述的方法相同,也在衬底电极层12表面产生小丘等凸部、衬底电极层12表面氧化形成氧化膜(未图示)。该氧化膜比较厚且厚度不均较大。
接着,如图6C所示,进行第1锌酸盐处理。首先,除去附着在半导体元件上表面的油脂等残留薄膜。之后,将半导体元件浸渍在锌酸盐液中。这时在锌酸盐液中根据蚀刻作用除去在衬底电极层12上表面形成的氧化膜。而且,由于上述的衬底电极层12的凸部比其他的衬底电极层12表面区域先在锌酸盐液中露出,所以凸部的衬底电极层12与锌酸盐液中的催化剂金属、例如Zn(锌)置换析出Zn粒子15。而且,根据新的Zn粒子析出在以往有凸部的区域Zn粒子15生长,并且,未曾露出过的部位的氧化膜除去的过程也在进行。但是,即使有基于该除去的进行而新露出的区域,在该新的露出区域也不仅因置换作用析出Zn、而且因电池作用引起Al向锌酸盐液中的溶解显著。据此,在新的露出区域形成贯穿衬底电极层12的贯通孔12Z。另外,在存在于与保护层14交界的界面上的衬底电极层12也根据上述的锌酸盐液的蚀刻作用而产生溶解,形成沿与该保护层14交界的界面区域的平面方向延伸的凹部12Y。
接着,如图6D所示通过湿蚀刻除去在衬底电极层12上析出的Zn粒子。据此,再次在上表面呈现出平坦的Al表面。这样,衬底电极层12除了贯通孔12Z形成区域之外上表面都是平坦的,之后,衬底电极层12上表面自然氧化形成的氧化膜(自然氧化膜)成为大致均匀的厚度。
然后,如图6E所示,接着进行第2锌酸盐处理。由于上述的自然氧化膜具有大致均匀的厚度,所以在根据蚀刻作用除去自然氧化膜时,衬底电极层12的整个上表面大致同时地在锌酸盐液中露出,除了贯通孔12Z之外的整个表面都大致均匀地析出Zn粒子15。因此,Zn粒子15彼此间的距离相互靠近,且其粒子变细。若这样细的Zn粒子15彼此间靠近析出,则在比较短时间内析出的Zn粒子15形成堆积层。另一方面,虽然在贯通孔12Z内壁也析出Zn,但是,有时在贯通孔12Z的最深部附近不析出Zn。
最后,如图5所示,在衬底电极层12的贯通孔12Z内部及衬底电极层12上根据无电解镀法析出成为表面电极层13的金属Ni。在以这样的方法形成电极时,需要进行2次锌酸盐处理,在锌酸盐处理中形成的孔部12Z容易变深。从而,如图5所示,有可能成为有许多孔部12Z贯穿到半导体基板1的状态。这样一来,成为表面电极层13的金属不能充分析出到在衬底电极层12上形成的贯通孔12Z最深部附近,据此,容易在贯通孔12Z最深部附近形成空穴K。另外,在上述的与保护层14交界的界面区域的衬底电极层12的凹部12Y的前端部附近Ni也会不充分析出,容易形成空穴K。
因此,如图3A~E所述,优选通过干蚀刻减薄自然氧化膜,且使其均匀后进行锌酸盐处理,据此,可形成密接性优越、不容易产生腐蚀的电极。
此外,本发明的制造方法并不局限于上述的实施方式,可在不脱离本发明要旨的范围内进行各种变更、改良等。
例如,上述的实施方式中,也可以:在形成保护层4(工序(b))后、一连串的无电解镀工序(d)~(e)之前,经过研磨上述半导体基板的另一主面、即与形成了衬底电极层2侧相反一侧的主面、侧面,并且,在研磨后新露出的半导体基板的另一主面、侧面上形成氧化膜的工序。
这样的研磨例如通过具有金刚石磨石的磨床进行,据此,使半导体基板的另一主面、侧面平坦。这时,例如在研磨半导体基板1的另一主面时,相对于半导体基板1的厚度625μm左右被研磨的厚度为275μm左右,使研磨后的半导体基板厚度为350μm左右。
另外,氧化膜的形成,是以在研磨后经纯水清洗及吹风干燥的方式而进行,据此,可在半导体基板的另一主面、侧面形成膜厚大致均匀的氧化膜(例如在为Si制的半导体基板的情况下,为SiO2膜)。
经过该工序,可使基板1的另一主面、侧面形成良好的状态。在各种工序中将半导体基板放置在制造装置的金属制工作台上时、利用金属制的机械臂在制造装置之间移动半导体基板时,有时工作台、机械臂的材料金属片会附着在半导体基板的另一主面、侧面,或产生划痕导致其内部材料从半导体基板表面露出。即使在这种情况下,通过进行上述的研磨也可除去金属片或划痕。另外,之后形成的氧化膜,由于作为无电解镀时的抗镀剂发挥掩模的作用,所以可防止研磨后的半导体基板基材(例如Si)在锌酸盐液、镀液中露出。
而且,通过防止镀膜材料向该金属片等中析出,可使镀膜集中在本身成为镀膜対象的衬底电极层上表面。从而,能够有效地抑制在衬底电极层上表面长时间析出镀膜材料及产生称为瘤的突起物。据此,在衬底电极层上表面在规定的时间内稳定地形成所需的表面电极层。尤其,在金属片或划痕的尺寸比无电解镀形成的表面电极层的俯视状态下的尺寸大时,该效果明显。例如,在由无电解镀形成的表面电极层在俯视状态下的直径为50μm左右、金属片或划痕在俯视状态下的直径非常大、为200μm以上时,该效果明显。
并且,根据使氧化膜发挥掩模的功能,在研磨后,无电解镀工序前,在半导体基板的另一主面、侧面可省略干膜、光抗蚀剂、或镀膜治具等新的掩模处理,能够提高半导体元件的生产性。
(功能元件装配结构体)
下面,以安装上述的半导体元件的半导体元件装配结构体为例对本发明的功能元件装配结构体进行说明。
该半导体元件装配结构体,如图4所示主要由上述的半导体元件和安装半导体元件的基体6构成。在基体6的上表面具有电路图形7及设在电路图形7的规定区域的焊盘部8。而且,该焊盘部8与半导体元件的表面电极层3可以通过钎料层9进行连接。或者也可以焊盘部8与形成在表面电极层3上的金(Au)层通过钎料层9进行连接。并且,也可以直接连接表面电极层3与焊盘部8。另外,也有时在装配半导体元件后,在半导体元件与基体6之间填充密封树脂10。
半导体元件装配结构体的基体6在其内部、上表面形成有由铝、金、铜等金属材料构成的电路图形7、过孔导体等,还安装有各种电子部件或其他功能元件。在该基体6上形成的电路图形7是通过将例如金、铝、铜等金属布线加工成规定图形而形成。
基体6的材料可为绝缘体材料或成为半导体元件搭載区域的一主面被氧化了的金属材料等,能够根据用途、功能适当选择。例如在半导体元件为热敏头控制用半导体元件的情况下,作为基体6可采用陶瓷制的热敏头基板或玻璃环氧树脂制的电路基板。
形成在基体6一主面上的电路图形7例如由铝(Al)、铜(Cu)、金(Au)等导电体构成,只要至少在基体6一主面上具有后述的焊盘部8的形成区域即可。另外,电路图形7根据需要有时设到另一主面或与形成在基体6内部的过孔导体连接。这样的电路图形7可通过以往公知的光刻技术或厚膜印刷技术来形成。
在电路图形7的局部上表面形成的焊盘部8可与上述的半导体元件的表面电极层3相同地通过无电解镀法形成。
另一方面,例如通过以往公知的印刷法涂敷钎焊膏,再将其加热熔融,而在半导体元件的表面电极层3上形成钎料层9。另外,可采用电解镀技术或无电解镀技术在表面电极层3上形成金层。作为这时的金镀液可由亚硫酸化合物构成或使用含有金、还原剂、稳定剂、缓冲剂等的无电解镀液。
然后,为了将半导体元件装配在基体6上,首先使基体6的焊盘部8 形成主面与半导体元件的表面电极层3形成面相对置,然后配置表面电极层3使其位于基体6的焊盘部8上。接着,将表面电极层3抵接在焊盘部8上,然后,加热表面电极层3使其熔融覆盖在焊盘部8上而接合。该接合是例如通过电热炉、超音波或激光照射等以往公知的方法使表面电极层3或钎料层9等与焊盘部8接合的金属层加热熔融而进行的。
最后,通过向基体6与半导体元件之间填充密封树脂10,而包覆该接合部。该密封树脂10可采用例如环氧树脂等以往公知的树脂,不过由于需要向由基体与半导体元件的保护层4形成的10μm~100μm左右狭窄的间隙填充,所以设定为较低的粘性。
此外,本发明不局限于上述实施方式,在不脱离本发明要旨范围内是可以进行各种变更改良的。例如,在上述实施例中也可以在形成表面电极层后、形成较薄的金(Au)层、再在其上形成钎料层。通过形成该金层,能够抑制表面电极层材料的镍表面在钎料层形成之前的过程中被氧化腐蚀。另外,也可以采用使表面电极层与焊盘部相对置、将各向异性导电膜夹在两者的间隙中进行热压接,从而实现导通的方法(未图示)。
在这种情况下,即使因半导体基板1与基体6的热膨胀系数差产生的热应力等加在半导体基板1与衬底电极层2之间、衬底电极层2与表面电极层3之间、且电路图形7与焊盘部8之间时各个部位之间也不容易产生剥离。另外,即使外加热应力以外的某种不需要的力也能起到相同的效果。
并且,在上述的实施方式中对作为功能元件采用半导体元件的情况进行了说明,但除了半导体元件之外例如也可为在压电基板上形成有电极层的SAW元件。
【实施例1】
在本实施例中关于贯通孔相对于贯通孔及孔部的总和的比例、与衬底电极层-表面电极层之间的接合强度的关联关系进行了试验。
1.试样制作
首先作为用于进行上述试验的半导体元件制作了试样No.1~No.6。
试样No.1通过现有例记载的制造方法制造,其他试样通过本发明的制造方法制造。
在试样No.2~No.6中,按照本发明的制造方法的工序(c)进行干蚀刻,使各试样的该蚀刻时间不同。各试样No.2~No.6的蚀刻时间如下:试样No.2约为1min、试样No.3约为5min、试样No.4约为10min、试样No.5约为20min、试样No.6约为30min。另一方面,试样No.2~No.6中共同的干蚀刻的各个条件为:实现的真空度为0.2Pa、气体为氢气(纯度:99.99%)、气体流量为100ml/min、气体压力为20Pa、RF功率为300W。
2.孔部(贯通孔)的计数方法
(1)首先,利用集束离子束加工观察装置(Focused Ion Beam System)以各试样No.1~No.6分别切下5处的方式切取试样No.1~No.6的位于表面电极层正下方的衬底电极层的剖面。该切取部宽度约为20μm、深度约为5μm。
(2)其次,用扫描式电子显微镜(加速电压为15.00kV、拍摄倍率为10000倍)拍摄该切取部的任意位置的图像,得到宽度约为10μm的剖面照片。
(3)再次,在该剖面照片中,数出形成在衬底电极层上的孔部及贯通孔的个数,进而计算出贯通孔/(孔部+贯通孔)。
3.共负强度试验
为了评价试样No.1~No.6的衬底电极层与表面电极层的接合强度,在表面电极层上形成大致球形的钎料凸起9,实施带有该钎料凸起9的状態下的共负强度试验。
该共负强度试验是采用图7所示的共负强度测定装置(RHESCA(株)制PTR-1000)M进行的。共负强度测定装置M具有球共负传感器21及共负刀具22,它们被可上下移动的保持着。接合了钎料凸起9的试样No.1~No.6被配置在工作台23上,该工作台23可以沿水平方向移动。
首先,如图8所示,将在表面电极层3上搭载了钎料凸起9的试样No.1~No.6载置在工作台23上。本实施例中钎料凸起9的直径尺寸为 40μm~100μm,保护层4的开口直径尺寸为40μm~100μm。
接着,在使共负刀具22下降到与保护层4表面接触之前的过程中,如果测定器识别到半导体元件表面的位置,则使共负刀具22上升预设距离(约10μm)。
然后,以速度25μm/sec使工作台23沿水平方向移动,并以使共负刀具22从横向推压钎料凸起9的方式通过接合部上方。
据此,在各钎料凸起使衬底电极层2与表面电极层3之间产生剥离,测定表面电极层3从衬底电极层2上剥离下来的俯视状态下的面积、即因剥离而新露出的衬底电极层2在俯视状态下的面积。进而,相除算出每个钎料凸起的剥离面积率(俯视状态下新露出的衬底电极层2面积/俯视状态下剥离前的表面电极层面积)。
此外,本共负强度试验是在试样No.1~No.6上分别对100个钎料凸起进行的。
4.结果
关于贯通孔相对于贯通孔及孔部的总和的比例、衬底电极层与表面电极层的接合强度的关联关系汇总在表1中。
【表1】
资料No. | 1 | 2 | 3 | 4 | 5 | 6 |
贯通孔的个数/(孔部的个数 +贯通孔的个数) | 25/25 | 20/23 | 10/21 | 4/17 | 1/12 | 0/13 |
26/26 | 21/25 | 10/19 | 5/18 | 1/14 | 0/10 | |
23/23 | 19/22 | 11/19 | 4/18 | 1/13 | 0/12 | |
25/25 | 20/22 | 10/22 | 5/17 | 2/15 | 0/11 | |
24/24 | 18/23 | 10/20 | 4/16 | 1/12 | 0/12 | |
(贯通孔/孔部+贯通孔)的平均值 | 100% | 85.2% | 50.5% | 25.6% | 9.1% | 0% |
共负强度试验的评价结果 | × | △ | △ | ○ | ◎ | ◎ |
这里,关于各试样No.1~No.6中分别具有的100个钎料凸起按以下的方式进行标记,即,表面电极层3的剥离面积率为50%以上的钎料凸起在90个以上时标记为“×”、25%以上且不足50%的钎料凸起在90个以上时标记为“△”、1%以上且不足25%的钎料凸起在90个以上时标记为“○”、完全不产生的钎料凸起在90个以上时标记为“◎”。
根据该实施例可知,工序(C)中的蚀刻时间越长、贯通孔相对贯通孔与孔部的总和所占的比例越小、反之孔部所占的比例越大。另外,还可知,若贯通孔减少、孔部增加,则越不容易在衬底电极层与表面电极层之间产生剥离。
Claims (24)
1.一种功能元件,具有:基板、形成在该基板一主面上的衬底电极层、按照使所述衬底电极层的局部露出的方式而形成的保护层和在从该保护层露出的部分的所述衬底电极层形成的表面电极层,其特征在于:
所述衬底电极层与所述表面电极层的界面区域的所述衬底电极层的上表面比所述衬底电极层与所述保护层的界面区域的所述衬底电极层的上表面低,在所述衬底电极层内形成有从所述衬底电极层与所述表面电极层的界面区域沿所述衬底电极层厚度方向延伸的多个孔部,并且,所述多个孔部由贯通所述衬底电极层的孔部和没有贯通所述衬底电极层的孔部组成,从而所述孔部的平均深度比所述衬底电极层的厚度浅。
2.如权利要求1所述的功能元件,其特征在于:所述衬底电极层的厚度为0.5μm~2.0μm。
3.如权利要求1所述的功能元件,其特征在于:所述多个孔部以在俯视状态下1~20个/μm2的密度形成于所述衬底电极层。
4.如权利要求1所述的功能元件,其特征在于:所述孔部的深度比所述衬底电极层的厚度浅。
5.如权利要求1所述的功能元件,其特征在于:所述孔部内填充有所述表面电极层的一部分。
6.如权利要求1所述的功能元件,其特征在于:在所述衬底电极层上覆盖着包围在所述表面电极层周围的保护层,所述表面电极层的一部分填充到凹部中,该凹部在所述保护层与衬底电极层的界面区域沿平面方向延伸。
7.如权利要求1所述的功能元件,其特征在于:所述表面电极层上形成有钎料层。
8.如权利要求1所述的功能元件,其特征在于:在所述表面电极层上形成有金层。
9.如权利要求1所述的功能元件,其特征在于:在所述衬底电极层上覆盖着包围在所述表面电极层周围的保护层,所述衬底电极层与所述表面电极层的界面区域的该衬底电极层的上表面,比所述衬底电极层与所述保护层的界面区域的该衬底电极层的上表面低5nm~50nm。
10.如权利要求1所述的功能元件,其特征在于:所述孔部的延伸方向具有弯曲部。
11.如权利要求1所述的功能元件,其特征在于:
所述衬底电极层由从Al、Al-Cu、Al-Si、Al-Si-Cu所组成的组中选择出来的至少一种金属材料形成。
12.如权利要求1所述的功能元件,其特征在于:
所述表面电极层由镍形成。
13.如权利要求6所述的功能元件,其特征在于:
所述保护层由电绝缘材料形成。
14.如权利要求13所述的功能元件,其特征在于:
所述电绝缘材料是从氮化硅、氧化硅以及聚酰亚胺所组成的组中选择出来的至少一种。
15.一种功能元件装配结构体,其特征在于,包括:具有电路布线的基体、形成在所述基体一主面上的焊盘部和装配在所述基体上的权利要求1~14中任一项所述的功能元件,且所述表面电极层与所述焊盘部电连接。
16.一种功能元件的制造方法,其特征在于,包括:
在基板一主面上形成衬底电极层的第1工序;
形成保护层且使所述衬底电极层的局部露出的第2工序;
通过干蚀刻除去在所述衬底电极层的露出部形成的氧化膜,在所述露出部使所述衬底电极层的整个表面露出的第3工序;
通过将所述基板浸渍在锌酸盐液中,而在所述露出部中的所述衬底电极层形成由贯通该衬底电极层的孔部和没有贯通所述衬底电极层的孔部组成的多个孔部的第4工序;
通过将所述基板浸渍在无电解镀液中,从而在所述衬底电极层上形成表面电极层的第5工序。
17.如权利要求16所述的功能元件的制造方法,其特征在于:在所述第4工序中,以在俯视状态下1~20个/μm2的密度将所述多个孔部形成于所述衬底电极层。
18.如权利要求16所述的功能元件的制造方法,其特征在于:在所述干蚀刻之前还进行湿蚀刻。
19.如权利要求16所述的功能元件的制造方法,其特征在于:使经过所述第3工序进入所述第4工序之前的所述基板与空气中的氧接触,而在所述衬底电极层的露出部形成自然氧化膜。
20.如权利要求16所述的功能元件的制造方法,其特征在于:所述基板是半导体基板,还包括:对所述第3工序前的所述半导体基板的另一主面进行研磨且在研磨后的该另一主面上形成氧化膜的工序。
21.如权利要求16所述的功能元件的制造方法,其特征在于:
所述衬底电极层由从Al、Al-Cu、Al-Si、Al-Si-Cu所组成的组中选择出来的至少一种金属材料形成。
22.如权利要求16所述的功能元件的制造方法,其特征在于:
所述表面电极层由镍形成。
23.如权利要求16所述的功能元件的制造方法,其特征在于:
所述保护层由电绝缘材料形成。
24.如权利要求23所述的功能元件的制造方法,其特征在于:
所述电绝缘材料是从氮化硅、氧化硅以及聚酰亚胺所组成的组中选择出来的至少一种。
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US7727781B2 (en) * | 2008-07-22 | 2010-06-01 | Agere Systems Inc. | Manufacture of devices including solder bumps |
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US20120248599A1 (en) * | 2011-03-28 | 2012-10-04 | Ring Matthew A | Reliable solder bump coupling within a chip scale package |
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US8796049B2 (en) * | 2012-07-30 | 2014-08-05 | International Business Machines Corporation | Underfill adhesion measurements at a microscopic scale |
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US9331033B1 (en) * | 2014-12-23 | 2016-05-03 | Sunasic Technologies Inc. | Method for forming stacked metal contact in electrical communication with aluminum wiring in semiconductor wafer of integrated circuit |
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