CN1976004A - 用在栓塞表面区域的表面结构 - Google Patents

用在栓塞表面区域的表面结构 Download PDF

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CN1976004A
CN1976004A CNA2006101630935A CN200610163093A CN1976004A CN 1976004 A CN1976004 A CN 1976004A CN A2006101630935 A CNA2006101630935 A CN A2006101630935A CN 200610163093 A CN200610163093 A CN 200610163093A CN 1976004 A CN1976004 A CN 1976004A
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CN100463137C (zh
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陈士弘
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Macronix International Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
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    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe

Abstract

一半导体组件中的一个包括有一栓塞表面的表面结构，可通过移除材料以生成具有至少一栓塞表面区域(典型地为钨或铜栓塞区域)其包括有一凹陷区域的一第一平面化表面而改善。一材料沉积于此第一平面化表面之上以及此凹陷区域的顶部内，以生成一材料层。此材料层接着被移除以生成一第二平坦化表面，而此材料则仍留在此凹陷区域的顶部内。为了形成一半导体相转换存储元件，一相转换元素形成于第二平面化表面的至少一个栓塞区域(做为一第一电极)以及一第二电极之间。

Description

用在栓塞表面区域的表面结构
相关申请参考
本申请于2005年12月2日申请美国临时性专利申请，该申请案的申请号为60/741,828，发明名称为“用于具有钨区域的表面结构改良方法”。
技术领域
本发明涉及一种用于改进半导体组件的一表面的表面结构的方法，还涉及一种改进半导体相转换存储元件的一表面的表面结构。
背景技术
钨通常沉积于介层窗、沟渠、以及其它在介电层中的孔洞，以在半导体组件中生成栓塞等其它结构。钨的沉积过程通常通过化学气相沉积过程来完成。随着结晶钨自各个方向填入孔洞中，通常会在此孔洞的中央之下生成窄缝。当使用钨以填满一高深宽比的孔洞时，例如填满介层窗以生成钨栓塞时，此窄缝的一部份通常无法闭合，而在此钨栓塞内形成一空洞。因此，在化学机械研磨(CMP)之后，钨结构所外露的区域(以下有时称为栓塞表面区域或栓塞区域、或钨区域或钨栓塞区域)，一般会具有外露的凹陷区域、沟槽、或其它在CMP过程之后所生成的凹陷区域。举例而言，当钨沉积以生成钨栓塞时，此钨栓塞可能具有内部空洞，然而此钨栓塞的顶端通常是密闭的。然而在CMP之后，钨栓塞的顶端可能被向下削减而露出此内部空洞，因而产生凹陷区域。此表面所产生的表面结构则较不佳而可能造成问题，例如在后续工艺步骤中与其上结构的电性接触不佳。
发明内容
本发明的第一目的在于提供一种改进半导体组件的表面的表面结构的方法，此表面包括栓塞区域，其通常为钨区域。此方法包括：从半导体组件移除材料，以生成具有栓塞区域的第一平面化表面。至少一个栓塞区域包括凹陷区域，此凹陷区域在平面化表面包括一顶部。一种材料沉积于此第一平面化表面之上，以生成材料层；此沉积步骤还包括将此材料沉积于凹陷区域的顶部之内。此材料层接着被移除以生成第二平面化表面，而至少一个栓塞区域的凹陷区域的顶部仍包含此材料。
本发明的第二目的在于提供一种改进半导体相转换存储元件的表面的表面结构，此表面包括有钨区域。此方法包括：通过在半导体组件上实施第一钨化学机械研磨程序，而从此半导体组件移除材料并生成具有钨区域的第一平面化表面，至少一个钨区域包括一凹陷区域，此凹陷区域于此平面化表面包括一顶部；沉积一种材料于第一平面化表面之上以生成一材料层；此沉积步骤还包括将此材料沉积于凹陷区域的顶部之内；通过进行第二化学机械研磨程序(CMP)以移除材料层，而生成第二平面化表面，而此至少一个钨区域的凹陷区域的顶部仍含有此材料；以及形成一个相转换元素于第二平面化表面的至少一个钨区域(做为第一电极)以及第二电极之间，以形成一个相转换存储元件，此相转换存储元件可用以生成一随机存取半导体内存。
以下详细说明本发明的结构与方法。本发明内容说明章节目的并非在于定义本发明。本发明由权利要求的范围所定义。本发明的实施例、特征、目的及优点等将可通过下列说明、权利要求范围及附图来得到充分了解。
附图说明
图1为一半导体组件的一部分的简化剖面图，其经过一第一传统CMP程序以生成一具有外露钨栓塞的第一平面化表面，并在此第一平面化表面生成外露的钨区域；
图2示出图1的结构经过一物质沉积于此第一平面化表面，以在此表面上生成一材料层并填入一钨栓塞的凹陷区域的至少顶部；
图3示出图2的结构经过一第二CMP程序而生成一第二平面化表面，其中此材料层被移除，而材料仍留在此凹陷区域的顶部之内，以改善平面化表面的表面结构；
图4示出本发明的一替代实施例，其类似于图1中的实施例，其中此半导体组件在第一平面化表面处包括了一钨CMP停止层；
图5类似于图2，示出沉积一材料于图4结构的第一平面化表面以及一钨栓塞的凹陷区域之内；
图6示出图5的结构经过一第CMP程序而移除此材料以及阻挡层，生成一类似于图3的结构；
图7示出图3的结构经过沉积相转换材料而生成一相转换存储元件；以及
图8-14为对应于图1-7的实施例的替代实施例。
附图标记说明
10        部分
12，14    钨栓塞
16        层间绝缘
18        第一平面化表面
20，22    外显钨区域
24        凹陷区域
26        材料
28        材料层
30        顶部
32        第二平面化表面
34        钨CMP停止层
38，40    相转换元素
42        间隔材料
44，46    第二电极
48        相转换存储元件
50        障碍层
具体实施方式
下面将参考特定实施例的结构和方法来叙述本发明。可以了解的是，本发明并不限定于此所揭露的特定实施例的结构和方法。本发明可利用其它特征、组件、方法、以及实施形式来实施。在各实施例中类似的元件将以共同的标号指明。
图1为为一半导体组件的一部分10，经过一适合研磨钨的第一现有化学机械研磨程序(CMP)之后的简化剖面图。半导体组件的一部分10在一层间绝缘16中具有钨栓塞12，14或其它钨结构，此层间绝缘包括如一层以上的二氧化硅、氮氧化硅、氮化硅、或其它材料。此第一CMP程序会生成一第一平面化表面18，其中钨栓塞12，14会在第一平面化表面外露其顶端而出现外显钨区域20，22(或称为栓塞区域或栓塞表面区域)。钨区域22具有一外露的凹陷区域24，其从第一平面化表面延伸进入栓塞14。凹陷区域24典型地为第一现有化学机械研磨(CMP)程序的结果。
图2为绘示图1中的结构经过一材料26沉积于第一平面化表面18之上，在表面18上形成一材料层28的结果。材料26也填入钨栓塞14的凹陷区域24的至少顶部30。材料26典型地为经由化学气相沉积(CVD)所沉积的氮化钛。也可使用其它如原子层沉积(ALD)或等离子体气相沉积(PVD)等工艺。亦可使用其它如氮化钽、硅、及二氧化硅等材料。虽然材料26较佳地为一金属，但在某些情况下非金属的材料也是适合的。
如下所述并参考图7，当图3的结构用以制造一相转换存储元件时，材料26较佳为氮化钛。以相转换为基础的记忆材料如硫属材料以及类似材料等，也可通过施加一幅度适用于集成电路的电流，而产生相转换。其大部分为非晶态的特征，其电阻高于大部分为结晶态，而此电阻的差异可轻易地被侦测以指定资料。这些性质引起了研究兴趣于使用可程序化电阻材料而形成非挥发性记忆电路，其可用以随机读取与写入。氮化钛可以提供与Ge2Sb2Te5(一般称为GST)以及其它相转换材料之间良好的电性接触，因此氮化钛在这些相转换存储元件中适用为材料26。
图3显示了图2的结构经过了一第二化学机械研磨(CMP)程序而生成一第二平面化表面32的结果，其中材料层28已经被移除。此第二CMP程序典型地比第一CMP程序温和。典型地，沿着第一平面化表面18的少量材料也在第二CMP程序中被移除。材料26保留在凹陷区域24的顶30之内，以改进第二平面化表面32的表面结构、有效地消除凹陷区域。
图4为绘示了类似图1的实施例的替代实施例。第一化学机械研磨(CMP)程序使得如钨栓塞14等钨结构的外露顶端平滑，并露出一定义第一平面化表面18的钨化学机械研磨(CMP)停止层34。停止层34可为氮化钛、氮化硅、或其它可做为一边缘停止层的材料。
图5类似于图2，绘示在第一平面化表面18上、以及钨栓塞14的凹陷区域24内沉积材料26的结果。图6显示图5的结构经过一第二化学机械研磨(CMP)程序而移除材料层28与阻挡层34以生成一类似于图3的结构。第二平面化表面32在第一平面化表面18之上具有一改进的表面结构，因为在凹陷区域24之中存在有材料26。如图4-6所示的具有阻挡层34的实施例的优点之一在于，在此工艺过程中层间绝缘16的损失会比图1-3所示的实施例来得少。
图7为绘示在图3的结构上沉积有相转换材料，以在额外的半导体工艺过程步骤之后形成相转换元素38，40。相转换元素38，40接触至钨区域20，22，并被间隔材料42所围绕。相转换元素38，40被捕捉于用做为第一电极的钨区域20，22与第二电极44，46之间。可选择在顶部30内的材料26以确保与相转换元素38，40的相转换材料之间的良好附着与接触。如上所述氮化钛可非常良好地附着到GST与其它相转换材料，因此特别适用于材料26。所产生的相转换存储元件48特别适合用以制造半导体随机存取内存。
图8-14绘示对应于图1-7的实施例的替代实施例。主要的差别在于，在栓塞12，14的侧壁上使用了障碍层50。障碍层50导电且由一种以上的材料或材料层所构成，例如氮化钛或氮化钽。
在上述说明中用到词汇如“之上”、“之下”、“顶”、“底”等。这些词汇仅用以协助了解本发明，而非用以限制本发明。
上述的说明中提到了使用钨。然而本发明可使用钨以外的其它导电材料。举例而言，当使用铜于双层镶嵌工艺过程中以生成层间连接铜栓塞、以及铜型栓塞区域时，也可使用本发明。
虽然本发明已参照较佳实施例来加以描述，但应该了解的是，本发明并未受限于其详细描述内容。替换方式及修改样式已于先前描述中所建议，并且其它替换方式及修改样式将为本领域技术人员所思及。特别是，根据本发明的结构与方法，所有具有实质上相同于本发明的构件结合而达成与本发明实质上相同结果者皆不脱离本发明的精神范畴。因此，所有这些替换方式及修改样式意欲落在本发明于随附权利要求范围及其均等物所界定的范畴之中。任何在前文中提及的专利申请案以及印刷文本，均列为本案的参考。

Claims (14)

1.一种用以改进一半导体组件的一表面的表面结构的方法，该表面包括栓塞区域，该方法包括：
从该半导体组件移除一第一材料以生成具有栓塞区域的一第一平面化表面，至少一个该栓塞区域包括一凹陷部分，该凹陷部分于该第一平面化表面包括一顶部部分；
沉积一材料于平面化表面之上，以生成一材料层；
该沉积步骤还包括沉积该材料于该凹陷部分的该顶部部分内；以及
移除该材料层以创造一第二平面化表面，该至少一个栓塞区域的该凹陷部分的该顶部部分内仍含有该材料。
2.根据权利要求1所述的方法，其特征在于，从该半导体组件移除一第一材料的该步骤以一钨化学机械研磨停止层所定义的该第一平面化表面所进行，同时一钨区域做为该栓塞区域。
3.根据权利要求2所述的方法，其特征在于，移除该材料层的该步骤移除该材料层以及该钨化学机械研磨停止层。
4.根据权利要求1所述的方法，其特征在于，该材料沉积步骤以一化学气相沉积氮化钛沉积步骤进行。
5.根据权利要求1所述的方法，其特征在于，从该半导体组件移除一第一材料的该步骤包括进行一第一钨化学机械研磨程序于该半导体组件之上，且该栓塞区域包括钨栓塞区域。
6.根据权利要求1所述的方法，其特征在于，移除该材料层的该步骤包括进行一第二化学机械研磨程序以移除该材料层。
7.根据权利要求1所述的方法，其特征在于，还包括形成一相转换元素介于作为一第一电极的该至少一个栓塞区域的该第二平面化表面与一第二电极之间，以形成一相转换存储元件。
8.根据权利要求1所述的方法，其特征在于，从该半导体组件移除一第一材料的该步骤在包括有钨栓塞区域的该栓塞区域进行。
9.根据权利要求1所述的方法，其特征在于，从该半导体组件移除一第一材料的该步骤在包括有铜栓塞区域的该栓塞区域进行。
10.根据权利要求1所述的方法，其特征在于，从该半导体组件移除一第一材料的该步骤在包括一栓塞于一绝缘层中的该半导体组件上进行。
11.根据权利要求10所述的方法，其特征在于，从该半导体组件移除一第一材料的该步骤以在该栓塞与该绝缘层间含有一障碍层的该半导体组件上进行。
12.根据权利要求11所述的方法，其特征在于，从该半导体组件移除一第一材料的该步骤以包含一导电材料的该障碍层进行。
13.一种用以改进一半导体相转换存储元件的一表面的表面结构的方法，该表面包括钨区域，该方法包括：
通过进行一第一钨化学机械研磨程序于一半导体组件上而从该半导体组件的表面移除一第一材料，以生成具有钨区域的一第一平面化表面，至少一个该钨区域包括一凹陷部分，该凹陷部分于该第一平面化表面包括一顶部部分；
沉积一材料于该第一平面化表面以生成一材料层；
此沉积步骤还包括沉积该材料于该凹陷部分的该顶部部分内；
通过进行一第二化学机械研磨程序而移除该材料层，以移除该材料层而生成一第二平面化表面，该至少一个钨区域的该凹陷区域的该顶部含有该材料；以及
形成一相转换元素介于作为一第一电极的该至少一个钨区域的该第二平面化表面与一第二电极之间，以形成一相转换存储元件。
14.根据权利要求13所述的方法，其特征在于，移除该第一材料的该步骤在有着于包含一钨栓塞的一绝缘层，与一障碍层介于该钨栓塞与该绝缘层之间的该半导体组件上进行。
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