CN1925120A - 晶穴朝下型芯片封装构造的制造方法及构造 - Google Patents
晶穴朝下型芯片封装构造的制造方法及构造 Download PDFInfo
- Publication number
- CN1925120A CN1925120A CNA2005100985061A CN200510098506A CN1925120A CN 1925120 A CN1925120 A CN 1925120A CN A2005100985061 A CNA2005100985061 A CN A2005100985061A CN 200510098506 A CN200510098506 A CN 200510098506A CN 1925120 A CN1925120 A CN 1925120A
- Authority
- CN
- China
- Prior art keywords
- those
- chip
- packaging structure
- active surface
- cake core
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 58
- 238000004519 manufacturing process Methods 0.000 title claims description 53
- 238000005538 encapsulation Methods 0.000 title description 15
- 238000004806 packaging method and process Methods 0.000 claims description 74
- 239000000758 substrate Substances 0.000 claims description 27
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 20
- 239000011889 copper foil Substances 0.000 claims description 19
- 239000000853 adhesive Substances 0.000 claims description 17
- 230000001070 adhesive effect Effects 0.000 claims description 17
- 239000011347 resin Substances 0.000 claims description 15
- 229920005989 resin Polymers 0.000 claims description 15
- 238000007789 sealing Methods 0.000 abstract description 9
- 238000005520 cutting process Methods 0.000 abstract description 6
- 239000003292 glue Substances 0.000 abstract description 3
- 230000008569 process Effects 0.000 abstract description 3
- 239000013078 crystal Substances 0.000 abstract 1
- 230000005611 electricity Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 7
- 238000013461 design Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000007639 printing Methods 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
本发明是有关于一种晶穴朝下型芯片封装构造的制造方法及构造。该晶穴朝下型芯片封装构造的制造方法,是先将复数个芯片设置在一散热片上,再贴设一如导线架或基板的内部电传导元件在该些芯片上,由该散热片与该内部电传导元件是能大致包覆该些芯片,但显露出该些芯片的焊垫,以供电性连接。并在经过设置外终端与封胶之后,并切割该散热片。故该散热片是作为芯片承载件与封胶形成载体,能将各式不同焊垫排列位置的芯片大量且低成本地封装成晶穴朝下型态。
Description
技术领域
本发明涉及一种芯片封装技术,特别是涉及一种可量产晶穴朝下型芯片封装构造的制造方法及构造。
背景技术
现有习知晶穴朝下型芯片封装构造(cavity-down chip package)是指一芯片载体(chip carrier)具有能容纳芯片的晶穴,在接合至一外部印刷电路板时,该晶穴是为朝向该位于下方的外部印刷电路板。通常晶穴朝下型芯片封装构造具有优良导热性与良好可靠度的优点,但仅能封装具有周边焊垫的特定芯片且封装成本较高。
在晶穴朝下型芯片封装制程中,一芯片是设置于一芯片载体(chipcarrier)的晶穴内,在打线连接时,芯片的整个主动面连同其焊垫是显露于该晶穴。通常该芯片载体是由一散热片与一电路基板所组成,并藉由复数个焊线电性连接该芯片载体的电路基板与该芯片的焊垫,再以一封胶体密封该芯片与该些焊线,通常在封装之前该芯片载体是已单体化,即一个芯片载体仅具有一晶穴而能容纳单一芯片,封装时必须另以一封装承载盒放置多个芯片载体,导致生产效率与定位效果较差。
请参阅图1A至图1E所示,是现有习知的晶穴朝下型芯片封装制程,如图1A所示,适用于晶穴朝下型芯片封装构造的芯片载体10是预先单体化形成,其是由一散热片11与一电路基板12所组成并具有一晶穴13。该电路基板12是预先粘贴在该散热片11上,以供制造单一个晶穴朝下型芯片封装构造。如图1B所示,之后,一芯片20是设置于该芯片载体10的该晶穴13内,其中该芯片20的一背面22是粘贴至该散热片11,而该芯片20的整个主动面21以及其位于该主动面21的复数个焊垫23是显露于该晶穴13。如图1C所示,之后,复数个焊线30是电性连接该芯片20的该些焊垫23至该电路基板12,目前在晶穴朝下型芯片封装制程中要求该些焊垫23必须位于该些芯片20的主动面21的周边(即周边焊垫),否则该些焊线30的长度与弧高均会过长与过高,导致较差的电性传输效率与封胶困难。如图1D所示,之后,一封胶体40是形成于该晶穴13,以密封保护该芯片20与该些焊线30。如图1E所示,最后,再将复数个焊球50设置在该电路基板12上,以得到单一个晶穴朝下型芯片封装构造。因此,在现有习知晶穴朝下型芯片封装构造的制造方法中,不但生产效率较差且成本高,并且仅能封装周边焊垫(peripheral pad)的特定芯片20,无法大量运用在记忆体芯片的封装。
由此可见,上述现有的晶穴朝下型芯片封装构造的制造方法及构造在产品结构、制造方法及使用上,显然仍存在有不便与缺陷,而亟待加以进一步改进。为了解决晶穴朝下型芯片封装构造的制造方法及构造存在的问题,相关厂商莫不费尽心思来谋求解决之道,但长久以来一直未见适用的设计被发展完成,而一般晶穴朝下型芯片封装构造的制造方法及构造又没有适切的制造方法及结构能够解决上述问题,此显然是相关业者急欲解决的问题。因此如何能创设一种新的晶穴朝下型芯片封装构造的制造方法及构造,便成了当前业界极需改进的目标。
有鉴于上述现有的晶穴朝下型芯片封装构造的制造方法及构造存在的缺陷,本发明人基于从事此类产品设计制造多年丰富的实务经验及专业知识,并配合学理的运用,积极加以研究创新,以期创设一种新的晶穴朝下型芯片封装构造的制造方法及构造,能够改进一般现有的晶穴朝下型芯片封装构造的制造方法及构造,使其更具有实用性。经过不断的研究、设计,并经反复试作及改进后,终于创设出确具实用价值的本发明。
发明内容
本发明的目的在于,提供一种新的晶穴朝下型芯片封装构造的制造方法,所要解决的技术问题是先将复数个芯片设置于一散热片,再将一例如导线架或是基板的内部电传导元件设置在该些芯片的主动面上,以利电性连接该些芯片与该内部电传导元件;并经过设置外终端与封胶之后,切割该散热片可大量生产与低成本地制造出复数个晶穴朝下型芯片封装构造,并且,具有能将各式不同焊垫排列位置的芯片加以封装成晶穴朝下型态的功效,从而更加适于实用。
本发明的另一目的在于,提供一种新的晶穴朝下型芯片封装构造的制造方法及构造,所要解决的技术问题是以一内部电传导元件设置于芯片的主动面,使其封装尺寸能小于现有习知基板设置于散热片的晶穴朝下型芯片封装构造,从而更加适于实用。
本发明的再一目的在于,提供一种晶穴朝下型芯片封装构造的制造方法及构造,所要解决的技术问题是使导线架的引脚是贴设在该些芯片的主动面上,以利形成较短长度的焊线,并且该内部电传导元件具有复数个支撑柱,以供结合至散热片,有利外终端的设置,可以低成本制造晶穴朝下型态芯片封装构造,从而更加适于实用。
本发明的还一目的在于,提供一种晶穴朝下型芯片封装构造的制造方法及构造,所要解决的技术问题是使散热片是为一背胶铜箔(Resin CoatedCopper foil,RCC),能低成本地大量取得,在晶穴朝下型芯片封装制程中,该背胶铜箔的一树脂层是粘接复数个芯片的背面,有效降低封装成本,从而更加适于实用,且具有产业上的利用价值。
本发明的目的及解决其技术问题是采用以下技术方案来实现的。依据本发明提出的一种晶穴朝下型芯片封装构造的制造方法,其包括以下步骤:提供一散热片;设置复数个芯片在该散热片上,每一芯片具有一主动面以及形成在该主动面的复数个焊垫;在设置该些芯片之后,设置一内部电传导元件在该些芯片的主动面上;电性连接该些芯片的该些焊垫至该内部电传导元件;设置复数个外终端在该内部电传导元件上;形成一封胶体在该散热片上,并使该封胶体覆盖该些芯片的显露主动面;以及切割该散热片,以形成复数个晶穴朝下型芯片封装构造。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的晶穴朝下型芯片封装构造的制造方法,其中所述的该些焊垫是排列于对应芯片的主动面的一中央位置。
前述的晶穴朝下型芯片封装构造的制造方法,其中所述的内部电传导元件是为一无外导脚的LOC导线架,其具有复数个可供贴设在该些芯片的主动面上的引脚,该些芯片的该些焊垫是藉由复数个焊线电性连接至该些引脚。
前述的晶穴朝下型芯片封装构造的制造方法,其中所述的内部电传导元件具有复数个支撑柱,以供结合至该散热片。
前述的晶穴朝下型芯片封装构造的制造方法,其中所述的内部电传导元件是为一具有槽孔的电路基板,当该电路基板设置在该些芯片的主动面上时,该些槽孔是显露出该些芯片的焊垫,藉由复数个焊线电性连接该些焊垫至该电路基板。
前述的晶穴朝下型芯片封装构造的制造方法,其中所述的散热片是为一背胶铜箔(Resin Coated Copper foil,RCC),该背胶铜箔的一树脂层是可粘接该些芯片的背面。
本发明的目的及解决其技术问题还采用以下的技术方案来实现。依据本发明提出的一种晶穴朝下型芯片封装构造,其包括:一散热片;一芯片,其是设置在该散热片上,该芯片具有一主动面以及形成在该主动面的复数个焊垫;一内部电传导元件,其是设置在该芯片的该主动面上并电性连接至该芯片的该些焊垫;复数个外终端,其是设置在该内部电传导元件上;以及一封胶体,其是形成于该散热片上并覆盖该芯片的显露主动面。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的晶穴朝下型芯片封装构造,其中所述的该些焊垫是排列于该主动面的一中央位置。
前述的晶穴朝下型芯片封装构造,其中所述的内部电传导元件是为一无外导脚的LOC导线架,其具有复数个可供贴设在该芯片的主动面上的引脚,该些芯片的该些焊垫是藉由复数个焊线电性连接至该些引脚。
前述的晶穴朝下型芯片封装构造,其中所述的内部电传导元件具有复数个支撑柱,以供结合至该散热片。
前述的晶穴朝下型芯片封装构造,其中所述的该些外终端是对准于该些支撑柱。
前述的晶穴朝下型芯片封装构造,其中所述的内部电传导元件是为一具有槽孔的电路基板,当该电路基板设置在该芯片的主动面上时,该槽孔是显露出该芯片的焊垫,藉由复数个焊线电性连接该些焊垫至该电路基板。
前述的晶穴朝下型芯片封装构造,其中所述的散热片是为一背胶铜箔(Resin Coated Copper foil,RCC),该背胶铜箔的一树脂层是可粘接该芯片的一背面。
经由上述可知,本发明是有关于一种晶穴朝下型芯片封装构造的制造方法及构造。该晶穴朝下型芯片封装构造的制造方法,是先将复数个芯片设置在一散热片上,再贴设一如导线架或基板的内部电传导元件在该些芯片上,由该散热片与该内部电传导元件是能大致包覆该些芯片,但显露出该些芯片的焊垫,以供电性连接。并在经过设置外终端与封胶之后,并切割该散热片。故该散热片是作为芯片承载件与封胶形成载体,能将各式不同焊垫排列位置的芯片大量且低成本地封装成晶穴朝下型态。
借由上述技术方案,本发明晶穴朝下型芯片封装构造的制造方法及构造至少具有下列优点:
本发明的晶穴朝下型芯片封装构造的制造方法,先将复数个芯片设置于一散热片,再将一例如导线架或是基板的内部电传导元件设置在该些芯片的主动面上,以利电性连接该些芯片与该内部电传导元件;并经过设置外终端与封胶之后,切割该散热片可大量生产与低成本地制造出复数个晶穴朝下型芯片封装构造,并且,具有能将各式不同焊垫排列位置的芯片加以封装成晶穴朝下型态的功效。特别适用于将中央焊垫的高频记忆体芯片(例如DDR2记忆体)以量产方式封装成“晶穴朝下”型态。
本发明晶穴朝下型芯片封装构造的制造方法以及其封装构造,利用一适用于晶穴朝下型封装的散热片作为芯片承载件与封胶载体,以供设置芯片与形成封胶体,并以一内部电传导元件设置于芯片的主动面,其封装尺寸能小于现有习知基板设置于散热片的晶穴朝下型芯片封装构造。
本发明晶穴朝下型芯片封装构造的制造方法以及其封装构造,其中一种可运用于晶穴朝下封装的内部电传导元件是为一无外导脚的LOC(Lead-On-Chip,芯片上引脚)导线架,该导线架的引脚是贴设在该些芯片的主动面上,以利形成较短长度的焊线。并且,该内部电传导元件具有复数个支撑柱,以供结合至该散热片,有利外终端的设置,以低成本制造晶穴朝下型态芯片封装构造。
本发明晶穴朝下型芯片封装构造的制造方法以及其封装构造,利用一适用于晶穴朝下型封装的散热片是为一背胶铜箔(Resin Coated Copperfoil,RCC),能低成本地大量取得,在晶穴朝下型芯片封装制程中,该背胶铜箔的一树脂层是粘接复数个芯片的背面,有效降低封装成本。
综上所述,本发明特殊的晶穴朝下型芯片封装构造的制造方法及构造,具有上述诸多的优点及实用价值,并在同类制造方法及产品中未见有类似的方法及结构设计公开发表或使用而确属创新,其不论在制造方法、产品结构或功能上皆有较大的改进,在技术上有较大的进步,并产生了好用及实用的效果,且较现有的晶穴朝下型芯片封装构造的制造方法及构造具有增进的多项功效,从而更加适于实用,而具有产业的广泛利用价值,诚为一新颖、进步、实用的新设计。
上述说明仅是本发明技术方案的概述,为了能够更清楚了解本发明的技术手段,而可依照说明书的内容予以实施,并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂,以下特举较佳实施例,并配合附图,详细说明如下。
附图说明
图1A至图1E是现有习知一个晶穴朝下型芯片封装构造在制造过程中的截面示意图。
图2A至图2F是本发明的一具体实施例的复数个晶穴朝下型芯片封装构造在可量产制造过程中的截面示意图。
图3是本发明的一具体实施例的所制得的晶穴朝下型芯片封装构造的截面示意图。
10:芯片载体 11:散热片
12:电路基板 13:晶穴
20:芯片 21:主动面
22:背面 23:焊垫
30:焊线 40:封胶体
50:焊球 100:晶穴朝下型芯片封装构造
110:散热片 111:树脂层
120:芯片 121:主动面
122:背面 123:焊垫
130:内部电传导元件 131:引脚
132:支撑 133:贴片
140:焊线 150:外终端
151:焊料 160:封胶体
210:锯切工具
具体实施方式
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效,以下结合附图及较佳实施例,对依据本发明提出的晶穴朝下型芯片封装构造的制造方法及构造其具体实施方式、制造方法、步骤、结构、特征,详细说明如后。
请配合参阅图2A至图2F所示,一种晶穴朝下型芯片封装构造的制造方法是具体说明如后。如图2A所示,首先,提供一散热片110。在本实施例中,该散热片110是为一种可大量取得且低成本的背胶铜箔(ResinCoated Copper foil,RCC),该背胶铜箔包括有一树脂层111,其具有半固化的粘性,以能在后续封装制程中粘接芯片与内部电传导元件。
本发明并不需要将该散热片110预先组合成具有晶穴的芯片载体,如图2B所示,复数个芯片120,是以加压粘接方式设置在该散热片110上,每一芯片120,具有一主动面121、一背面122以及复数个形成在该主动面121的焊垫123。可利用上述背胶铜箔的树脂层111直接粘接该些芯片120的背面122,或是使用其它的粘晶材料进行粘晶操作。在本实施例中,该些焊垫123,是排列于对应芯片120的主动面121的一中央位置,例如中央单排或双排排列,并且不受局限的,该些焊垫123亦可排列于对应主动面121的其它任意位置。特别适用的是,该些芯片120是可为高频记忆体芯片,例如频率高于500MHz的记忆体芯片,其焊垫可为中央排列。
如图2C所示,之后,在设置该些芯片120之后,设置一内部电传导元件130在该些芯片120的主动面121上,以部分覆盖该些芯片120的主动面121,但仍显露该些芯片120的焊垫123。该内部电传导元件130,是可为一导线架或一各式基板,其中以选用无外导脚的LOC导线架具有较低的成本。在一具体实施例中,该内部电传导元件130,是可为一种无外导脚的LOC导线架,其具有复数个引脚131,利用至少一粘性胶片133将该些引脚131贴设在该些芯片120的主动面121上;较佳的,该内部电传导元件130是另具有复数个支撑柱132,可运用导线架的半蚀刻技术或是外加元件的接合方式形成,以供支撑并结合至该散热片110。在本实施例中,该散热片110上的树脂层111是粘接该些支撑柱132。此外,在另一具体实施例中,该内部电传导元件130,是可为一种具有槽孔的电路基板(图中未示),当该电路基板的内部电传导元件130设置在该些芯片120的主动面121上时,该些槽孔是显露出该些芯片120的焊垫123,以利内部电性连接。
如图2D所示,之后,藉由打线形成的复数个焊线140电性连接该些芯片120的该些焊垫123至该内部电传导元件130。如图2E所示,之后,设置复数个外终端150在该内部电传导元件130上。该些外终端150是可对准于该些支撑柱132,由该些支撑柱132提供足够可设置该些外终端150的支撑力。通常该些外终端150是为金属球或凸块;在本实施例中,该些外终端150是为例如铜球或是锡球等的金属球,并以焊料151接合至该内部电传导元件130。较佳的,该些外终端150的设置高度是高于该些焊线140的弧高,以利该些外终端150导接至一外部印刷电路板(图中未示)。
并且,如图2F所示,可利用液态点涂或是印刷方式形成一封胶体160在该散热片110上,并且该封胶体160除了可覆盖该些主动面121的显露部分并包覆该些焊线140,该封胶体160是可沿着该些引脚131的间隔往下流布至在该内部电传导元件130与该散热片110间的空隙并可覆盖该些芯片120的侧面。此外,该封胶体160的形成步骤除了可实施在该些外终端150的设置步骤之后,亦可实施在该些外终端150的设置步骤之前。当该封胶体160是形成在该该些外终端150的设置步骤之前,则可运用点涂、压模、印刷等更多方法形成该封胶体160。
最后,如图2F所示,可利用一锯切工具210切割该散热片110,以形成复数个如图3所示的晶穴朝下型芯片封装构造100。
请参阅图3所示,依本发明所制造得到的晶穴朝下型芯片封装构造100具有晶穴朝下型态,达到良好导热性与电传导路径,此外,更能低成本地大量生产,具有能将各式不同焊垫排列位置的芯片加以封装成晶穴朝下型态的功效,特别适用于“晶穴朝下型”封装高频记忆体芯片或是其它大宗可规格化量产的芯片。
以上所述,仅是本发明的较佳实施例而已,并非对本发明作任何形式上的限制,虽然本发明已以较佳实施例揭露如上,然而并非用以限定本发明,任何熟悉本专业的技术人员,在不脱离本发明技术方案范围内,当可利用上述揭示的方法及技术内容作出些许的更动或修饰为等同变化的等效实施例,但凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰,均仍属于本发明技术方案的范围内。
Claims (13)
1、一种晶穴朝下型芯片封装构造的制造方法,其特征在于其包括以下步骤:
提供一散热片;
设置复数个芯片在该散热片上,每一芯片具有一主动面以及形成在该主动面的复数个焊垫;
在设置该些芯片之后,设置一内部电传导元件在该些芯片的主动面上;
电性连接该些芯片的该些焊垫至该内部电传导元件;
设置复数个外终端在该内部电传导元件上;
形成一封胶体在该散热片上,并使该封胶体覆盖该些芯片的显露主动面;以及
切割该散热片,以形成复数个晶穴朝下型芯片封装构造。
2、根据权利要求1所述的晶穴朝下型芯片封装构造的制造方法,其特征在于其中所述的该些焊垫是排列于对应芯片的主动面的一中央位置。
3、根据权利要求1所述的晶穴朝下型芯片封装构造的制造方法,其特征在于其中所述的内部电传导元件是为一无外导脚的LOC导线架,其具有复数个可供贴设在该些芯片的主动面上的引脚,该些芯片的该些焊垫是藉由复数个焊线电性连接至该些引脚。
4、根据权利要求1或3所述的晶穴朝下型芯片封装构造的制造方法,其特征在于其中所述的内部电传导元件具有复数个支撑柱,以供结合至该散热片。
5、根据权利要求1所述的晶穴朝下型芯片封装构造的制造方法,其特征在于其中所述的内部电传导元件是为一具有槽孔的电路基板,当该电路基板设置在该些芯片的主动面上时,该些槽孔是显露出该些芯片的焊垫,藉由复数个焊线电性连接该些焊垫至该电路基板。
6、根据权利要求1所述的晶穴朝下型芯片封装构造的制造方法,其特征在于其中所述的散热片是为一背胶铜箔,该背胶铜箔的一树脂层是可粘接该些芯片的背面。
7、一种晶穴朝下型芯片封装构造,其特征在于其包括:
一散热片;
一芯片,其是设置在该散热片上,该芯片具有一主动面以及形成在该主动面的复数个焊垫;
一内部电传导元件,其是设置在该芯片的该主动面上并电性连接至该芯片的该些焊垫;
复数个外终端,其是设置在该内部电传导元件上;以及
一封胶体,其是形成于该散热片上并覆盖该芯片的显露主动面。
8、根据权利要求7所述的晶穴朝下型芯片封装构造,其特征在于其中所述的该些焊垫是排列于该主动面的一中央位置。
9、根据权利要求7所述的晶穴朝下型芯片封装构造,其特征在于其中所述的内部电传导元件是为一无外导脚的LOC导线架,其具有复数个可供贴设在该芯片的主动面上的引脚,该些芯片的该些焊垫是藉由复数个焊线电性连接至该些引脚。
10、根据权利要求7或9所述的晶穴朝下型芯片封装构造,其特征在于其中所述的内部电传导元件具有复数个支撑柱,以供结合至该散热片。
11、根据权利要求7所述的晶穴朝下型芯片封装构造,其特征在于其中所述的该些外终端是对准于该些支撑柱。
12、根据权利要求7所述的晶穴朝下型芯片封装构造,其特征在于其中所述的内部电传导元件是为一具有槽孔的电路基板,当该电路基板设置在该芯片的主动面上时,该槽孔是显露出该芯片的焊垫,藉由复数个焊线电性连接该些焊垫至该电路基板。
13、根据权利要求7所述的晶穴朝下型芯片封装构造,其特征在于其中所述的散热片是为一背胶铜箔,该背胶铜箔的一树脂层是可粘接该芯片的一背面。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNB2005100985061A CN100416783C (zh) | 2005-08-31 | 2005-08-31 | 晶穴朝下型芯片封装构造的制造方法及构造 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNB2005100985061A CN100416783C (zh) | 2005-08-31 | 2005-08-31 | 晶穴朝下型芯片封装构造的制造方法及构造 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1925120A true CN1925120A (zh) | 2007-03-07 |
CN100416783C CN100416783C (zh) | 2008-09-03 |
Family
ID=37817685
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2005100985061A Expired - Fee Related CN100416783C (zh) | 2005-08-31 | 2005-08-31 | 晶穴朝下型芯片封装构造的制造方法及构造 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN100416783C (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8129225B2 (en) | 2007-08-10 | 2012-03-06 | Infineon Technologies Ag | Method of manufacturing an integrated circuit module |
CN104022091A (zh) * | 2013-03-01 | 2014-09-03 | 英飞凌科技奥地利有限公司 | 半导体芯片封装 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5661086A (en) * | 1995-03-28 | 1997-08-26 | Mitsui High-Tec, Inc. | Process for manufacturing a plurality of strip lead frame semiconductor devices |
US6048755A (en) * | 1998-11-12 | 2000-04-11 | Micron Technology, Inc. | Method for fabricating BGA package using substrate with patterned solder mask open in die attach area |
US6825550B2 (en) * | 1999-09-02 | 2004-11-30 | Micron Technology, Inc. | Board-on-chip packages with conductive foil on the chip surface |
CN1172369C (zh) * | 2001-06-13 | 2004-10-20 | 矽品精密工业股份有限公司 | 具散热片的半导体封装件 |
US7105931B2 (en) * | 2003-01-07 | 2006-09-12 | Abbas Ismail Attarwala | Electronic package and method |
-
2005
- 2005-08-31 CN CNB2005100985061A patent/CN100416783C/zh not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8129225B2 (en) | 2007-08-10 | 2012-03-06 | Infineon Technologies Ag | Method of manufacturing an integrated circuit module |
CN104022091A (zh) * | 2013-03-01 | 2014-09-03 | 英飞凌科技奥地利有限公司 | 半导体芯片封装 |
Also Published As
Publication number | Publication date |
---|---|
CN100416783C (zh) | 2008-09-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN100485917C (zh) | 电镀于封胶内的无外引脚半导体封装构造的制造方法 | |
CN101188226A (zh) | 芯片封装结构及其制程 | |
CN1106164A (zh) | 半导体器件及其制造方法 | |
CN206282838U (zh) | 无源器件与有源器件的集成封装结构 | |
CN201655787U (zh) | 半导体封装结构 | |
CN1925120A (zh) | 晶穴朝下型芯片封装构造的制造方法及构造 | |
CN110767615A (zh) | 一种ssd存储芯片封装结构及制造方法 | |
CN115995440A (zh) | 半导体封装结构及其制造方法 | |
CN1153287C (zh) | 具有内嵌式散热块的半导体封装件 | |
CN212848364U (zh) | 多基岛引线框架的封装结构 | |
CN203277361U (zh) | 导线架及其封装构造 | |
CN100403532C (zh) | 散热型球格阵列封装结构 | |
CN1941336A (zh) | 增进晶背散热的薄型封装构造 | |
CN212182316U (zh) | 一种无载体的半导体叠层封装结构 | |
CN102354720A (zh) | 一种led的封装方法及led封装结构 | |
CN1152429C (zh) | 封装影像感测芯片及其封装方法 | |
CN1577779A (zh) | 中央焊垫记忆体堆叠封装组件及其封装制程 | |
CN101064259A (zh) | 半导体封装件及其芯片承载结构与制法 | |
CN1851907A (zh) | 包含被动元件的半导体封装构造 | |
CN1921099A (zh) | 引脚在芯片上的集成电路封装构造及其芯片承载件 | |
CN2779610Y (zh) | 导线架型电气封装体 | |
CN1917196A (zh) | 柱格阵列封装构造及其电子装置 | |
CN1917157A (zh) | 晶穴朝下晶片封装构造及其制造方法 | |
CN219106192U (zh) | 全覆式Chip LED器件 | |
TWI839000B (zh) | 封裝結構以及封裝方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080903 Termination date: 20200831 |
|
CF01 | Termination of patent right due to non-payment of annual fee |