CN1906766A - 半导体装置的模块结构 - Google Patents

半导体装置的模块结构 Download PDF

Info

Publication number
CN1906766A
CN1906766A CNA2004800405801A CN200480040580A CN1906766A CN 1906766 A CN1906766 A CN 1906766A CN A2004800405801 A CNA2004800405801 A CN A2004800405801A CN 200480040580 A CN200480040580 A CN 200480040580A CN 1906766 A CN1906766 A CN 1906766A
Authority
CN
China
Prior art keywords
semiconductor
conductivity type
electrode
heat dissipation
dissipation plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2004800405801A
Other languages
English (en)
Other versions
CN100533764C (zh
Inventor
北村谦二
谷高真一
远藤陆男
富永雄二郎
田中俊秀
佐藤浩一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honda Motor Co Ltd
Original Assignee
Honda Motor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honda Motor Co Ltd filed Critical Honda Motor Co Ltd
Publication of CN1906766A publication Critical patent/CN1906766A/zh
Application granted granted Critical
Publication of CN100533764C publication Critical patent/CN100533764C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/051Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • H01L23/3171Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395Vertical transistors, e.g. vertical IGBT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395Vertical transistors, e.g. vertical IGBT
    • H01L29/7396Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/8611Planar PN junction diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165Reinforcing structures
    • H01L2224/02166Collar structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402Field plates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1203Rectifying Diode
    • H01L2924/12036PN diode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本发明的半导体模块,由具有动作部(1)和护圈部(12)的半导体元件(13),和设置在该半导体元件的上面以及下面,并对该半导体元件进行冷却的上下的散热部件(15、14)构成。钝化膜(20),覆盖护圈部,但不覆盖动作部。上部散热部(15),由与所述钝化膜非接触地连接在动作部上的金属平板构成。上部散热部和下部散热部(14)可热传导地被连接。

Description

半导体装置的模块结构
技术领域
本发明涉及半导体装置的模块结构,尤其涉及在包括绝缘栅型双极晶体管(Insulated Gate Bipolar Transistor)(IGBT)等的功率设备的半导体装置中的设备上部具备散热机构的半导体装置的模块结构。
背景技术
公知有作为控制比较大的电流的开关半导体元件的功率设备。在功率设备中有功率晶体管、功率MOSFET、IGBT等。其中IGBT,作为具有基于电压驱动的驱动容易性和基于传导率调制效果的低损耗性的优点的设备使用于电动车辆的逆变器等中。
图5表示现有的IGBT模块的结构。现有的IGBT模块100,具备对具有动作部101和护圈(guard ring)部102的半导体元件103进行冷却的散热板104。散热板104,由与设置在动作部101和护圈部102的下部的基板105接合的下部散热板构成,基板105由绝缘体构成。半导体元件103由IGBT构成。
动作部101,由下述部分构成:第1导电型(N型)半导体的高电阻层106;位于其下部的第1导电型(N+型)半导体的缓冲缓冲层107;形成在第1导电型半导体的高电阻层106的上部的第2导电型(P型)半导体的基极层108;形成在该基极层108的上部的第1导电型(N型)半导体的发射极区域109;与该发射极区域109接触的发射极电极110;和在第2导电型半导体的基极层108的沟道区域上由绝缘体111绝缘形成的栅极电极112。
在第1导电型半导体的缓冲层107的下面,形成有第2导电型(P+型)半导体的集电极层113。该集电极层113与集电极电极114接触。
护圈部102,具有形成在N型半导体层106的上部的第2导电型(P型)半导体层115和堆积在该半导体层115的上部的SiO2等的绝缘膜116。参照编号117为栅极电极引导线。
在动作部101和护圈部102中,在发射极电极110的一部分上与绝缘膜116之上,为了抑制漏电流,由聚酰亚胺等的钝化膜118覆盖表面以使作为绝缘膜116的SiO2不被剥离。
构成半导体元件103的半导体由硅(Si)构成。发射极电极110由铝硅(AlSi)构成。集电极电极114由金属114a和金属114b形成,金属114a由银(Ag)或金(Au)构成,金属114b由镍(Ni)构成。集电极电极114和基板105由焊锡119接合。从发射极电极110开始由铝等构成的金属线(wire)120来进行布线。散热板104由铝或铜等形成。基板105由焊锡121与散热板104接合。
图6表示现有的二极管模块的结构。图6中所示的二极管模块200,具备对具有动作部201和护圈部202的半导体元件203进行冷却的散热板204。散热板204,与设置在动作部201和护圈部202的下部的绝缘体构成的基板205接合。半导体元件203为二极管。
动作部201,由下述部分构成:第1导电型(N型)半导体的高电阻层206;位于其下部的第1导电型(N+型)半导体的缓冲层207;形成在第1导电型半导体的高电阻层106的上部的第2导电型(P+型)的半导体层208;与该第2导电型的半导体层208接触的阴极电极209;和与第1导电型的半导体层207接触的阳极电极210。
护圈部202,由形成在N型半导体层206的上部的第2导电型(P型)半导体层211和堆积在该半导体层211的上部的SiO2等的绝缘膜212构成。在阴极电极209的一部分上和由SiO2构成的绝缘体212上,为了抑制漏电流,由聚酰亚胺等的钝化膜213覆盖表面以使SiO2不被剥离。
构成半导体元件203的半导体为硅(Si)。阴极电极209为铝硅(AlSi)或铝/钛镍/钛(Al/TiNi/Ti)。阳极电极210由银(Ag)或金(Au)等的金属210a和镍(Ni)等的金属210b构成。阳极电极210和基板205被焊锡214接合。从阴极电极209开始利用由铝等构成的金属线215进行布线。散热板204由铝或铜等形成。基板205由焊锡216与散热板204接合。
如果将这些功率设备用于电动车辆的逆变器等中,则流过数百安培(A)左右的大电流,半导体元件自身发热。因此,以往在半导体元件的下部(集电极电极侧)设置吸热设备或水冷机构并进行冷却。但是,存在不能冷却半导体元件上面侧的单元,而使单元破坏的情况。
与此相对,例如在特开2000-124398号、特开2000-156439号以及特开2002-33445号中提出了在半导体元件的上面侧具备平面的金属板(盖板(strap)),通过兼具来自电极的导线和散热板,从半导体元件上面开始进行散热的技术。
例如,在特开2000-124398号中公开了一种功率半导体模块,该功率半导体模块由安装在绝缘基板上的功率半导体芯片以及金属平板形成,并具备布线部件,该布线部件具备:与上述功率半导体芯片的电极部对置的电极对置部;从该电极对置部弯曲延伸的立起部;以及与该立起部连接的导出部,上述功率半导体芯片的电极部和上述布线部件的电极相对部由导电性树脂来接合。
在特开2000-156439号中公开了散热散热散热散热散热散热一种功率半导体模块,其中,功率半导体元件的下面被搭载在散热板上并被收纳在筐体内,所述功率半导体模块具备接合在上述半导体元件的上面和上述散热板上的平板状或块(block)的散热部件,并经由散热部件从上述半导体元件的上面向上述散热板散热。
在特开2003-33445号中,公开了一种半导体装置,该半导体装置在主框(frame)上配置2以上的功率元件,并介由金属的连接用框至少连接功率元件的活性面彼此之间。
由此,在半导体元件的上面侧具备平面的金属板(盖板),从元件上面开始进行散热的半导体装置中,通过具有焊锡或导电性树脂等的导电性以及某程度的热传导率的粘接剂将半导体元件上面和盖板电连接。
因此,在特开2000-124398号、特开2000-156439号以及特开2002-33445号中公开的半导体元件的上面侧具备平面的金属板(盖板),并从元件上面开始进行散热的技术中,形成在钝化膜之下的单元与除此之外的单元,其散热特性大幅度不同。在这种状态下,如果单元进行工作,则电流流动,产生焦耳热,容易产生闭锁(latch up)现象。如果产生闭锁现象,则局部地流过电流,产生高热量,成为PN结破坏等单元破坏的原因。
另外,此时,由于作为金属的盖板的热膨胀系数,与半导体元件(Si)、钝化膜(聚酰亚胺、SiN、SiO、SiON、PSG(Phosphorous Silicate Glass),SiO2、NSG(Nondoped Silicate Glass)等)或硅基板的热膨胀系数不同,因此通过半导体元件自身的发热或热冲击试验时的热冲击,向钝化膜下的护圈部施加横方向的应力,会在护圈部的硅基板上产生裂缝。由于该裂缝,其结果导致耐压下降。
此外,在现有的半导体元件中,考虑到在图案加工时产生的侧边(sideedge),将钝化膜形成至单元区域的发射极电极上部为止。
发明内容
在此,期望有一种可解除由于因从半导体元件的上面开始进行散热的结构中的盖板、半导体元件与钝化膜之间的热膨胀系数的不同而产生在护圈部中的应力,而导致耐压下降的问题,以及解除由于钝化膜正下方的单元和除此之外的单元中的散热特性大幅度不同而产生的单元破坏的问题的技术。
在本发明中,提供一种半导体装置的模块结构,其具备:第1导电型的高电阻层;第2导电型的基极层,其形成在所述第1导电型的高电阻层的上部;第1导电型的发射极区域,其形成在所述第2导电型的基极层的上部;发射极电极,其与所述发射极区域连接;栅极电极,其与所述第2导电型的基极层邻接并被绝缘;护圈部,,加深包括所述发射极区域的单元区域周围的扩散;钝化膜,其形成在所述护圈部的上部,且不覆盖在所述单元区域的上部;第2导电型集电极层,其形成在所述第1导电型的缓冲层下面;集电极电极,其与所述集电极层连接;金属平板的上部散热部,其以与所述钝化膜非接触的高度,与所述发射极电极连接。
由此,能减小在护圈部中所产生的应力,难以产生耐压降低和单元破坏。即、根据本发明,通过在功率半导体元件的上面侧安装兼具导线和散热板的盖板,能够防止所产生的单元破坏和因对护圈部施加应力而导致的耐压下降。
在本发明中,所述半导体装置的模块结构,优选还具备二极管部,该二极管部的上部阴极电极与所述上部散热部连接。由此,能够形成减少护圈部中产生的应力,并难以产生耐压下降、单元破坏和元件破坏的半导体装置。
附图说明
图1是表示本发明的半导体装置的模块结构中的有关第1实施例的IGBT模块的剖面图。
图2是表示以沟槽结构为第1实施例的半导体装置的模块结构的例子的剖面图。
图3是表示本发明的半导体装置的模块结构中的有关第2实施例的二极管模块的剖面图。
图4是表示在本发明的第3实施例中的由第1实施例的IGBT模块与第2实施例的二极管模块构成的半导体装置的模块结构的剖面图。
图5是表示现有的IGBT模块的结构的剖面图。
图6是表示现有的二极管模块的结构的剖面图。
具体实施方式
以下,参照附图对本发明的几个最佳实施例进行说明。
图1是表示有关本发明的第一实施例的半导体装置的模块结构的主要部分的剖面图。在本实施例中,采用绝缘栅型双极晶体管(IGBT)作为半导体装置。IGBT模块10,具备对具有动作部11和护圈部12的半导体元件13进行冷却的散热板14、15。
散热板14、15,由下部散热板14和上部散热板(盖板)15构成,所述下部散热板14与设置在动作部11和护圈部12的下部的由绝缘体构成的基板34接合,所述上部散热板15具有动作部11上部的、经由金属17、金属18以及粘接剂19与发射极电极16接合的部分;和设置间隙21而不与堆积在护圈部12的上部的钝化膜20接合的部分。
金属17和金属18,为发射极电极16和粘接极19的相关金属。金属18为银(Ag)、金(Au)等。金属17为镍(Ni)、钛/镍(Ni/Ti)等。
粘接剂19为焊锡或导电型树脂等。钝化膜20,由聚酰亚胺、氮化硅(SiN)、氧化硅(SiO)、氮氧化硅(SiON)、磷玻璃(PSG)、非掺杂硅酸盐玻璃(NSG)、二氧化硅(SiO2)等构成。半导体元件13由绝缘型双极晶体管(IGBT)构成。
动作部11,具备:第1导电型(N型)半导体的高电阻层22;位于其下部的第1导电型(N+型)半导体的缓冲层23;形成在第1导电型半导体的高电阻层22的上部的第2导电型(P+型)半导体的基极层24;形成在第2导电型半导体的基极层24的上部的第1导电型(N型)半导体的发射极区域25;与发射极区域25接触的发射极电极16;和在第2导电型半导体的基极层24的沟道区域上由绝缘体26绝缘形成的栅极电极27。在第1导电型半导体的缓冲层23的下面,形成有第2导电型半导体的集电极层28。集电极层28,与由银(Ag)或金(Au)等的金属29b和镍(Ni)等的金属29a构成的集电极电极29接触。
护圈部12,在N型半导体层22的上部形成有第2导电型(P型)半导体层30,在其上部堆积有SiO2等的绝缘层31。此外,护圈部12的表面,为了抑制漏电流,而被聚酰亚胺或氮化硅(SiN)、氧化硅(SiO)、氧氮化硅(SiON)等的钝化膜20所覆盖,以使作为绝缘膜31的SiO2不被剥离。钝化膜20不覆盖动作部的上部。参照编号32为栅极电极引导线。
构成该半导体装置的半导体,例如为硅(Si),但并不限于此,也可是砷化镓(GaAs)等的化合物半导体。发射极电极16为铝硅(AlSi)。集电极电极29与基板34由焊锡35所接合。下部散热板14由铝或铜等所形成。上部散热板(盖板)15也由铝或铜等所形成。
基板34,在其两面粘接有由铜或铝等构成的金属薄板(未图示),并由氧化铝或氮化铝、氮化硅等构成。基板34由焊锡等接合在散热板14上。集电极电极29为焊锡35等的导电性材料,与基板34上的金属薄板电连接。半导体元件13经由基板34搭载在下部散热板14上。上部散热板(盖板)15通过焊锡36与基板34接合。
IGBT模块10在下部散热板14下,由高热传导性的润滑脂与吸热设备等散热器接合。在IGBT模块10运转时,由半导体元件(IGBT元件)13所产生的热,经由下部散热板14和上部散热板15传导到散热器,并被散热。由此,IGBT元件13被冷却。
在这样构成的IGBT模块10中,由IGBT元件13所产生的热,从集电极电极29侧的IGBT元件13下面经由基板34和下部散热板14传导到散热器。
另一方面,在发射极电极16侧的IGBT元件13上面,上部散热板15经由粘接剂19与IGBT元件13的发射极电极16接合,还有该上部散热板15通过焊锡36等与基板34接合。上部散热板15为剖面积大的平板状,因此作为热传导路使用。由IGBT元件13所产生的热,也从IGBT元件13的发射极电极16侧的IGBT元件13上面经由粘接剂19、上部散热板15、基板34以及下部散热板14传导到散热器。
由此,由IGBT元件13所产生的热,从IGBT13的发射极电极16侧、集电极电极29侧这两侧向散热器传导,因此与如现有的IGBT模块那样,只从IGBT元件13的集电极电极29侧向散热器传导的装置相比,由于热传导路增加,因此减少热电阻。由此,能够提高IGBT模块10的冷却性能,降低IGBT元件13的发热温度。此外,由于上部散热板15由金属构成,因此不仅承担来自IGBT元件13的散热,而且构成连接IGBT元件13和发射极用的外部电极端子(未图示)间的电布线的一部分,作为电布线使用。
还有,上述上部散热板15,在与护圈部12上部的钝化膜20之间具有间隙21,由于不与钝化膜20接合,因此即使温度上升时的上部散热板15的膨胀与钝化膜20、护圈部12的热膨胀不同,也不会在形成护圈部12的N型高电阻层22或P型半导体层30、N+型缓冲层23、集电极层28的硅基板上产生热应力,能够抑制在该硅基板中的裂缝的产生,能够避免由裂缝产生所引起的耐压下降。此外,钝化膜20只位于护圈部上部,因此能够避免由焦耳热所引起的半导体内部的温度的不均匀性,因此难以产生闭锁,能够减少单元的破坏。
上述那样的结构,也能对图2所示的沟槽(trench)结构的元件使用。图2是将本发明使用于沟槽机构的设备中的图。单元区域(动作部11)的结构不同,但作为本发明的主要部分的、在单元区域上不具备钝化膜20这一点和由于上部散热板与钝化膜非接触,因此不施加应力这一点相同。此外,关于图2中的符号,对具有与图1的结构相同的功能的部件附加相同的符号。
图3是表示本发明的有关第2实施例的半导体装置的模块结构的剖面图。在该实施例中,构成半导体装置的半导体元件为二极管。二极管模块40,具备对具有动作部41和护圈部42的半导体元件43进行冷却的散热板44、45。
散热板44、45,由下部散热板44和上部散热板(盖板)45构成,所述下部散热板44与设置在动作部41和护圈部42的下部的由绝缘体构成的基板58接合,所述上部散热板45具有:动作部41的上部的、介由金属47、金属48以及粘接剂49与阴极电极46接合的部分;和设置间隙51而不与堆积在护圈部42的上部接合的部分。
金属47和金属48,为阴极电极46与粘接剂49的相关金属。金属47为银(Ag)、金(Au)等。金属48为镍(Ni)、钛/镍(Ni/Ti)等。
粘接剂49为焊锡或导电性树脂等。钝化膜50由聚酰亚胺、氮化硅(SiN)、氧化硅(SiO)、氮氧化硅(SiON)、磷玻璃(PSG)、非掺杂硅酸盐玻璃(NSG)、二氧化硅(SiO2)等构成。半导体元件43由二极管构成。
动作部41具备:第1导电型(N型)半导体的高电阻层52;位于其下部的第1导电型(N+型)半导体的半导体层53;形成在第1导电型(N型)半导体的高电阻层52的上部的第2导电型(P+型)的半导体层54;与第2导电型半导体层54接触的阴极电极46;和由与第1导电型的半导体层53接触的银(Ag)或金(Au)等的金属55b和镍(Ni)等的金属55a构成的阳极电极55。
护圈部42,在N型半导体层52的上部形成有第2导电型(P型)半导体层56,在其上部堆积有SiO2等的绝缘层57。护圈部42的表面,为了抑制漏电流,而被聚酰亚胺或氮化硅(SiN)、氧化硅(SiO)、氧氮化硅(SiON)、磷玻璃(PSG)、非掺杂硅酸盐玻璃(NSG)、二氧化硅(SiO2)等的钝化膜50所覆盖,以使作为绝缘膜57的SiO2不被剥离。钝化膜50不覆盖动作部41的上部。
构成该半导体装置的半导体,例如为硅(Si),但并不限于此,也可是砷化镓(GaAs)等的化合物半导体。阴极电极46为铝硅(AlSi)。阳极电极55与基板58由焊锡59a接合。下部散热板44由铝或铜等形成。上部散热板(盖板)45也由铝或铜等形成。
基板58,在其两面粘接有由铜等构成的金属薄板(未图示),并由氧化铝或氮化铝等构成。基板58由焊锡等接合在下部散热板44上。阳极电极55由焊锡59a等导电性材料与基板58上的金属薄板电连接。半导体元件43经由基板58搭载在下部散热板44上。上部散热板(盖板)45由焊锡59b与基板58接合。
二极管模块40在下部散热板44下,由高热传导性的润滑脂等与吸热设备等散热器接合。在二极管模块运转时,由半导体元件(二极管元件)43所产生的热,经由下部散热板44和上部散热板45传导到散热器,并被散热。由此,二极管元件43被冷却。
在这样构成的二极管模块40中,由二极管元件43所产生的热,从阳极电极55侧的二极管元件43下面经由基板58和下部散热板44传导到散热器。
另一方面,在阴极电极46侧的二极管元件43上面,上部散热板45经由粘接剂49与二极管元件43的阴极电极46接合。该上部散热板45由焊锡59b等与基板58接合。上部散热板45为剖面积大的平板状,因此作为热传导路使用。由二极管元件43所产生的热,从二极管元件43的阴极电极46侧的二极管元件43上面开始经由粘接剂49、上部散热板45、基板58以及下部散热板44传导到散热器。
由此,由二极管元件43所产生的热,从二极管43的阴极电极46侧、阳极电极55侧的两侧向散热器传导,因此与如现有的二极管模块那样,只从二极管元件43的阳极电极55侧向散热器传导的装置相比,由于热传导路增加,因此减少热电阻。由此,能够提高二极管模块40的冷却性能,降低二极管元件43的发热温度。此外,由于上部散热板45由金属构成,因此不仅承担来自二极管元件43的散热,而且构成连接二极管元件43和阴极用的外部电极端子(未图示)间的电布线的一部分,并作为电布线使用。
还有,上述上部散热板45,在与护圈部42上部的钝化膜50之间具有间隙51,由于不与钝化膜50接合,因此即使温度上升时的上部散热板45的膨胀与钝化膜50、护圈部42的热膨胀不同,也不会在形成护圈部42的N型高电阻层52或P型半导体层56、N+型缓冲层53的硅基板上产生热应力,能够抑制在该硅基板上的裂缝的产生,能够避免由裂缝产生所引起的耐压下降。此外,钝化膜50只位于护圈部上部,因此能够避免由焦耳热所引起的半导体内部的温度的不均匀性,因此难以产生闭锁,能够减少单元的破坏。
图4是表示有关本发明的第3实施例的半导体装置的模块结构的主要部分的剖面图。该实施例的半导体装置模块60,具有绝缘栅型双极晶体管(IGBT)和二极管。IGBT元件与第1实施例所说明的结构相同,因此赋予与图1所示的符号相同的符号,二极管元件与第2实施例所说明的结构相同,因此赋予与图3所示的符号相同的符号,省略这些元件结构的详细的说明。
简单地进行说明,第3实施例的半导体装置模块60,具备冷却半导体元件(IGBT元件)13和半导体元件(二极管元件)43的散热板61、62。散热板61、62由下部散热板61和上部散热板62构成,所述下部散热板61设置在半导体元件13、43的下部,所述上部散热板62具有:动作部11、41的上部的与电极16、46接合的部分;和不与堆积在护圈部12、42的上部的钝化膜20、50接合的部分。
半导体装置模块60在下部散热板61下,由高热传导性的润滑脂等与吸热设备等散热器接合。在半导体装置模块60运转时,由IGBT元件13和二极管元件43所产生的热,经由下部散热板61和上部散热板62传导到散热器,并被散热。由此,IGBT元件13和二极管元件43被冷却。
在这样构成的半导体装置模块60中,由IGBT元件13和二极管元件43所产生的热,从集电极电极29侧的IGBT元件13下面经由基板34和下部散热板61传导到散热器,另外,从阳极电极55侧的二极管元件43下面经由基板58和下部散热板61传导到散热器。
另一方面,在发射极电极16侧的IGBT元件13上面,上部散热板62经由粘接剂19与IGBT元件13的发射极电极16接合。在阴极电极46侧的二极管元件43上面,上部散热板62经由粘接剂49与二极管元件43的阴极电极46接合。
该上部散热板62由焊锡63等与基板接合。上部散热板62为剖面积大的平板状,因此作为热传导路使用。由IGBT元件13所产生的热,也从IGBT元件13的发射极电极16侧的IGBT元件13上面,经由粘接剂19、上部散热板62、基板58以及下部散热板61传导到散热器。由二极管元件43所产生的热,也从二极管元件43的阴极电极46侧的二极管元件43上面经由粘接剂49、上部散热板62、基板58以及下部散热板61传导到散热器。
由此,由IGBT元件13所产生的热,从IGBT13的发射极电极16侧、集电极电极29侧这两侧向散热器传导。由二极管元件43所产生的热,从二极管43的阴极电极46侧、阳极电极55侧这两侧向散热器传导。因此与如现有的半导体装置模块那样,只从IGBT元件的集电极电极侧和二极管元件的阳极电极侧向散热器传导的装置相比,由于增加热传导路,因此减少热电阻。由此,能够提高半导体装置模块的冷却性能,降低IGBT元件13和二极管元件43的发热温度。此外,由于上部散热板62由金属构成,因此不仅承担来自IGBT元件13和二极管元件43的散热,而且构成连接IGBT元件13和发射极用的外部电极端子间,连接二极管元件43和阴极用的外部电极端子间的电布线的一部分,并作为电布线使用。
上述上部散热板62,在与护圈部12上部的钝化膜20之间具有间隙21,由于不与钝化膜20接合,因此即使温度上升时的上部散热板62的膨胀与钝化膜20、护圈部12的热膨胀不同,也不会在形成护圈部12的N型高电阻层22或P型半导体层30、N+型缓冲层23、集电极层28的硅基板上产生热应力,能够抑制在该硅基板上的裂缝的产生,能够避免由裂缝产生所引起的耐压下降。此外,钝化膜20只位于护圈部上部,因此能够避免由焦耳热所引起的半导体内部的温度的不均匀性,因此难以产生闭锁,能够减少单元的破坏。
还有,上述上部散热板62,在与护圈部42上部的钝化膜50之间具有间隙51,由于不与钝化膜50接合,因此即使温度上升时的上部散热板62的膨胀与钝化膜50、护圈部42的热膨胀不同,也不会在形成护圈部42的N型高电阻层52或P型半导体层56、N+型缓冲层53的硅基板上产生热应力,能够抑制在该硅基板上的裂缝的产生,能够避免由裂缝产生所引起的耐压下降。此外,钝化膜50只位于护圈部上部,因此能够避免由焦耳热所引起的半导体内部的温度的不均匀性,因此难以产生闭锁,能够减少单元的破坏。
在本实施例中,对采用N型半导体作为第1导电型半导体,采用P型半导体作为第2导电型半导体进行了说明,但不限于此,也可采用P型半导体作为第1导电型半导体,采用N型半导体作为第2导电型半导体。
产业上的利用可能性
如上所述,根据本发明,由于通过在半导体元件的上面侧安装兼具导线和散热板的盖板,能够防止由热应力所引起的单元破坏、元件破坏和因对护圈部施加应力而导致的的耐压下降,因此在流过大电流的功率半导体模块等功率设备中有用。

Claims (2)

1、一种半导体装置的模块结构,具备:
第1导电型的高电阻层;
第2导电型的基极层,其形成在所述第1导电型的高电阻层的上部;
第1导电型的发射极区域,其形成在所述第2导电型的基极层的上部;
发射极电极,其与所述发射极区域连接;
栅极电极,其与所述第2导电型的基极层相邻且被绝缘;
护圈部,加深包括所述发射极区域的单元区域周围的扩散;
钝化膜,其形成在所述护圈部的上部,且未覆盖在所述单元区域的上部;
第2导电型的集电极层,其被形成在所述第1导电型的缓冲层的下面;
集电极电极,其与所述集电极层连接;以及
金属平板的上部散热部,其以与所述钝化膜非接触的高度,与所述发射极电极连接。
2、根据权利要求1所述的半导体装置的模块结构,其特征在于,
所述半导体装置的模块结构还具备二极管部,该二极管部的上部的阴极电极与所述上部散热部连接。
CNB2004800405801A 2004-01-15 2004-11-30 半导体装置的模块结构 Expired - Fee Related CN100533764C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP008022/2004 2004-01-15
JP2004008022A JP2005203548A (ja) 2004-01-15 2004-01-15 半導体装置のモジュール構造

Publications (2)

Publication Number Publication Date
CN1906766A true CN1906766A (zh) 2007-01-31
CN100533764C CN100533764C (zh) 2009-08-26

Family

ID=34792205

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004800405801A Expired - Fee Related CN100533764C (zh) 2004-01-15 2004-11-30 半导体装置的模块结构

Country Status (5)

Country Link
US (1) US7663220B2 (zh)
JP (1) JP2005203548A (zh)
CN (1) CN100533764C (zh)
DE (1) DE112004002653T5 (zh)
WO (1) WO2005069381A1 (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103579303A (zh) * 2012-08-02 2014-02-12 丰田自动车株式会社 半导体装置及其制造方法
CN106409893A (zh) * 2015-07-28 2017-02-15 无锡华润华晶微电子有限公司 一种绝缘栅双极晶体管及其制备方法
CN106471623A (zh) * 2014-07-07 2017-03-01 丰田自动车株式会社 半导体装置
CN113614883A (zh) * 2019-03-28 2021-11-05 株式会社电装 半导体装置

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4984485B2 (ja) * 2005-10-17 2012-07-25 富士電機株式会社 半導体装置
JP2007142138A (ja) * 2005-11-18 2007-06-07 Mitsubishi Electric Corp 半導体装置
JP2008227116A (ja) 2007-03-13 2008-09-25 Renesas Technology Corp 半導体装置およびその製造方法
EP2017887A1 (en) * 2007-07-20 2009-01-21 ABB Research Ltd. Package for electronic components and method for packaging semiconductor devices
JP5589342B2 (ja) * 2009-10-19 2014-09-17 トヨタ自動車株式会社 半導体装置
JP5720647B2 (ja) * 2012-09-03 2015-05-20 トヨタ自動車株式会社 半導体装置及びその製造方法
DE102014212455A1 (de) * 2014-06-27 2015-12-31 Robert Bosch Gmbh Diode mit einem plattenförmigen Halbleiterelement
US9548262B2 (en) * 2014-09-29 2017-01-17 Shindengen Electric Manufacturing Co., Ltd. Method of manufacturing semiconductor package and semiconductor package
JP6264334B2 (ja) * 2015-07-21 2018-01-24 トヨタ自動車株式会社 半導体装置
US11145712B2 (en) * 2016-05-17 2021-10-12 Mitsubishi Electric Corporation Semiconductor apparatus and method for manufacturing the same
JP6972622B2 (ja) * 2017-04-03 2021-11-24 富士電機株式会社 半導体装置および半導体装置の製造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000124398A (ja) 1998-10-16 2000-04-28 Mitsubishi Electric Corp パワー半導体モジュール
JP2000156439A (ja) 1998-11-20 2000-06-06 Mitsubishi Electric Corp パワー半導体モジュール
JP2001111034A (ja) * 1999-10-07 2001-04-20 Fuji Electric Co Ltd プレーナ型半導体装置
JP3596388B2 (ja) * 1999-11-24 2004-12-02 株式会社デンソー 半導体装置
US6703707B1 (en) * 1999-11-24 2004-03-09 Denso Corporation Semiconductor device having radiation structure
JP4409064B2 (ja) 2000-07-14 2010-02-03 三菱電機株式会社 パワー素子を含む半導体装置
JP2003017658A (ja) * 2001-06-28 2003-01-17 Toshiba Corp 電力用半導体装置
US7145254B2 (en) * 2001-07-26 2006-12-05 Denso Corporation Transfer-molded power device and method for manufacturing transfer-molded power device
US6803667B2 (en) * 2001-08-09 2004-10-12 Denso Corporation Semiconductor device having a protective film
JP3627738B2 (ja) * 2001-12-27 2005-03-09 株式会社デンソー 半導体装置
US6867978B2 (en) * 2002-10-08 2005-03-15 Intel Corporation Integrated heat spreader package for heat transfer and for bond line thickness control and process of making
US20040118501A1 (en) * 2002-12-19 2004-06-24 Intel Corporation Heat transfer composite with anisotropic heat flow structure
JP3879688B2 (ja) * 2003-03-26 2007-02-14 株式会社デンソー 半導体装置

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103579303A (zh) * 2012-08-02 2014-02-12 丰田自动车株式会社 半导体装置及其制造方法
CN103579303B (zh) * 2012-08-02 2017-06-06 丰田自动车株式会社 半导体装置及其制造方法
CN106471623A (zh) * 2014-07-07 2017-03-01 丰田自动车株式会社 半导体装置
CN106471623B (zh) * 2014-07-07 2019-10-29 丰田自动车株式会社 半导体装置
CN106409893A (zh) * 2015-07-28 2017-02-15 无锡华润华晶微电子有限公司 一种绝缘栅双极晶体管及其制备方法
CN113614883A (zh) * 2019-03-28 2021-11-05 株式会社电装 半导体装置
CN113614883B (zh) * 2019-03-28 2023-08-04 株式会社电装 半导体装置

Also Published As

Publication number Publication date
US20070138596A1 (en) 2007-06-21
CN100533764C (zh) 2009-08-26
JP2005203548A (ja) 2005-07-28
US7663220B2 (en) 2010-02-16
DE112004002653T5 (de) 2006-12-07
WO2005069381A1 (ja) 2005-07-28

Similar Documents

Publication Publication Date Title
US10483216B2 (en) Power module and fabrication method for the same
CN1204623C (zh) 半导体装置
CN1906766A (zh) 半导体装置的模块结构
KR101375502B1 (ko) 전력용 반도체 모듈
JP5163055B2 (ja) 電力半導体モジュール
CN1127761C (zh) 半导体装置
CN1146994C (zh) 半导体器件
US10861833B2 (en) Semiconductor device
KR20140026496A (ko) 반도체 유닛 및 그것을 이용한 반도체 장치
CN1146041C (zh) 包括冷却器的电力电子部件
JP2021122076A (ja) 半導体装置
JP7192968B2 (ja) 半導体装置
CN1508883A (zh) 半导体器件及保持电路
US10490482B1 (en) Cooling devices including jet cooling with an intermediate mesh and methods for using the same
JP5098630B2 (ja) 半導体装置及びその製造方法
WO2018047485A1 (ja) パワーモジュールおよびインバータ装置
JP2012209470A (ja) 半導体装置、半導体装置モジュール及び半導体装置の製造方法
JP4293272B2 (ja) 半導体装置
US11735557B2 (en) Power module of double-faced cooling
US20240096730A1 (en) Semiconductor Module Having Double Sided Heat Dissipation Structure and Method for Fabricating the Same
JP7293978B2 (ja) 半導体装置
CN111180516B (zh) 半导体装置
US11276627B2 (en) Semiconductor device
CN1943032A (zh) 半导体器件
CN111448668B (zh) 功率半导体装置、模块及制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090826

Termination date: 20121130