WO2016051449A1 - 半導体パッケージの製造方法および半導体パッケージ - Google Patents

半導体パッケージの製造方法および半導体パッケージ Download PDF

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Publication number
WO2016051449A1
WO2016051449A1 PCT/JP2014/075819 JP2014075819W WO2016051449A1 WO 2016051449 A1 WO2016051449 A1 WO 2016051449A1 JP 2014075819 W JP2014075819 W JP 2014075819W WO 2016051449 A1 WO2016051449 A1 WO 2016051449A1
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Prior art keywords
sealing resin
semiconductor element
die pad
region
lead
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PCT/JP2014/075819
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English (en)
French (fr)
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有市 見澤
健男 長瀬
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新電元工業株式会社
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Application filed by 新電元工業株式会社 filed Critical 新電元工業株式会社
Priority to JP2015508905A priority Critical patent/JP5930566B1/ja
Priority to PCT/JP2014/075819 priority patent/WO2016051449A1/ja
Priority to EP14863035.3A priority patent/EP3203510A4/en
Priority to US14/648,558 priority patent/US9548262B2/en
Priority to CN201480003328.7A priority patent/CN105684142B/zh
Publication of WO2016051449A1 publication Critical patent/WO2016051449A1/ja

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Definitions

  • the present invention relates to a semiconductor package manufacturing method and a semiconductor package.
  • a resin-sealed semiconductor package in which a semiconductor element, a lead, a connecting member, and a die pad are sealed with a sealing resin in a state where the semiconductor element is bonded onto the die pad and the semiconductor element and the lead are connected by a connecting member.
  • the die pad is made of metal and has low adhesion with the sealing resin. Therefore, peeling is likely to occur between the die pad and the sealing resin.
  • the reliability test of semiconductor packages environmental tests such as temperature cycle test and intermittent operation test
  • the die pad and the sealing resin are exposed to external heat and semiconductor elements. Thermal expansion due to self-heating. For this reason, there is a possibility that the die pad and the sealing resin move relative to each other based on the difference in thermal expansion coefficient between the die pad and the sealing resin, and a crack is generated in the bonding member that joins the semiconductor element and the die pad.
  • a crack occurs in the bonding member, the electrical resistance between the semiconductor element and the die pad increases. Moreover, the heat dissipation of the semiconductor element also deteriorates.
  • Patent Document 1 the above problem is suppressed by performing a roughening process on the upper surface of the die pad to increase the adhesion between the die pad and the sealing resin.
  • a semiconductor element is bonded to the upper surface of the die pad.
  • it seals with sealing resin.
  • the sealing resin is filled in the uneven portion on the upper surface of the die pad, and the sealing resin and the uneven portion are physically engaged. Therefore, relative movement between the die pad and the sealing resin is suppressed.
  • Patent Document 1 does not mention the adhesion between the sealing resin and the semiconductor element.
  • the surface of a semiconductor element is made of an inorganic material such as a semiconductor oxide film or an electrode, the adhesion between the sealing resin and the semiconductor element is weak. For this reason, when the reliability test described above is performed on the semiconductor package, the sealing resin and the semiconductor element move relative to each other based on the difference in thermal expansion coefficient between the semiconductor element and the sealing resin, and the semiconductor element and the die pad. There is a possibility that cracks may occur in the joining member that joins.
  • a silane coupling agent is known as a technique for increasing the adhesion between an inorganic substance (metal) and an organic substance (resin).
  • a silane coupling agent is a technique for enhancing the adhesion between a metal and a resin by chemically bonding the metal and the resin.
  • Patent Document 2 when a resin substrate on which a semiconductor package is mounted and a heat dissipation substrate formed of metal are bonded, a silane coupling agent is applied to the surface of the heat dissipation substrate to increase the adhesion between them.
  • Patent Documents 3 to 5 disclose techniques for mounting a semiconductor element on a lead frame whose surface is treated with a silane coupling agent and then sealing the semiconductor element and the lead with a sealing resin.
  • increasing the adhesion between the sealing resin and the semiconductor element may not always produce a favorable effect in improving the electrical characteristics of the semiconductor package.
  • the semiconductor element and the sealing resin are in close contact with each other, when the reliability test is performed, the semiconductor element and the sealing resin are based on the difference in thermal expansion coefficient between the semiconductor element and the sealing resin.
  • a large stress is generated at the interface.
  • a plurality of layers for forming an electric circuit are formed in a semiconductor element.
  • cracks are generated in each layer, or between the layers. Separation may occur, which may affect the electrical characteristics of the semiconductor element.
  • An object of the present invention is to provide a method for manufacturing a semiconductor package and a semiconductor package, which have high adhesion between a die pad and a semiconductor element and a sealing resin and are excellent in electrical characteristics of the semiconductor element.
  • a manufacturing method of a semiconductor package includes a mounting step of bonding a semiconductor element to an upper surface of a die pad, a connecting step of electrically connecting the semiconductor element and a lead by a connecting member, the die pad, and the semiconductor element A surface treatment step of surface-treating the surfaces of the connection member and the lead with a silane coupling agent; and a sealing step of sealing the die pad, the semiconductor element, the connection member, and the lead with a sealing resin.
  • the first surface of the semiconductor element to which the connecting member is bonded out of the surface of the semiconductor element includes a first region where the organic matter is exposed and a second region where the inorganic matter is exposed.
  • the bonding strength between the first region and the sealing resin is weaker than the bonding strength between the second region and the sealing resin.
  • a semiconductor package includes a die pad, a semiconductor element bonded to an upper surface of the die pad, a lead, a connecting member that connects the semiconductor element and the lead, the die pad, the semiconductor element, A sealing resin that seals the connection member and the lead, and the surface of the die pad, the semiconductor element, the connection member, and the lead is surface-treated with a silane coupling agent,
  • the first surface of the semiconductor element to which the connection member is bonded includes a first region where an organic substance is exposed and a second region where an inorganic substance is exposed, and the first region and the first region
  • the surface of the second region is surface-treated with a silane coupling agent, and the bonding strength between the first region and the sealing resin is the same as that of the second region. Weaker than the bonding strength between Kifutome resin.
  • the surface treatment using the silane coupling agent is performed after the mounting of the semiconductor element and the connection with the lead is completed, not only the bonding strength between the die pad and the sealing resin but also the sealing between the semiconductor element and the sealing element is performed. Bonding strength with the stop resin is also improved.
  • the hydroxyl region end of the silane coupling agent is less likely to bind to the first region where the organic matter is exposed than the second region where the inorganic matter is exposed, the bonding strength between the sealing resin and the first region is reduced. Is weaker than the bonding strength between the sealing resin and the second region.
  • the second region of the semiconductor element and the sealing are sealed based on the difference in coefficient of thermal expansion between the semiconductor element and the sealing resin.
  • the stress generated at the interface with the stop resin can be relaxed in the semiconductor element and the sealing resin corresponding to the first region.
  • FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG. It is a figure which shows the flow of the manufacturing method which concerns on 1st embodiment. It is the figure which showed the area
  • the semiconductor package 30 according to the present embodiment includes a die pad 11, a semiconductor element 31, a lead 12, a suspension lead portion 15, a connection member 32, a sealing resin 33, including.
  • the die pad 11 is a flat member for mounting the semiconductor element 31. As shown in FIG. 2, the die pad 11 has a first main surface 1101 and a second main surface (upper surface) 1102 opposite to the first main surface 1101. The semiconductor element 31 is bonded to the second main surface 1102 of the die pad 11 using a bonding member 41 such as solder or silver paste.
  • a bonding member 41 such as solder or silver paste.
  • the semiconductor element 31 includes a base material portion 311.
  • the base material portion 311 is a plate-like semiconductor having a rectangular shape in plan view.
  • the base material part 311 is made of, for example, silicon.
  • a semiconductor oxide film which is an inorganic substance, for example, a silicon oxide film (SiO 2 ) is formed on the surface of the base material portion 311.
  • the base material portion 311 includes a first main surface 3111 and a second main surface 3112 opposite to the first main surface 3111.
  • the second main surface 3112 faces the second main surface 1102 of the die pad 11.
  • the semiconductor element 31 includes a guard ring 341.
  • the guard ring 341 is formed in a loop shape.
  • the guard ring 341 is made of aluminum, for example.
  • the guard ring 341 is provided on the first main surface 3111 of the base material portion 311.
  • the guard ring 341 is provided to protect the semiconductor element 31 from cracks that occur during scribing.
  • An insulating layer 342 is formed on the surface of the guard ring 341.
  • the insulating layer 342 is manufactured by, for example, forming a TEOS (tetraethoxysilane) layer on the surface of the guard ring 341 and then laminating an organic layer on the TEOS layer.
  • the organic substance is, for example, polyimide.
  • the surface of the insulating layer 342 is made of an organic material.
  • the semiconductor element 31 includes an electrode portion 312.
  • the electrode portion 312 is a plate-like metal member provided to electrically connect the semiconductor element 31 and the lead 12.
  • the electrode portion 312 is provided in a portion of the first main surface 3111 of the base material portion 311 that is surrounded by the guard ring 341 in plan view.
  • the electrode portion 312 is made of metal.
  • the electrode unit 312 is made of aluminum, for example.
  • a film of metal oxide, for example, aluminum oxide (Al 2 O 3 ) is formed on the surface of the electrode portion 312.
  • the electrode unit 312 includes, for example, a first electrode 3121 and a second electrode 3122.
  • the first surface 3101 is on the outermost surface of the semiconductor element 31 on the first main surface 3111 side.
  • the first surface 3101 includes the first main surface 3111 of the base material portion 311, the surface of the insulating layer 342, and the surface of the electrode portion 312.
  • the surface of the base material portion 311 is composed of an inorganic material such as a semiconductor or a semiconductor oxide film
  • the surface of the insulating layer 342 is composed of an organic film made of an organic material such as polyimide
  • the surface of the electrode portion 312 is a metal or metal oxide. It is comprised with inorganic substances, such as. Accordingly, the first surface 3101 includes the first region 34 where the organic matter is exposed and the second region 35 where the inorganic matter is exposed.
  • the first region 34 includes the surface of the insulating layer 342.
  • the second region 35 includes the surface of the electrode portion 312 and the first main surface 3111 of the base material portion 311. Note that there may be a portion where an organic film is formed on the surface of the electrode portion 312. In this case, the first region 34 includes an organic surface provided on the electrode portion 312. At least a part of the surface of the electrode portion 312 is included in the second region 35.
  • connection member 32 is, for example, a bonding wire as shown in FIGS.
  • the bonding wire is formed of the same inorganic material as the electrode unit 312, for example, aluminum.
  • the connection member 32 includes a first connection member 321a and a second connection member 322a.
  • the first connecting member 321a is joined to the surface of the portion included in the second region 35 of the first electrode 3121 by wire bonding.
  • the second connection member 322a is joined to the surface of the portion included in the second region 35 of the second electrode 3122 by wire bonding.
  • the first connecting member 321a is joined to the surface of the portion included in the second region 35 of the first electrode 3121 by wire bonding.
  • the second connection member 322a is joined to the surface of the portion included in the second region 35 of the second electrode 3122 by wire bonding.
  • the semiconductor element 31 includes a third electrode 313 as shown in FIGS.
  • the third electrode 313 is formed on the second main surface 3112 of the base material portion 311.
  • the semiconductor element 31 is, for example, a bipolar transistor.
  • the first electrode 3121 is a gate electrode
  • the second electrode 3122 is a source electrode
  • the third electrode 313 is a drain electrode.
  • the lead 12 includes a first end 17 and a second end 18.
  • a connection member 32 is connected to the first end 17. For example, nickel plating is applied to the first end portion 17 of the lead 12.
  • the leads 12 are arranged at an interval on one end side of the die pad 11 in plan view.
  • the lead 12 is formed to extend in a direction away from one end of the die pad 11 along the main surfaces 1101 and 1102 of the die pad 11. Of both ends in the longitudinal direction of the lead 12, the end adjacent to the die pad 11 is a first end 17. The end located away from the die pad 11 is the second end 18.
  • the leads 12 are arranged at an interval on one end side of the die pad 11 in plan view.
  • the lead 12 is formed to extend in a direction away from one end of the die pad 11 along the main surfaces 1101 and 1102 of the die pad 11. Of both ends in the longitudinal direction of the lead 12, the end adjacent to the die pad 11 is a first end 17. The end located away from the die pad 11 is the second end 18.
  • the suspension lead portion 15 extends in the longitudinal direction of the lead 12 from one end of the die pad 11.
  • the suspension lead portion 15 is, for example, a drain wire.
  • the suspension lead portion 15 is electrically connected to the third electrode 313 via the die pad 11.
  • the die pad 11, the lead 12, and the suspension lead portion 15 are sealed with a sealing resin 33.
  • the first end 17 of the lead 12 is sealed with a sealing resin 33.
  • the second end portion 18 of the lead 12 extends from the sealing resin 33. Further, the first main surface 1101 of the die pad 11 is exposed to the outside of the sealing resin 33.
  • the sealing resin 33 contains a silane coupling agent.
  • the silane coupling agent contained in the sealing resin 33 is, for example, a curing accelerator when the sealing resin 33 is cured, or an adhesion improver that improves the adhesion between the sealing resin 33 and the die pad 11 and the semiconductor element 31. Function as.
  • a silane coupling agent different from the silane coupling agent used in the surface treatment described later is used, but the same as the silane coupling agent used in the surface treatment.
  • a silane coupling agent may be used.
  • the surfaces of the die pad 11, the semiconductor element 31, the connection member 32, the lead 12 and the suspension lead portion 15 are surfaced by a silane coupling agent in a state where the semiconductor element is bonded to the die pad and the semiconductor element and the lead are connected by the connection member. As a result, the bonding strength with the sealing resin 33 is increased.
  • the silane coupling agent molecule has two functional groups bonded to the silicon atom: the first functional group that chemically bonds to the organic material at the end and the second functional group that chemically bonds to the inorganic material at the end. Has the structure.
  • the second functional group is bonded to the inorganic material by, for example, dehydrating condensation with a hydroxyl group on the surface of the inorganic material by hydrolysis.
  • silane coupling agent known ones such as 3-mercaptopropyltrimethoxysilane and 3-acryloxypropyltrimethoxysilane can be used.
  • the lead frame When manufacturing the semiconductor package 30, a lead frame having the die pad 11, the lead 12 and the suspension lead portion 15 shown in FIG. 1 is prepared.
  • the lead frame further includes a connection frame portion (not shown) that integrally connects the die pad 11 and the plurality of leads 12.
  • the lead frame can be obtained by, for example, pressing a conductive plate material such as a copper plate.
  • the suspension lead portion 15 is bent, and the die pad 11 is shifted in the thickness direction with respect to the lead 12. Accordingly, the lead 12 is positioned above the second main surface 1102 of the die pad 11 (see FIG. 2).
  • the semiconductor element 31 is mounted on the second main surface (upper surface) 1102 of the die pad 11, as shown in FIGS.
  • the semiconductor element 31 is placed so that the second main surface 3112 of the base material portion 311 faces the second main surface 1102 of the die pad 11.
  • the third main electrode 313 formed on the second surface 3102 which is the surface opposite to the first surface 3101 of the semiconductor element 31, is bonded to the second main surface of the die pad 11 by a bonding member 41 such as solder or silver paste. Bonded to surface 1102. Joining using solder is performed, for example, by a reflow method.
  • the third electrode 313 is electrically connected to the die pad 11 by the bonding member.
  • connection process S2 Next, as shown in FIG. 5, the semiconductor element 31 and the lead 12 are electrically connected by a connecting member 32. In the connecting step, both ends of the connecting member 32 are connected to the semiconductor element 31 and the lead 12 (see FIGS. 1 and 2).
  • connection step S2 as shown in FIGS. 1 and 2, the first electrode 3121 of the semiconductor element 31 and the first lead 121 are connected by the first bonding wire 321a. Further, the second electrode 3122 of the semiconductor element 31 and the second lead 122 are connected by the second bonding wire 322a.
  • the surface treatment step S3 includes, for example, a spraying step S31 and a heating step S32 in this order.
  • a solution obtained by diluting the silane coupling agent with ethanol, methanol, isopropyl alcohol, or the like is used, for example, from the second main surface 1102 side of the die pad 11, the die pad 11, the semiconductor element 31, and the connecting member 32.
  • the surface of the lead 12 and the suspension lead portion 15 is sprayed.
  • region to spray is area
  • a silane coupling agent is applied to the upper surface of the end portion 17 and the suspension lead portion 15.
  • the base material portion 311 is formed of silicon. For this reason, a film of silicon oxide (SiO 2 ) is formed on the surface of the base material portion 311. Moreover, the electrode part 312 is formed with aluminum. For this reason, a film of aluminum oxide (Al 2 O 3 ) is formed on the surface of the electrode portion 312.
  • the number of exposed hydroxyl terminal ends is smaller than in the second region 35 including the base material portion 311 and the electrode portion 312.
  • the second functional group of the silane coupling agent is not easily bonded to the first region 34. Therefore, the bonding strength between the sealing resin 33 and the first region 34 is weaker than the bonding strength between the sealing resin 33 and the second region 35.
  • the semiconductor element 31 When performing a reliability test such as a temperature cycle test or an intermittent operation test, the semiconductor element 31 is heated from the outside or generates heat by itself. Although the semiconductor element 31 and the sealing resin 33 are thermally expanded by the generated heat, the second region 35 including the electrode portion 312 and the base material portion 311 and the second region 35 are strong due to a difference in thermal expansion coefficient. A large stress is generated at the interface with the sealing resin 33 bonded to.
  • the bonding strength between the sealing resin 33 and the first region 34 is weaker than the bonding strength between the sealing resin 33 and the second region 35. No significant stress is generated at the interface. For this reason, the stress generated at the interface between the second region 35 of the semiconductor element 31 and the sealing resin 33 is relaxed in the semiconductor element and the sealing resin corresponding to the first region 34. As a result, it is possible to suppress the stress from acting strongly on the second region 35.
  • the mechanism by which the stress generated at the interface between the semiconductor element 31 and the sealing resin 33 is relaxed by forming the first region 34 is as follows.
  • the semiconductor element 31 and the sealing resin 33 When heat is applied to the semiconductor element 31 and the sealing resin 33, the semiconductor element 31 and the sealing resin 33 each thermally expand. Due to thermal expansion, the semiconductor element 31 and the sealing resin 33 each expand in a direction parallel to the interface. The semiconductor element 31 and the sealing resin 33 have different thermal expansion coefficients. For this reason, the expanding length differs between the semiconductor element 31 and the sealing resin 33.
  • the semiconductor element 31 has a larger thermal expansion coefficient than the sealing resin 33. The same applies when the thermal expansion coefficient of the sealing resin 33 is larger.
  • the sealing resin 33 having a smaller expansion length follows the semiconductor element 31 having a larger expansion length and is parallel to the interface. It is displaced to. For this reason, in the vicinity of the interface, the sealing resin 33 receives an elastic force proportional to the amount of displacement of the sealing resin 33.
  • the amount of displacement is proportional to the difference between the expanding lengths of the semiconductor element 31 and the sealing resin 33. As a result, it is considered that stress is generated in the vicinity of the interface.
  • the length of expansion of the semiconductor element 31 and the sealing resin 33 is proportional to the length of the surface where the semiconductor element 31 and the sealing resin 33 are joined before heat is applied. Therefore, the longer the surface where the semiconductor element 31 and the sealing resin 33 are joined, the greater the stress generated in the vicinity of the interface.
  • the first region 34 is formed on a part of the surface where the semiconductor element 31 and the sealing resin 33 are joined before the heat is applied.
  • the sealing resin 33 since the bonding strength between the semiconductor element 31 and the sealing resin 33 is weak, the sealing resin 33 is difficult to follow the semiconductor element 31 and be displaced. For this reason, the length of the surface where the semiconductor element 31 and the sealing resin 33 are joined is substantially shortened. As a result, the stress generated near the interface can be further reduced.
  • the above is the mechanism in which the stress is relaxed by forming the first region 34.
  • the base material portion 311 and the electrode portion 312 have a strong binding force with the sealing resin, there is little possibility that the base material portion 311 and the electrode portion 312 are all peeled off from the sealing resin 33. Therefore, the electrical characteristics of the semiconductor element 31 can be enhanced without significantly impairing the adhesion between the semiconductor element 31 and the sealing resin 33.
  • the bonding strength between the first region 34 and the sealing resin 33 is weaker than the bonding strength between the surface of the electrical connection portion and the sealing resin 33. Therefore, the connection member 32 joined to the electrode portion 312 can be protected from being peeled off. Thereby, the connection reliability of the semiconductor element 31 and the connection member 32 can be improved.
  • the first region 34 is formed in a loop shape.
  • the stress generated based on the difference in thermal expansion coefficient between the semiconductor element 31 and the sealing resin 33 is the first stress regardless of the direction in the first surface 3101. This can be mitigated in the portion of the semiconductor element or sealing resin corresponding to the region 34.
  • the bonding strength between the sealing resin 33 and the bonding member 41 is weaker than the bonding strength between the sealing resin 33 and the second region 35 and the bonding strength between the sealing resin 33 and the die pad 11. Therefore, the stress generated between the semiconductor element 31 and the die pad 11 due to the difference in thermal expansion coefficient between the semiconductor element 31 or the die pad 11 and the sealing resin 33 can be relaxed on the surface of the bonding member 41. it can.
  • the material which forms the base material part 311 and the material which forms the electrode part 312 are not restricted to the above-mentioned combination.
  • the semiconductor material and the metal material can be selected as appropriate, and the number of hydroxyl groups on the surface can be controlled by appropriately performing surface treatment according to the characteristics of the material. For this reason, the bonding strength between the electrode portion 312 and the sealing resin 33 can be made weaker than the bonding strength between the base material portion 311 and the sealing resin 33 for various combinations of materials.
  • the lead frame after the solution spraying is heated.
  • the lead frame after spraying the solution is heated at a temperature of 25 ° C. to 250 ° C. (more preferably 50 ° C. to 150 ° C.). Since the heating temperature is relatively low, the dehydration condensation reaction of the silane coupling agent hardly proceeds in the electrode part. Therefore, it is suppressed that the adhesive force between the electrode portion 312 and the sealing resin 33 becomes excessively strong.
  • the sealing resin 33 includes a silane coupling agent.
  • the silane coupling agent contained in the sealing resin 33 has a function as an adhesion imparting agent, the adhesion between the sealing resin 33 and the die pad 11 and the semiconductor element 31 is increased.
  • the silane coupling agent contained in the sealing resin 33 may be used as a curing accelerator or the like when the sealing resin 33 is cured, and the silane coupling agent used in the surface treatment step S3 is The required functions do not necessarily match. If the silane coupling agent contained in the sealing resin 33 and the silane coupling agent used in the surface treatment step S3 are different, an appropriate silane coupling agent can be selected according to the function required for each.
  • the connecting frame portion (not shown) excluding one end on the die pad side of the suspension lead portion 15 and the second end portion 18 of the lead 12 are arranged outside the sealing resin 33. .
  • the connecting frame portion excluding one end portion of the suspension lead portion 15 is cut off. Further, the second end portion 18 of each lead 12 is bent as necessary. Thereby, the semiconductor package 30 shown in FIGS. 1 and 2 is obtained.
  • the sealing resin 33 is formed so that the first main surface 1101 is exposed. However, the lead frame and the molding die are disposed so that the first main surface 1101 is buried in the sealing resin 33. May be designed.
  • the first embodiment of the present invention has been described above.
  • the surfaces of the die pad 11 and the semiconductor element 31 are surface-treated with a silane coupling agent, not only the adhesion between the die pad 11 and the sealing resin 33 but also between the semiconductor element 31 and the sealing resin 33. Adhesion also increases. Therefore, even if a temperature cycle test or the like is performed, peeling does not easily occur between the semiconductor element 31 and the sealing resin 33, and the occurrence of cracks in the bonding member 41 that connects the semiconductor element 31 and the die pad 11 can be suppressed.
  • the semiconductor is tested when the reliability test is performed.
  • the stress generated at the interface between the second region 35 of the element 31 and the sealing resin 33 is relieved at the portion of the semiconductor element or the sealing resin corresponding to the first region 34. Therefore, it is possible to suppress the stress generated in the sealing resin 33 from acting on the electrode portion 312 strongly.
  • the base material portion 311 and the electrode portion 312 have a strong bonding force with the sealing resin 33, there is little possibility that the base material portion 311 and the electrode portion 312 are all separated from the sealing resin 33. Therefore, the electrical characteristics of the semiconductor element 31 can be enhanced without significantly impairing the adhesion between the semiconductor element 31 and the sealing resin 33.
  • the semiconductor package 30 having high adhesion between the die pad 11 and the semiconductor element 31 and the sealing resin 33 and excellent in the electrical characteristics of the semiconductor element 31.
  • connection member 32 is not a bonding wire but a clip connector. This is different from the first embodiment.
  • the clip connector is a strip-shaped connection member, and is formed by bending a conductive plate material.
  • One end surface of the clip connector is bonded to the surface of the first end portion 17 of the lead 12 via a bonding member such as solder or silver paste.
  • the other end surface of the clip connector is bonded to the surface of the electrode portion 312 via a bonding member such as solder or silver paste.
  • the clip connector includes, for example, a first clip connector (not shown) and a second clip connector 322b.
  • the first electrode 3121 (see FIGS. 1 and 2) is connected to the first clip connector.
  • the second electrode 3122 is connected to the second clip connector 322b.
  • the semiconductor package 30b of this embodiment is manufactured by the same manufacturing method as that of the first embodiment. According to this embodiment, the same effects as those of the first embodiment can be obtained.
  • Example ⁇ A semiconductor package was manufactured using a sealing resin (epoxy resin). In the manufacturing process, the above-described surface treatment process was performed. As a silane coupling agent to be sprayed, 3-mercaptopropyltrimethoxysilane was used.
  • Comparative Example A semiconductor package was manufactured without performing the surface treatment. Other manufacturing conditions are the same as in the examples. The comparative example was also subjected to the same temperature cycle test as that of the example, and the variation of the thermal resistance characteristics was evaluated.
  • the present invention can be used to increase the adhesion between the die pad and the semiconductor element and the sealing resin, and to improve the connection reliability between the semiconductor element and the connection member.

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Abstract

 半導体パッケージにおいて、ダイパッド、半導体素子、接続部材およびリードの表面は、シランカップリング剤によって表面処理され、半導体素子の表面のうち接続部材が接合される半導体素子の第一の面は、有機物が露出した第一の領域と、無機物が露出した第二の領域と、を含み、第一の領域と封止樹脂との接合強度は、第二の領域と封止樹脂との接合強度よりも弱い。

Description

半導体パッケージの製造方法および半導体パッケージ
 この発明は、半導体パッケージの製造方法および半導体パッケージに関する。
 半導体素子をダイパッド上に接合し、半導体素子とリードとを接続部材によって接続した状態で、半導体素子、リード、接続部材およびダイパッドを封止樹脂で封止した樹脂封止型の半導体パッケージが知られている(特許文献1~5参照)。
特開2011-82389号公報 特開2005-226096号公報 特開2005-340474号公報 特開2005-072306号公報 特開平08-078561号公報
 ダイパッドは、金属によって形成されており、封止樹脂との密着力は低い。そのため、ダイパッドと封止樹脂との間には剥離が生じやすい。ダイパッドと封止樹脂とが剥離した状態で、半導体パッケージの信頼性試験(温度サイクル試験、断続動作試験等の環境試験)を行うと、ダイパッドおよび封止樹脂などは、外部からの熱や半導体素子の自己発熱により熱膨張する。このため、ダイパッドと封止樹脂との熱膨張係数の相違に基づいて、ダイパッドと封止樹脂とが相対移動し、半導体素子とダイパッドを接合する接合部材にクラックが発生する惧れがある。接合部材にクラックが生じると、半導体素子とダイパッドとの間の電気抵抗が高くなる。また、半導体素子の放熱性も悪くなる。
 特許文献1では、ダイパッドの上面に粗面化処理を施し、ダイパッドと封止樹脂との密着力を高めることで、上記の問題を抑制している。特許文献1では、ダイパッドの上面に粗面化処理を施した後、ダイパッドの上面に半導体素子を接合する。そして、半導体素子とリードとを接続部材によって接続した後、封止樹脂で封止を行う。この方法では、封止樹脂がダイパッドの上面の凹凸部に充填され、封止樹脂と凹凸部とが物理的に係合する。そのため、ダイパッドと封止樹脂との相対移動が抑制される。
 しかし、この方法では、ダイパッドと封止樹脂との密着力が、ダイパッドと封止樹脂との係合という物理的な作用によってのみ生じるため、密着力は必ずしも十分ではない。また、特許文献1では、封止樹脂と半導体素子との密着力については言及されていない。一般に、半導体素子の表面は、半導体の酸化膜や電極等の無機物からなるため、封止樹脂と半導体素子との密着力が弱い。このため、半導体パッケージに対して前述した信頼性試験を行うと、半導体素子と封止樹脂との熱膨張係数の相違に基づいて、封止樹脂と半導体素子とが相対移動し、半導体素子とダイパッドとを接合する接合部材にクラックが発生する惧れがある。
 一方、無機物(金属)と有機物(樹脂)との密着力を高める技術として、シランカップリング剤が知られている。シランカップリング剤は、金属と樹脂とを化学的に接合することにより、金属と樹脂との密着力を高める技術である。特許文献2では、半導体パッケージが搭載される樹脂基板と、金属で形成された放熱基板とを接合する際に、放熱基板の表面にシランカップリング剤を塗布し、両者の密着力を高めている。特許文献3~5には、表面をシランカップリング剤で処理したリードフレームに半導体素子を実装した後、半導体素子およびリードを封止樹脂で封止する技術が開示されている。
 しかし、この方法では、シランカップリング剤が、ダイパッドと接合部材との密着力を阻害しないように、半導体素子の搭載される領域にマスキングを施すなどの工夫が必要となる。また、ダイパッドと封止樹脂との密着力は高まるが、封止樹脂と半導体素子との密着力については、依然として改善の余地がある。
 一方、封止樹脂と半導体素子との密着力を高めることは、半導体パッケージの電気的特性を高める上で、必ずしも好ましい効果を生まない場合がある。例えば、半導体素子と封止樹脂とが強固に密着していると、信頼性試験を行ったときに、半導体素子と封止樹脂との熱膨張係数の相違に基づいて、半導体素子と封止樹脂との界面に大きな応力が発生する。半導体素子には、電気回路を形成するための複数の層が形成されているが、半導体素子と封止樹脂との界面に大きな応力が発生すると、各層にクラックが発生したり、各層の間に剥離が生じたりして、半導体素子の電気的特性に影響を及ぼす惧れがある。
 本発明の目的は、ダイパッドおよび半導体素子と封止樹脂との密着力が高く、半導体素子の電気的特性にも優れた半導体パッケージの製造方法および半導体パッケージを提供することにある。
 本発明の一態様に係る半導体パッケージの製造方法は、ダイパッドの上面に半導体素子を接合する搭載工程と、前記半導体素子とリードとを接続部材によって電気接続する接続工程と、前記ダイパッド、前記半導体素子、前記接続部材および前記リードの表面をシランカップリング剤によって表面処理する表面処理工程と、前記ダイパッド、前記半導体素子、前記接続部材および前記リードを封止樹脂で封止する封止工程と、をこの順に含み、前記半導体素子の表面のうち前記接続部材が接合される前記半導体素子の第一の面は、有機物が露出した第一の領域と、無機物が露出した第二の領域と、を含み、前記第一の領域と前記封止樹脂との接合強度は、前記第二の領域と前記封止樹脂との接合強度よりも弱い。
 本発明の一態様に係る半導体パッケージは、ダイパッドと、前記ダイパッドの上面に接合された半導体素子と、リードと、前記半導体素子と前記リードとを接続する接続部材と、前記ダイパッド、前記半導体素子、前記接続部材および前記リードを封止する封止樹脂と、を含み、前記ダイパッド、前記半導体素子、前記接続部材および前記リードの表面は、シランカップリング剤によって表面処理され、前記半導体素子の表面のうち前記接続部材が接合される前記半導体素子の前記第一の面は、有機物が露出した第一の領域と、無機物が露出した第二の領域と、を含み、前記第一の領域および前記第二の領域の表面は、シランカップリング剤によって表面処理されており、前記第一の領域と前記封止樹脂との接合強度は、前記第二の領域と前記封止樹脂との接合強度よりも弱い。
 本発明によれば、半導体素子の実装やリードとの接続が終了してからシランカップリング剤を用いた表面処理を行うので、ダイパッドと封止樹脂との接合強度だけでなく、半導体素子と封止樹脂との接合強度も向上する。また、有機物が露出した第一の領域には、無機物が露出した第二の領域と比べて、シランカップリング剤の水酸基末端が結合しにくいため、封止樹脂と第一の領域との接合強度は、封止樹脂と第二の領域との接合強度に比べて弱い。このため、半導体素子外部からの加熱または半導体素子自身の発熱に起因する熱膨張が起きたとき、半導体素子と封止樹脂との熱膨張係数の相違に基づいて半導体素子の第二の領域と封止樹脂との界面において生ずる応力を、第一の領域に対応する半導体素子や封止樹脂の部分において緩和することができる。その結果、半導体素子の第一の面側に形成される電気回路形成用の各層にクラックが発生したり、各層の間に剥離が生じたりすることを抑え、半導体素子の電気的特性に影響を及ぼすことを抑制できる。したがって、ダイパッドおよび半導体素子と封止樹脂との密着力が高く、半導体素子の電気的特性にも優れた半導体パッケージの製造方法および半導体パッケージを提供することができる。
第一実施形態に係る半導体パッケージの構成を示す上視平面図である。 第一実施形態に係る半導体パッケージの構成を示す側面図である。 半導体素子を、第一の電極および第二の電極が形成された第一の面側から見た上視平面図である。 図1のA-A′断面図である。 第一実施形態に係る製造方法のフローを示す図である。 噴霧工程においてシランカップリング剤を噴霧する領域およびシランカップリング剤が塗布される面を示した図である。 第二実施形態に係る半導体パッケージの構成を示す側面図である。
〔第一実施形態〕
(半導体パッケージ)
 以下、図1から図4を参照して、本実施形態に係る半導体パッケージ30について説明する。本実施形態に係る半導体パッケージ30は、図1および図2に示すように、ダイパッド11と、半導体素子31と、リード12と、吊りリード部15と、接続部材32と、封止樹脂33と、を含む。
 ダイパッド11は、半導体素子31を搭載するための平板状の部材である。ダイパッド11は、図2に示すように、第一の主面1101と、第一の主面1101と反対側の第二の主面(上面)1102と、を有する。半導体素子31は、はんだや銀ペースト等の接合部材41を用いて、ダイパッド11の第二の主面1102に接合される。
 半導体素子31は、基材部311を含む。基材部311は、平面視矩形の板状の半導体である。基材部311は、例えば、シリコンで形成される。基材部311の表面には、無機物である半導体の酸化膜、例えばシリコン酸化膜(SiO)が形成される。図4に示すように、基材部311は、第一の主面3111と、第一の主面3111と反対側の第二の主面3112と、を含む。第二の主面3112は、ダイパッド11の第二の主面1102と対向する。
 図3および図4に示すように、半導体素子31は、ガードリング341を含む。ガードリング341は、ループ状に形成されている。ガードリング341は、例えば、アルミニウムで形成される。ガードリング341は、基材部311の第一の主面3111に設けられる。ガードリング341は、半導体素子31をスクライビングの際に生じるクラックから保護するために設けられる。ガードリング341の表面には、絶縁層342が形成される。絶縁層342は、例えば、ガードリング341の表面にTEOS(テトラエトキシシラン)の層を形成した後、TEOSの層の上に有機物の層を積層することによって作製される。有機物は、例えばポリイミドである。絶縁層342の表面は、有機物によって構成されている。
 半導体素子31は、電極部312を含む。電極部312は、半導体素子31とリード12とを電気接続するために設けられる、板状の金属部材である。電極部312は、基材部311の第一の主面3111のうち、平面視でガードリング341に囲まれた部分に設けられる。
 電極部312は、金属で形成される。電極部312は、例えば、アルミニウムで形成される。電極部312の表面には、金属酸化物、例えば酸化アルミニウム(Al)の膜が形成されている。電極部312は、例えば、第一の電極3121と、第二の電極3122と、を含む。
 以下、半導体素子31の表面のうち、接続部材32が接合される半導体素子31の面を、第一の面3101と称する。第一の面3101は、半導体素子31における第一の主面3111側の最表面にある。第一の面3101には、基材部311の第一の主面3111、絶縁層342の表面および電極部312の表面が含まれる。基材部311の表面は、半導体や半導体の酸化膜等の無機物によって構成され、絶縁層342の表面はポリイミドなどの有機物からなる有機膜によって構成され、電極部312の表面は金属や金属酸化物等の無機物で構成されている。よって、第一の面3101は、有機物が露出した第一の領域34と、無機物が露出した第二の領域35と、を含む。
 第一の領域34は、絶縁層342の表面を含む。第二の領域35は、電極部312の表面と、基材部311の第一の主面3111を含む。なお、電極部312の表面に有機膜が形成された部分があってもよい。この場合、第一の領域34は、電極部312上に設けられた有機物の表面を含む。電極部312の表面の少なくとも一部は、第二の領域35に含まれる。
 接続部材32は、例えば、図1および図2に示すように、ボンディングワイヤーである。ボンディングワイヤーは、電極部312と同じ無機物、例えば、アルミニウムで形成される。接続部材32は、第一の接続部材321aと、第二の接続部材322aと、を含む。
 第一の電極3121の第二の領域35に含まれる部分の表面には、ワイヤーボンディングによって、第一の接続部材321aが接合される。第二の電極3122の第二の領域35に含まれる部分の表面には、ワイヤーボンディングによって、第二の接続部材322aが接合される。
 第一の電極3121の第二の領域35に含まれる部分の表面には、ワイヤーボンディングによって、第一の接続部材321aが接合される。第二の電極3122の第二の領域35に含まれる部分の表面には、ワイヤーボンディングによって、第二の接続部材322aが接合される。
 半導体素子31は、図2および図4に示すように、第三の電極313を含む。第三の電極313は、基材部311の第二の主面3112に形成される。半導体素子31は、例えば、バイポーラトランジスタであり、第一の電極3121はゲート電極、第二の電極3122はソース電極、第三の電極313はドレイン電極である。
 リード12は、第一の端部17と、第二の端部18を含む。第一の端部17には、接続部材32が接続される。リード12の第一の端部17には、例えばニッケルめっきが施されている。
 リード12は、平面視したダイパッド11の一端側に間隔をあけて配されている。リード12は、ダイパッド11の主面1101,1102に沿ってダイパッド11の一端から離れる方向に延びて形成されている。リード12の長手方向の両端部のうち、ダイパッド11に隣り合う端部は、第一の端部17である。ダイパッド11から離れて位置する端部は、第二の端部18である。
 リード12は、平面視したダイパッド11の一端側に間隔をあけて配されている。リード12は、ダイパッド11の主面1101,1102に沿ってダイパッド11の一端から離れる方向に延びて形成されている。リード12の長手方向の両端部のうち、ダイパッド11に隣り合う端部は、第一の端部17である。ダイパッド11から離れて位置する端部は、第二の端部18である。
 図1に戻って、吊りリード部15は、ダイパッド11の一端からリード12の長手方向に延びる。吊りリード部15は、例えば、ドレイン線である。吊りリード部15は、ダイパッド11を介して、第三の電極313と電気接続されている。
 ダイパッド11、リード12、吊りリード部15は、封止樹脂33によって封止される。リード12の第一の端部17は、封止樹脂33により封止されている。リード12の第二の端部18は、封止樹脂33から延出している。また、ダイパッド11の第一の主面1101は、封止樹脂33の外部に露出している。
 封止樹脂33には、シランカップリング剤が含まれている。封止樹脂33に含まれるシランカップリング剤は、例えば、封止樹脂33を硬化する際の硬化促進剤や、封止樹脂33とダイパッド11および半導体素子31との密着性を高める密着性向上剤として機能する。なお、封止樹脂33が含むシランカップリング剤は、例えば、後述する表面処理で用いられるシランカップリング剤とは異なるシランカップリング剤が用いられるが、表面処理で用いられるシランカップリング剤と同じシランカップリング剤であってもよい。
 ダイパッド11、半導体素子31、接続部材32、リード12および吊りリード部15の表面は、半導体素子がダイパッドに接合されると共に半導体素子及びリードが接続部材によって接続された状態でシランカップリング剤によって表面処理され、封止樹脂33との接合強度が高められている。シランカップリング剤の分子は、末端が有機材料と化学結合する第一の官能基、および、末端が無機材料と化学結合する第二の官能基の、二種類の官能基が、シリコン原子に結合した構造を有する。第二の官能基は、例えば、加水分解によって無機材料表面の水酸基と脱水縮合することにより、無機材料と結合する。よって、シランカップリング剤を用いて、有機材料である封止樹脂33と、無機材料であるダイパッド11等とを結合させることが可能である。シランカップリング剤としては、3-メルカプトプロピルトリメトキシシランや3-アクリロキシプロピルトリメトキシシラン等、公知のものを用いることができる。
(製造方法)
 以下、主に図5および図6を参照して、本実施形態に係る製造方法について説明する。
 半導体パッケージ30を製造する際には、図1に示したダイパッド11、リード12および吊りリード部15を有するリードフレームを準備する。リードフレームは、ダイパッド11および複数のリード12を一体に連結する連結フレーム部(図示略)をさらに含む。リードフレームは、例えば銅板のように導電性を有する板材にプレス加工を施すことで得られる。
 本実施形態の製造方法では、吊りリード部15を折り曲げて、リード12に対してダイパッド11をその厚さ方向にずらす。これにより、リード12はダイパッド11の第二の主面1102よりも上方に位置する(図2参照)。
(搭載工程S1)
 図5に示すように、本実施形態の半導体パッケージ30の製造方法では、まず、ダイパッド11の第二の主面(上面)1102に、半導体素子31を搭載する(図1および図2参照)。
 搭載工程S1においては、図1および図2に示すように、半導体素子31をダイパッド11の第二の主面(上面)1102の上に載置する。半導体素子31は、基材部311の第二の主面3112がダイパッド11の第二の主面1102と対向するように載置される。半導体素子31の第一の面3101の反対側の面である第二の面3102に形成された第三の電極313を、はんだや銀ペースト等の接合部材41によって、ダイパッド11の第二の主面1102に接合する。はんだを用いた接合は、例えば、リフロー方式により行われる。接合部材により、第三の電極313は、ダイパッド11と電気接続される。
(接続工程S2)
 次に、図5に示すように、半導体素子31とリード12とを、接続部材32によって電気的に接続する。接続工程では、接続部材32の両端を、半導体素子31及びリード12に接続する(図1および図2参照)。
 接続工程S2においては、図1および図2に示すように、第一のボンディングワイヤー321aによって、半導体素子31の第一の電極3121と第一のリード121とを接続する。また、第二のボンディングワイヤー322aによって、半導体素子31の第二の電極3122と第二のリード122とを接続する。
(表面処理工程S3)
 次に、図5に示すように、ダイパッド11、半導体素子31、接続部材32、リード12および吊りリード部15の表面をシランカップリング剤によって表面処理する(図1および図2参照)。表面処理工程S3は、例えば、噴霧工程S31と、加熱工程S32と、をこの順に含む。
 噴霧工程S31においては、シランカップリング剤をエタノール、メタノール、イソプロピルアルコール等で希釈して得られる溶液を、例えばダイパッド11の第二の主面1102側から、ダイパッド11、半導体素子31、接続部材32、リード12、および吊りリード部15の表面に噴霧する。噴霧する領域は、図6(a)に点線で示すように、封止樹脂33(図1参照)で封止される面全域が含まれる領域Aである。その結果、図6(b)中に太線で示すように、ダイパッド11の表面、半導体素子31の基材部311の表面および電極部312の表面、接続部材32の上側表面、リード12の第一の端部17、吊りリード部15の上側表面に、シランカップリング剤が塗布される。この方法により、ダイパッド11、半導体素子31、接続部材32およびリード12の表面を無駄なく効率的に表面処理することができる。
 本実施形態では、基材部311は、シリコンで形成される。このため、基材部311の表面は、酸化シリコン(SiO)の膜が形成されている。また、電極部312は、アルミニウムで形成される。このため、電極部312の表面には、酸化アルミニウム(Al)の膜が形成されている。
 本実施形態の半導体モジュールによれば、第二実施形態と同様の効果を奏する。
 他方、有機物が表面に露出した第一の領域34には、基材部311や電極部312を含む第二の領域35と比べて、水酸基の末端の露出する本数が少ない。このため、第一の領域34には、シランカップリング剤の第二の官能基が結合しにくい。したがって、封止樹脂33と第一の領域34との接合強度は、封止樹脂33と第二の領域35との接合強度に比べて弱い。
 温度サイクル試験、断続動作試験等の信頼性試験を行ったときに、半導体素子31は外部から加熱され、あるいは自ら発熱する。発生した熱により、半導体素子31や封止樹脂33は熱膨張するが、熱膨張係数の差によって、電極部312や基材部311を含む第二の領域35と、第二の領域35と強固に結合した封止樹脂33との界面で、大きな応力が発生する。
 他方、封止樹脂33と第一の領域34との接合強度は、封止樹脂33と第二の領域35との接合強度に比べて弱いため、第一の領域34と封止樹脂33との界面では、大きな応力は発生しない。このため、半導体素子31の第二の領域35と封止樹脂33との界面で発生した応力は、第一の領域34に対応する半導体素子や封止樹脂の部分において緩和される。その結果、第二の領域35に応力が強く作用することを抑制することができる。
 第一の領域34を形成することによって、半導体素子31と封止樹脂33との界面で発生する応力が緩和される機構は、以下の通りである。
 半導体素子31と封止樹脂33とに熱が加わると、半導体素子31と封止樹脂33とはそれぞれ熱膨張する。熱膨張により、半導体素子31と封止樹脂33とは、それぞれ前記界面に平行な方向へ膨張する。半導体素子31と封止樹脂33とは異なる熱膨張係数を有する。このため、膨張する長さは、半導体素子31と封止樹脂33とで異なる。以下、半導体素子31は封止樹脂33よりも大きな熱膨張係数を有すると仮定する。封止樹脂33の熱膨張係数の方が大きい場合も、同様である。
 半導体素子31と封止樹脂33との接合強度が強い場合、膨張する長さがより小さい封止樹脂33は、膨張する長さがより大きい半導体素子31に追随して、前記界面に平行な方向に変位する。このため、前記界面近傍で、封止樹脂33は、封止樹脂33の変位量に比例した弾性力を受ける。変位量は、半導体素子31と封止樹脂33との、膨張する長さの差に比例する。その結果、前記界面近傍で応力が発生すると考えられる。
 半導体素子31と封止樹脂33とが膨張する長さは、熱が加わる前における半導体素子31と封止樹脂33とが接合する面の長さに比例する。したがって、半導体素子31と封止樹脂33とが接合する面が長ければ長いほど、前記界面近傍で発生する応力は大きくなる。
 熱が加わる前の状態で、半導体素子31と封止樹脂33とが接合する面の一部に、第一の領域34を形成する。第一の領域34では、半導体素子31と封止樹脂33との接合強度が弱いため、封止樹脂33が半導体素子31に追随して変位し難くなる。このため、半導体素子31と封止樹脂33とが接合する面の長さは、実質的に短くなる。その結果、前記界面近傍で発生する応力を、より小さくすることができる。
 以上が、第一の領域34を形成することによって応力が緩和される機構である。
 また、基材部311および電極部312は、封止樹脂との結合力が強いので、基材部311と電極部312が全て封止樹脂33から剥離する惧れは少ない。よって、半導体素子31と封止樹脂33との密着力を大きく損なわずに、半導体素子31の電気的特性を高めることができる。
 また、第一の領域34と封止樹脂33との接合強度は、電気接続部の表面と封止樹脂33との接合強度よりも弱い。これにより、電極部312に接合する接続部材32を、剥離しないように保護することができる。これにより、半導体素子31と接続部材32との接続信頼性を高めることができる。
 また、本実施形態では、第一の領域34はループ状に形成されている。この構成により、半導体素子31と封止樹脂33との熱膨張係数の相違に基づいて生じた応力が、第一の面3101面内のいずれの方向に向かっていても、生じた応力を第一の領域34に対応する半導体素子や封止樹脂の部分において緩和することができる。
 また、接合部材41には、無機物が表面に露出した第二の領域35やダイパッド11の上面と比べて、水酸基の末端の露出する本数が少ないため、シランカップリング剤の水酸基末端が結合し難い。このため、封止樹脂33と接合部材41との接合強度は、封止樹脂33と第二の領域35との接合強度や、封止樹脂33とダイパッド11との接合強度に比べて弱い。このため、半導体素子31やダイパッド11と封止樹脂33との熱膨張係数の差に起因して、半導体素子31とダイパッド11との間で生ずる応力を、接合部材41の表面において緩和することができる。これにより、半導体素子31やダイパッド11と封止樹脂33との密着力を大きく損なわずに、接合部材41におけるクラックの発生を抑制することができる。その結果、半導体素子31の電気的特性を高めることができる。
 なお、基材部311を形成する材料、および電極部312を形成する材料は、上述の組み合わせに限られない。半導体材料および金属材料は適宜選択可能であり、また、材料の特性に応じて適宜表面処理を行うことで、表面の水酸基の個数を制御することも可能である。このため、様々な材料の組み合わせに対して、電極部312と封止樹脂33との接合強度を、基材部311と封止樹脂33との接合強度より弱くすることが可能である。
 加熱工程S32においては、前記溶液噴霧後のリードフレームを加熱する。加熱工程S32では、例えば、25℃~250℃(より好ましくは50℃~150℃)の温度で前記溶液噴霧後のリードフレームを加熱する。加熱温度が比較的低いため、電極部においてシランカップリング剤の脱水縮合反応が進行し難くなる。そのため、電極部312と封止樹脂33との密着力が過度に強くなることが抑制される。
(封止工程S4)
 次に、図5に示すように、ダイパッド11、半導体素子31、接続部材32、リード12および吊りリード部15を、封止樹脂33で封止する。封止工程を行う際には、あらかじめ、半導体パッケージ30の外側の形状にあわせて作製されたモールド金型(図示略)を準備する。封止工程S4においては、ダイパッド11、半導体素子31、接続部材32、リード12および吊りリード部15を、モールド金型に設置する。その上で、モールド金型に、封止樹脂33を流し込み硬化させる。
 本実施形態では、封止樹脂33には、シランカップリング剤が含まれる。この構成によれば、封止樹脂33に含まれるシランカップリング剤が密着付与剤としての機能を有するので、封止樹脂33とダイパッド11および半導体素子31との密着力が大きくなる。また、封止樹脂33に含まれるシランカップリング剤は、封止樹脂33を硬化する際の硬化促進剤等として利用される場合があり、表面処理工程S3で用いられるシランカップリング剤とは、必ずしも求められる機能は一致しない。封止樹脂33に含まれるシランカップリング剤と表面処理工程S3で用いられるシランカップリング剤とが異なれば、それぞれに求められる機能に応じて適切なシランカップリング剤を選択することができる。
 以上の封止工程S4により、吊りリード部15のダイパッド側の一端を除く連結フレーム部(図示略)、および、リード12の第二の端部18が、封止樹脂33の外側に配される。
 封止工程S4の後には、吊りリード部15の一端部を除く連結フレーム部を切り落とす。また、必要に応じて、各リード12の第二の端部18に折り曲げ加工を施す。これにより、図1および図2に示す半導体パッケージ30が得られる。なお、図示例では、第一の主面1101が露出するように封止樹脂33が形成されているが、第一の主面1101が封止樹脂33に埋没するようにリードフレームおよびモールド金型を設計してもよい。
 以上、本発明の第一の実施形態について説明した。本実施形態では、ダイパッド11と半導体素子31の表面がシランカップリング剤によって表面処理されるので、ダイパッド11と封止樹脂33との密着力だけでなく、半導体素子31と封止樹脂33との密着力も高まる。よって、温度サイクル試験等を行っても、半導体素子31と封止樹脂33との間に剥離が生じ難くなり、半導体素子31とダイパッド11とを接続する接合部材41においてクラックの発生を抑制できる。
 また、第一の領域34と封止樹脂33との密着力が、電極部312や基材部311と封止樹脂33との密着力よりも弱いので、信頼性試験を行ったときに、半導体素子31の第二の領域35と封止樹脂33との界面で生じた応力は、第一の領域34に対応する半導体素子や封止樹脂の部分で緩和される。よって、封止樹脂33の内部に発生した応力が電極部312に強く作用することを抑制できる。一方、基材部311および電極部312は、封止樹脂33との結合力が強いので、基材部311と電極部312が全て封止樹脂33から剥離する惧れは少ない。よって、半導体素子31と封止樹脂33との密着力を大きく損なわずに、半導体素子31の電気的特性を高めることができる。
 以上より、本実施形態によれば、ダイパッド11および半導体素子31と封止樹脂33との密着力が高く、半導体素子31の電気的特性にも優れた半導体パッケージ30を提供することができる。
〔第二実施形態〕
 以下、図7を参照して、本実施形態に係る半導体パッケージ30bについて説明する。以下、図1から図6までと同じ構成要素には同じ符号を付し、説明を省略する。
 図7に示すように、本実施形態では、接続部材32はボンディングワイヤーではなく、クリップ接続子である。この点において、第一の実施形態と異なる。
 クリップ接続子は、帯板状の接続部材であり、導電性の板材を折り曲げて形成される。クリップ接続子の一端の面は、はんだや銀ペースト等の接合部材を介してリード12の第一の端部17の面と接合する。クリップ接続子の他端の面は、はんだや銀ペースト等の接合部材を介して電極部312の面と接合する。
 クリップ接続子は、例えば、第一のクリップ接続子(図示略)と、第二のクリップ接続子322bと、を含む。第一の電極3121(図1および図2参照)は、第一のクリップ接続子と接続される。第二の電極3122は、第二のクリップ接続子322bと接続される。
 本実施形態の半導体パッケージ30bは、第一の実施形態と同様の製造方法によって製造される。本実施形態によれば、第一の実施形態と同様の効果を奏する。
 以上、添付図面を参照しながら本発明に係る好適な実施の形態例について説明したが、本発明はかかる例に限定されないことは言うまでもない。上述した例において示した各構成部材の諸形状や組み合わせ等は一例であって、本発明の主旨から逸脱しない範囲において設計要求等に基づき種々変更可能である。
 以下、実施例を用いて、本発明についてより詳細に説明する。ただし本発明は、以下に示す実施例によって何ら限定されるものではない。
〔実施例〕
 封止樹脂(エポキシ樹脂)を用いて、半導体パッケージを製造した。製造過程で、上述の表面処理工程を行った。噴霧するシランカップリング剤として、3-メルカプトプロピルトリメトキシシランを用いた。
 上述のように製造した半導体パッケージのサンプルに対し、前処理を行った後に、温度サイクル試験を行った。前処理は、以下の3つの処理を、この順に行った。
(前処理1)Ta(周囲温度)=125℃、24時間
(前処理2)Ta=85℃、RH(相対湿度)=85%、168時間
(前処理3)IRリフロー(260℃、2サイクル)
 温度サイクル試験は、以下の条件で行った。
(条件)最低保存温度=-55℃、最高保存温度=150℃、1000サイクル
 上記の条件で、それぞれ同数のサンプルに対して温度サイクル試験を行い、半導体パッケージの熱抵抗特性の変動を評価した。
〔比較例〕
 半導体パッケージを、上記表面処理を行わずに製造した。その他の製造条件は、実施例と同じである。比較例についても、実施例と同じ温度サイクル試験を行い、熱抵抗特性の変動を評価した。
〔試験結果〕
 表面処理を行った実施例では、1000サイクル終了時点まで不良品が発生しなかった。これに対し、表面処理を行わなかった比較例では、300サイクル終了時点で既に不良品が発生し、1000サイクル終了時点において、比較例で発生した不良品は全サンプルの77%であった。
 以上に示したように、表面処理を行った実施例では、不良品が発生せず、表面処理を行わなかった比較例は、不良品が発生した。これらの結果から、本発明を用いて、ダイパッドおよび半導体素子と封止樹脂との密着力を高めるとともに、半導体素子と接続部材との間の接続信頼性も向上することができることが示唆される。
11 ダイパッド
12 リード
31 半導体素子
32 接続部材
33 封止樹脂
30 半導体パッケージ
312 電極部
34 第一の領域
35 第二の領域
41 接合部材
S1 搭載工程
S2 接続工程
S3 表面処理工程
S31 噴霧工程
S32 加熱工程
S4 封止工程

Claims (11)

  1.  ダイパッドの上面に半導体素子を接合する搭載工程と、前記半導体素子とリードとを接続部材によって電気接続する接続工程と、前記ダイパッド、前記半導体素子、前記接続部材および前記リードの表面をシランカップリング剤によって表面処理する表面処理工程と、前記ダイパッド、前記半導体素子、前記接続部材および前記リードを封止樹脂で封止する封止工程と、をこの順に含み、
     前記半導体素子の表面のうち前記接続部材が接合される前記半導体素子の第一の面は、有機物が露出した第一の領域と、無機物が露出した第二の領域と、を含み、
     前記第一の領域と前記封止樹脂との接合強度は、前記第二の領域と前記封止樹脂との接合強度よりも弱い
     半導体パッケージの製造方法。
  2.  前記半導体素子の前記第一の面には、前記接続部材と電気接続される電極部が設けられ、
     前記電極部と前記接続部材とにより電気接続部が構成されており、
     前記電気接続部の表面は、無機物によって構成され、
     前記第一の領域と前記封止樹脂との接合強度は、前記電気接続部の表面と前記封止樹脂との接合強度よりも弱い
     請求項1に記載の半導体パッケージの製造方法。
  3.  前記搭載工程において、前記ダイパッドと前記半導体素子とを接合部材を用いて接合し、
     前記表面処理工程において、前記接合部材の表面を前記シランカップリング剤によって表面処理し、
     前記第二の領域と前記封止樹脂との接合強度は、前記接合部材と前記封止樹脂との接合強度よりも強く、
     前記ダイパッドの前記上面と前記封止樹脂との接合強度は、前記接合部材と前記封止樹脂との接合強度よりも強い
     請求項1または2に記載の半導体パッケージの製造方法。
  4.  前記表面処理工程は、前記ダイパッド、前記半導体素子、前記接続部材および前記リードの表面に前記シランカップリング剤を含む溶液を噴霧する噴霧工程と、前記溶液を加熱する加熱工程と、をこの順に含む
     請求項1から3のいずれか1項に記載の半導体パッケージの製造方法。
  5.  前記加熱工程では、前記ダイパッドおよび前記リードを含むリードフレームを25℃~150℃の温度で加熱する
     請求項4に記載の半導体パッケージの製造方法。
  6.  前記封止樹脂には、シランカップリング剤が含まれている
     請求項1から5のいずれか1項に記載の半導体パッケージの製造方法。
  7.  ダイパッドと、前記ダイパッドの上面に接合された半導体素子と、リードと、前記半導体素子と前記リードとを接続する接続部材と、前記ダイパッド、前記半導体素子、前記接続部材および前記リードを封止する封止樹脂と、を含み、
     前記ダイパッド、前記半導体素子、前記接続部材および前記リードの表面は、シランカップリング剤によって表面処理され、
     前記半導体素子の表面のうち前記接続部材が接合される前記半導体素子の前記第一の面は、有機物が露出した第一の領域と、無機物が露出した第二の領域と、を含み、
     前記第一の領域と前記封止樹脂との接合強度は、前記第二の領域と前記封止樹脂との接合強度よりも弱い
     半導体パッケージ。
  8.  前記半導体素子の前記第一の面には、前記接続部材と電気接続される電極部が設けられ、
     前記電極部と前記接続部材とにより電気接続部が構成されており、
     前記電気接続部の表面は、無機物によって構成され、
     前記第一の領域と前記封止樹脂との接合強度は、前記電気接続部の表面と前記封止樹脂との接合強度よりも弱い
     請求項7に記載の半導体パッケージ。
  9.  前記第一の領域は、ループ状に形成されている
     請求項7または8に記載の半導体パッケージ。
  10.  前記ダイパッドと前記半導体素子とは、接合部材を用いて接合され、
     前記接合部材の露出した表面は、前記シランカップリング剤によって表面処理されており、
     前記第二の領域と前記封止樹脂との接合強度は、前記接合部材と前記封止樹脂との接合強度よりも強く、
     前記ダイパッドの前記上面と前記封止樹脂との接合強度は、前記接合部材と前記封止樹脂との接合強度よりも強い
     請求項7から9のいずれか1項に記載の半導体パッケージ。
  11.  前記封止樹脂には、シランカップリング剤が含まれている
     請求項7から10のいずれか1項に記載の半導体パッケージ。
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11297730A (ja) * 1998-04-08 1999-10-29 Denso Corp 半導体装置及び半導体装置の製造方法
JP2001118885A (ja) * 1999-10-21 2001-04-27 Matsushita Electric Ind Co Ltd 電子部品の実装方法及び基板モジュール
JP2005072306A (ja) 2003-08-26 2005-03-17 Kobe Steel Ltd 電子部品用金属板・条材及びその製造方法
JP2005226096A (ja) 2004-02-10 2005-08-25 Kobe Steel Ltd 電子部品用銅又は銅合金板・条材及びその製造方法
JP2005340474A (ja) 2004-05-26 2005-12-08 Matsushita Electric Ind Co Ltd リードフレームとその製造方法
JP2006319109A (ja) * 2005-05-12 2006-11-24 Matsushita Electric Ind Co Ltd 半導体装置用リードフレームおよびそれを用いた半導体装置用パッケージとその製造方法
JP2011082389A (ja) 2009-10-08 2011-04-21 Shindengen Electric Mfg Co Ltd 半導体パッケージ及びその製造方法
JP2012023233A (ja) * 2010-07-15 2012-02-02 Mitsubishi Electric Corp 半導体装置および半導体装置の製造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6331149A (ja) * 1986-07-25 1988-02-09 Fujitsu Ltd 半導体装置
JPH06350000A (ja) * 1993-06-04 1994-12-22 Hitachi Ltd リードフレームの表面処理剤およびそれを用いた半導体集積回路装置の製造方法
US5641997A (en) * 1993-09-14 1997-06-24 Kabushiki Kaisha Toshiba Plastic-encapsulated semiconductor device
JP3417079B2 (ja) 1994-08-31 2003-06-16 ソニー株式会社 半導体装置の製造方法
KR100374872B1 (ko) * 1997-07-18 2003-03-04 히다찌 가세이 고오교 가부시끼가이샤 구멍을 갖는 반도체용 접착테이프, 접착테이프가 부착된 리드프레임의 제조방법, 접착테이프가 부착된 리드프레임 및 이를 사용한 반도체장치
JP3432708B2 (ja) * 1997-07-31 2003-08-04 株式会社東芝 半導体装置と半導体モジュール
US6700185B1 (en) * 1999-11-10 2004-03-02 Hitachi Chemical Co., Ltd. Adhesive film for semiconductor, lead frame and semiconductor device using the same, and method for manufacturing semiconductor device
JP2003046034A (ja) * 2001-07-31 2003-02-14 Nec Kagobutsu Device Kk 樹脂封止型半導体装置
WO2004075293A1 (ja) * 2003-02-19 2004-09-02 Hitachi Chemical Co., Ltd. 半導体用接着フィルム、これを用いた接着フィルム付金属板、接着フィルム付配線回路及び半導体装置並びに半導体装置の製造方法
JP4225183B2 (ja) * 2003-11-05 2009-02-18 株式会社デンソー 半導体装置の製造方法
JP2005203548A (ja) * 2004-01-15 2005-07-28 Honda Motor Co Ltd 半導体装置のモジュール構造
JP5719167B2 (ja) * 2010-12-28 2015-05-13 ルネサスエレクトロニクス株式会社 半導体装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11297730A (ja) * 1998-04-08 1999-10-29 Denso Corp 半導体装置及び半導体装置の製造方法
JP2001118885A (ja) * 1999-10-21 2001-04-27 Matsushita Electric Ind Co Ltd 電子部品の実装方法及び基板モジュール
JP2005072306A (ja) 2003-08-26 2005-03-17 Kobe Steel Ltd 電子部品用金属板・条材及びその製造方法
JP2005226096A (ja) 2004-02-10 2005-08-25 Kobe Steel Ltd 電子部品用銅又は銅合金板・条材及びその製造方法
JP2005340474A (ja) 2004-05-26 2005-12-08 Matsushita Electric Ind Co Ltd リードフレームとその製造方法
JP2006319109A (ja) * 2005-05-12 2006-11-24 Matsushita Electric Ind Co Ltd 半導体装置用リードフレームおよびそれを用いた半導体装置用パッケージとその製造方法
JP2011082389A (ja) 2009-10-08 2011-04-21 Shindengen Electric Mfg Co Ltd 半導体パッケージ及びその製造方法
JP2012023233A (ja) * 2010-07-15 2012-02-02 Mitsubishi Electric Corp 半導体装置および半導体装置の製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3203510A4

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102023105517A1 (de) 2022-04-06 2023-10-12 Mitsubishi Electric Corporation Verfahren zum Herstellen einer Halbleitervorrichtung und Halbleitervorrichtung

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EP3203510A1 (en) 2017-08-09
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