CN1806342A - 在集成soi工艺中防止寄生沟道 - Google Patents

在集成soi工艺中防止寄生沟道 Download PDF

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CN1806342A
CN1806342A CNA2004800162015A CN200480016201A CN1806342A CN 1806342 A CN1806342 A CN 1806342A CN A2004800162015 A CNA2004800162015 A CN A2004800162015A CN 200480016201 A CN200480016201 A CN 200480016201A CN 1806342 A CN1806342 A CN 1806342A
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T·勒塔维
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Koninklijke Philips NV
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/78654—Monocrystalline silicon transistors

Abstract

公开了一种绝缘体上的硅器件，其中通过在源或漏下面的深N注入阻止了在器件的薄膜部分感应出的寄生沟道(110)使得电流在源(101)和漏(101)之间流动。深N注入阻止了耗尽区的形成，由此切断了可能发生的电流在源(101)和漏(101)之间流动。

Description

在集成SOI工艺中防止寄生沟道
技术领域
本发明涉及一种CMOS器件，更具体地涉及一种消除薄膜CMOS器件中设置在源区的寄生MOS沟道的技术，或称作源跟随结构。本发明还公开了为了有效完成发明的结构，进行深N离子注入的方法。虽然大部分应用在PMOS器件中，本发明也可以在NMOS结构中使用。
背景技术
图1示出了包括源101、漏102和MOS栅区103的薄膜CMOS器件。SOI层104形成具有埋入氧化层106的MOS结105。衬底层107在埋入氧化层106下面，衬底层典型地为几百微米厚。在图1中示出的尺寸上，衬底层107太厚了而不能描绘，因此没有完全示出。
在源跟随模式下，有时称作源高模式，通过典型地高于衬底107保持电压的电压为源101加偏压。在典型的应用中，这个电压差可以超过两百伏特。在SOI层104可以仅仅稍微比一微米厚度更厚的薄膜器件中，这个电压差可以足够在MOS结105或附近感应出不希望的耗尽区。因此如图1中所示，在MOS结处存在在源101和漏102之间的寄生通道110。这个区产生了寄生MOS沟道，使得当真实的MOS栅区103倾向于关闭时，漏电流在源101和漏101之间传输。该器件由此不希望地工作就好像第二栅区存在，其中第二栅极在接通状态，即使当实际栅区103处于关闭状态。
在目前为止，当在源跟随结构中使用薄膜SOI器件时，没有已知方法能用于停止这个漏电流。现有解决方法都包括使用更厚的SOI层104，而不是薄膜器件。这些现有器件具有如此厚的SOI层以使得不会在寄生MOS沟道110中产生耗尽区。然而，在薄膜应用中该区110用作除了常规栅区的第二电流通路。
在具有薄膜SOI器件的源跟随结构中需要用于消除这个寄生沟道110的技术。
在互补结构中(即使用NMOS器件，其中源的偏压远远低于衬底)，可能存在类似的结构。
附图简介
图1是现有技术中CMOS薄膜器件的描述图，示出了寄生MOS沟道110；
图2是根据本发明制造的器件的示意性描述图。
图3A-D描述了贯穿器件在不同位置处的掺杂浓度。
优选实施例的详细描述
图2描述了包括设置在源区101下的深N层201的典型PMOS器件。衬底区107保持示例性的-200伏特的电压，低于源偏置的电压超过200伏特。由于相对薄的SOI层104，(稍微大于1微米)，寄生MOS沟道110由如图1中所示在漏102和源101之间形成的耗尽区产生。然而，所示的直接位于源区101下的深N层201阻止了完全耗尽，而改为形成如图2中虚线所示的空间电荷中性区205。这个空间电荷中性区205阻止了在源101和漏102之间的电流沿着可能跨过MOS沟道110形成的任何寄生沟道流动。
在优选实施例中，深N层201的注入应当使用31P++和200KeV注入机器的双重离子注入完成。这在不需要高能量注入机器的情况下给出了400KeV的注入能量。
也应当注意在图2中在源区101下示出了深N层，应当注意空间电荷中性区205可以沿着可能成为在源101和漏102之间的寄生电流通路110的任何地方形成，因此，深N层201可以直接设置在漏区102下面，而不是源区101下面。
当器件在源高PMOS结构中有主要应用，互补器件也可以在NMOS中进行。这样的NMOS器件包括在源或漏下面的与那些已经描述的浓度类似的P注入，和可以应用于其中器件的偏压结构与这里关于PMOS器件的描述相反的配置中。
图3A-D示出了关于在PMOS器件中实施本发明的进一步制造信息。图3A描述示出了上述的器件不同部分相对厚度的剖面图。在图3A中描述的器件以图3B中描绘的浓度掺杂。注意图3C和3D比较了在源和漏区中分别存在的掺杂浓度。注意在图3D中示出的深N区的掺杂浓度比在图3B中示出用于N阱、栅区的浓度高1个数量级。
注意以上描述了实施本发明的优选实施例，多种修改和添加对于本领域的技术人员是显而易见的。这样的修改倾向于被下面所附的权利要求所覆盖。

Claims (11)

1、薄膜绝缘体的硅(SOI)器件包括源(101)，栅(103)，漏(102)，SOI层(104)和衬底层(107)，衬底层保持在比源足够低的电势，以使得寄生MOS沟道(110)在源和漏之间形成；在源或漏和寄生MOS沟道之间形成深N注入层(201)以阻止当器件处于关闭状态时在源和漏之间的电流经过寄生MOS沟道流动。
2、如权利要求1的器件，其中深N注入层(201)在源(101)和寄生MOS沟道(110)之间形成。
3、如权利要求1的器件，其中深N注入层(201)在漏(102)和寄生MOS沟道(110)之间形成。
4、薄膜绝缘体的硅(SOI)器件包括源(101)，栅(103)，漏(102)，SOI层(104)和衬底层(107)，该SOI层保持在比源(101)足够高的电势，以使得寄生MOS沟道(110)在源和漏之间形成；在源或漏和寄生MOS沟道之间形成深P注入层以阻止当器件处于关闭状态时在源(101)和漏(102)之间的电流经过寄生MOS(110)沟道流动。
5、如权利要求1的器件，其中深P注入层在源(101)和寄生MOS沟道(110)之间形成。
6、如权利要求1的器件，其中深P注入层在漏(102)和寄生MOS沟道(110)之间形成。
7、分离MOS器件的源和漏以避免寄生MOS沟道形成的方法，包括：加入注入双倍离子化的31P++，在MOS器件的漏(102)或源(101)下形成深N层(201)，由此阻止当器件处于关闭状态时电流经过在所述MOS器件中形成的寄生MOS(110)沟道流动。
8、如权利要求7的方法，其中所述器件包括埋入氧化层，和其中所述寄生MOS沟道在埋入氧化层(106)-硅层(104)的界面处或附近形成。
9、如权利要求7的方法，其中深N层(201)的掺杂浓度大约高于在器件上的N阱层的掺杂浓度一个数量级。
10、一种CMOS器件，包括：邻近埋入氧化层(106)并被栅区(103)分开的源(101)和漏(102)区，埋入氧化层邻近衬底层(107)，和直接在漏(102)或源(101)下的粒子注入层(201)，以使得在衬底和源之间的电势的差超过30伏特时，横跨栅区感应出寄生MOS沟道(110)和注入层(201)把所述寄生MOS沟道(110)从所述漏区(102)分离开以由此阻止电流在所述源(101)和漏(102)之间经过所述寄生MOS沟道(110)流动。
11、如权利要求10的器件，其中离子化粒子使用大约200KeV的能量注入。
CNA2004800162015A 2003-06-11 2004-06-08 在集成soi工艺中防止寄生沟道 Pending CN1806342A (zh)

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EP1636851A1 (en) 2006-03-22
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