CN1783479A - 互连结构及其形成方法 - Google Patents
互连结构及其形成方法 Download PDFInfo
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- CN1783479A CN1783479A CNA2005101173780A CN200510117378A CN1783479A CN 1783479 A CN1783479 A CN 1783479A CN A2005101173780 A CNA2005101173780 A CN A2005101173780A CN 200510117378 A CN200510117378 A CN 200510117378A CN 1783479 A CN1783479 A CN 1783479A
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- hard mask
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- interconnection structure
- dielectric material
- dielectric
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
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- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
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- Spectroscopy & Molecular Physics (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
OMCATSHM1300mm | OMCATSHM2300mm | OMCATSHM3300mm | OMCATSHM4200mm* | |
OMCATS流速(mgm) | 2000 | 2500 | 2800 | 1800 |
O2流速(sccm) | 0 | 160 | 220 | 0 |
He载体流速(sccm) | 1000 | 1000 | 1000 | 500 |
温度(℃) | 350 | 350 | 350 | 350 |
气压(托) | 5 | 5 | 5 | 5 |
距离(毫英寸) | 450 | 450 | 450 | 450 |
HF功率(W) | 500 | 500 | 400 | 500 |
LF功率(W) | 0 | 150 | 60 | 75 |
Claims (29)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/981,233 | 2004-11-04 | ||
US10/981,233 US7335980B2 (en) | 2004-11-04 | 2004-11-04 | Hardmask for reliability of silicon based dielectrics |
Publications (2)
Publication Number | Publication Date |
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CN1783479A true CN1783479A (zh) | 2006-06-07 |
CN100388477C CN100388477C (zh) | 2008-05-14 |
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CNB2005101173780A Expired - Fee Related CN100388477C (zh) | 2004-11-04 | 2005-11-03 | 互连结构及其形成方法 |
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US (3) | US7335980B2 (zh) |
CN (1) | CN100388477C (zh) |
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2004
- 2004-11-04 US US10/981,233 patent/US7335980B2/en active Active
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2005
- 2005-11-03 CN CNB2005101173780A patent/CN100388477C/zh not_active Expired - Fee Related
-
2008
- 2008-01-18 US US12/016,594 patent/US7485582B2/en not_active Expired - Fee Related
- 2008-01-23 US US12/018,640 patent/US20080118717A1/en not_active Abandoned
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Also Published As
Publication number | Publication date |
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CN100388477C (zh) | 2008-05-14 |
US20080132055A1 (en) | 2008-06-05 |
US7485582B2 (en) | 2009-02-03 |
US20060091559A1 (en) | 2006-05-04 |
US20080118717A1 (en) | 2008-05-22 |
US7335980B2 (en) | 2008-02-26 |
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