CN1770451A - 改善芯片面积和封装引线端子数量及寄生电感的ic器件 - Google Patents

改善芯片面积和封装引线端子数量及寄生电感的ic器件 Download PDF

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CN1770451A
CN1770451A CNA2005101132348A CN200510113234A CN1770451A CN 1770451 A CN1770451 A CN 1770451A CN A2005101132348 A CNA2005101132348 A CN A2005101132348A CN 200510113234 A CN200510113234 A CN 200510113234A CN 1770451 A CN1770451 A CN 1770451A
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circuit
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bonding welding
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lead
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樱井祥嗣
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Sharp Corp
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Abstract

本发明的半导体集成电路器件具有以下结构：在半导体衬底上设置的多个电路块中，对于按照彼此不是并行工作状态的第一电路块(1)和第二电路块(2)而言，共用第一电路块(1)和第二电路块(2)的GND线(G1)。而且，还电连接一个键合焊盘(PD)和GND线(G1)。因此，由于将两个电路块的GND端子设置为一个GND端子，所以就能够减少引线端子的数量。

Description

改善芯片面积和封装引线端子数量及寄生电感的IC器件
发明领域
本发明涉及一种包含例如像高频通信装置的发送系统电路及接收系统电路那样的、仅彼此任何一方工作的这种电路的半导体集成电路器件，特别地涉及一种通过焊接线进行集成电路芯片和半导体组件的电连接的半导体集成电路器件。
背景技术
通常，半导体集成电路器件的集成电路芯片(以下简称芯片)，在其上表面具有多个键合焊盘，该多个键合焊盘排列在形成于芯片上的电路的周边区域上。并且，通过焊接线电连接此键合焊盘和容纳集成电路芯片的半导体组件(以下简称组件)的引线端子，执行与外部间的信号接收或电路工作中所需电压的施加等。
另一方面，公知了电连接在键合焊盘和半导体组件的引线端子之间的焊接线所具有的寄生电感对集成电路芯片的电路特性具有较大的影响，并成为重要的课题。
作为一个例子，在发射极接地放大电路中，存在所谓的因所谓发射极负反馈、连接于供给接地电压GND的键合焊盘的焊接线所具有的寄生电感使电路特性显著劣化的问题。再有，所谓发射极负反馈是在晶体管的发射极和地之间存在阻抗成分时，因阻抗引起的负反馈而使发射极接地放大电路的互感劣化，产生功率劣化的现象。
关于此点，在特开2002-43869号公报中，公开了一种避免所谓随电感等接地阻抗增大而使放大电路的功率劣化的问题的结构。具体而言，公开了这样的结构，其中：除设置了向信号放大电路提供接地电压GND的第一端子，还设置了经电容耦合电路与接地电压GND连接的第二接地端子，设定电容耦合电路的电容值以使焊接线和电容耦合电路的阻抗关系成为按使用频率串联谐振，将接地阻抗设定为最小值，由此就不会产生功率劣化。
但是，根据上述公报的结构，确定用于减少阻抗的最佳电容值是非常困难的，且也存在所谓结构复杂化的问题。
特别地，在高频电路中，焊接线所具有的寄生电感对电路特性的影响巨大，在输入信号的使用频率的范围内即频带宽度的情况下，上述结构就会存在所谓难以获得充分效果的问题。
作为其它方式，通过并联连接多个焊接线，也能够伴随焊接线的连接而减少寄生电感。
但是，从小型化、低成本化的观点来看，常规的半导体集成电路器件会优选缩小芯片面积并减少封装的引线端子数量，上述方式存在所谓伴随键合焊盘的增加而导致芯片面积增大及封装引线端子数量增多的问题。
技术方案
为了解决上述这样的问题点而进行本发明，本发明的目的在于，提供一种通过简单的结构就能够抑制芯片面积增大、抑制封装的引线端子数量增多、并且能够减少寄生电感的半导体集成电路器件。
本发明的半导体集成电路器件包括在半导体衬底上设置的多个电路。多个电路包括彼此不并行工作的第一电路和第二电路。还包括一个共用的第一电源线，该第一电源线将电源电压及接地电压之一供给到半导体衬底上设置的第一电路和第二电路。
优选地，还包括至少与第一电源线电连接的一个键合焊盘。
特别地，还包括引线和焊接线，该引线设置在容纳半导体衬底的封装中并接收来自外部电压的供给、该焊接线电连接引线和各个至少一个键合焊盘。将电连接引线和各个至少一个键合焊盘的焊接线的条数设定为多条。
优选地，第一及第二电路中的至少一个电路中包括发射极接地放大电路。
优选地，第一电路对应于高频通信电路的接收系统电路，第二电路对应于与高频通信电路的接收系统电路的不并行工作的发送系统电路。
特别地，还包括引线和焊接线，该引线设置在容纳半导体衬底的封装中并接收来自外部电压的供给、该焊接线电连接引线和各个至少一个键合焊盘。半导体衬底包括多个键合焊盘，该多个键合焊盘包含至少一个键合焊盘。引线电连接到至少一个键合焊盘，至少一个键合焊盘比多个键合焊盘中的另一键合焊盘的焊接线长度短。
特别地，靠近至少一个键合焊盘配置第一电路和第二电路，以便缩短第一电源线的长度。
优选地，还包括一个共用的第二电源线，该第二电源线将电源电压及接地电压的另一个供给到第一电路及第二电路。
本发明的半导体集成电路器件包括一个共用的第一电源线，该第一电源线将电源电压及接地电压之一供给到彼此不并行工作的第一电路和第二电路。因此，能够减少电源线的条数、减少与电源线连接的端子数量，并且能够缩小芯片面积。
基于结合附图而进行理解的有关本发明的以下详细说明，本发明的上述和其它目的、特征、方面及优点就会变得更加明显。
附图说明
图1是根据本发明的实施例1的集成电路芯片的示意性框图。
图2是根据本发明的实施例2的集成电路芯片的示意性框图。
图3是说明根据本发明的实施例3的集成电路芯片和引线端子的关系图。
图4是根据本发明的实施例4的发射极接地放大电路的电路结构图。
图5是根据本发明的实施例5的高频通信电路的示意性框图。
图6是说明根据本发明的实施例6的集成电路芯片和引线端子的连接关系图。
图7是根据本发明的实施例7的集成电路芯片的示意性框图。
优选实施例的说明
实施例1
下面，将在实施例中描述本发明的实施方式。
参照图1，根据本发明的实施例1的集成电路芯片TP包括：第一～第四电路模块1～4；在其周边区域配置的多个键合焊盘PD；VDD线V1～V4；GND线G1、G3、G4。第一～第四电路模块1～4分别与VDD线V1～V4对应连接，接收电源电压VDD的供给。此外，第一及第二电路模块1、2共同连接到GND线G1、接收从GND线G1供给接地电压GND。此外，第三及第四电路模块3、4分别从GND线G3、G4接收接地电压GND的供给。再有，在本实施例中，省略各电路模块1～4的输入输出线。再有，VDD线及GND线是分别供给电源电压VDD及接地电压GND的电压的电源线。
在此，第一电路模块及第二电路模块彼此不是并行工作状态。第三电路模块及第四电路模块是任意工作状态。
通常，作为半导体集成电路器件的引线端子，被划分为三类：与输入输出线电连接的输入输出端子、与VDD线电连接的电源端子、与GND线电连接的GND端子。并且，考虑噪音等的影响，通常是在每一个电路模块中独立设置VDD线及GND线的结构。因此，假如增加集成电路芯片上的电路模块的数量，那么为了增加那些必要的VDD及GND线，在增大半导体集成电路器件的电路规模的同时，就还需要增加用于与线连接的键合焊盘的数量。即，必须增加与键合焊盘连接的半导体封装的引线端子数量。
但是，在包含例如像高频通信装置的发送系统电路及接收系统电路那样且仅彼此任何一方工作的这种电路的半导体集成电路器件的情况下，不工作的一方的电路就不会产生噪音。也就是说，即使共用两电路的GND线，由于仅一方工作，因而来自另一方的噪音就不会成为问题。
因此，本发明的半导体集成电路器件是这样的一种结构，即在半导体衬底上设置的多个电路模块中，对于彼此不是并行工作状态的第一电路模块和第二电路模块而言，共用第一电路模块1和第二电路模块2的GND线G1。
在本实施例中，单一的键合焊盘与GND线连接。因此，由于将两个电路模块的GND端子设为一个GND端子，因此就能够减少引线端子数量。
再有，在本实施例中，作为一个例子，虽然说明了不是彼此并行工作状态的第一电路模块和第二电路模块组，但在半导体芯片上存在多个这样相同的组的情况下，按照相同的方式，通过共用GND线，也能够相对于电路模块数量而减少GND端子数量。由此，就能够减小半导体集成电路器件的电路规模，还能够减少此部分封装的引线端子数量。
实施例2
参照图2，根据本发明的实施例2的集成电路芯片TPa与根据本发明实施例1的集成电路芯片TP相比较，不同之处在于，GND线G1与三个键合焊盘PD0～PD2连接。就其它方面而言，由于与用图1所说明的集成电路芯片TP相同，因此不重复其详细说明。再有，在各个附图中，用相同符号表示相同的部分。
按照本发明的实施例2的芯片结构，为了在多个电路模块中共用上述GND线G1，而将上述GND线G1连接到多个未使用的键合焊盘PD上，由此，在整体上不仅能够抑制GND端子数量的增加，而且能够减少因焊接线的多个连接而引起的寄生电感。
再有，在本实施例中，虽然说明了将GND线G1与三个键合焊盘PD0～PD2连接的结构，但不限定于此，可通过与更多的键合焊盘连接，以进一步减少寄生电感。
实施例3
使用图3来说明根据本发明的实施例3的集成电路芯片TPa和引线端子的关系。
参照图3，在本实施例中，示出了半导体封装的引线端子RD0～RD2。通过焊接线，半导体封装的引线端子RD0～RD2分别与键合焊盘PD0～PD2连接。并且，在本实施例中，存在多条用于电连接引线端子和相对应的键合焊盘的焊接线。在本实施例中，虽然示出了每两条焊接线与各个键合焊盘连接的例子，但不限定于两条，也可以是两条以上。
利用按照本实施例3的结构，通过增加并联连接的焊接线的条数，就能够进一步减小寄生电感。
实施例4
参照图4，根据本发明的实施例4的发射极接地放大电路10包括：双极性晶体管11、负载电感12、发射极接地放大电路10的输入端子13、发射极接地放大电路10的输出端子14、与VDD线连接的电源端子15、与GND线连接的GND端子16。
发射极接地放大电路10根据负载电感12及双极晶体管11、以规定的放大倍数放大来自输入端子13的输入信号，并输出到输出端子14。
当这种发射极接地放大电路10被设置成例如图1～图3的第一电路模块时，若将GND端子16连接到图1～图3的GND线上，就能够降低发射极接地放大电路的发射极和地之间的阻抗。因此，就能够抑制上述的发射极负反馈引起的互感的劣化，并能够以所希望的放大倍数来放大信号。
在本实施例中，彼此不是并行工作状态的第一电路模块和第二电路模块中，至少使其任意一方包括发射极接地放大电路。按照已经说明的结构，由于发射极接地放大电路对寄生电感非常敏感，作为对策，通常就需要多个GND端子，但根据本发明，就能够抑制GND端子的增加。并且，像发射极接地放大电路这样的、在必须减少寄生电感这样的电路的GND端子上并联连接由实施例3说明的多个焊接线时，就能够进一步抑制GND端子数量的增加。
实施例5
本发明的实施例5作为上述说明的半导体集成电路器件的具体结构例，适用于高频通信电路100，并对此情况进行说明。
参照图5，根据本发明的实施例5的高频通信电路100包括：低噪声放大器(LNA)20；混频器21、31；带通滤波器22、32；解调器23；功率放大器(PA)30；调制器33；PLL 40和局部振荡器(VCO)41、42。LNA 20、混频器21、带通滤波器22和解调器23构成接收系统电路模块24(以下称为接收系统电路模块24)。此外，PA30、混频器31、带通滤波器32和调制器33构成发送系统电路模块34(以下称为发送系统电路34)。发送及接收系统电路模块24、34不是并行工作状态。局部振荡器41、42及PLL40在接收和发送状态的任何状态下都处于工作状态。
此外，高频通信电路100设置有：接收系统电路模块24的输入端子50；接收系统电路模块24的输出端子56；发送系统电路模块34的输出端子52；发送系统电路模块34的输入端子54；共用LNA和PA的GND端子51；在接收及发送系统电路模块24、34中共用两个混频器21、31的GND端子53；以及共用解调器23和调制器33的GND端子55。
接着，说明高频通信电路100的工作。
高频通信电路100处于接收状态时，发送系统电路模块34处于非工作状态，接收系统电路模块24和其它电路处于工作状态。利用LNA 20放大从接收系统电路的输入端子50输入的接收信号后，通过混频器21与局部振荡器42的输出信号进行混合，朝着期望的频率进行降频变频。降频变频后的信号由带通滤波器22去除不需要的频率成分之后，根据局部振荡器41的输出信号，由解调器23进行解调，并从发送系统电路模块24的输出端子56输出。
另一方面，高频通信电路100处于发送状态时，接收系统电路模块24处于非工作状态，发送系统电路模块34和其它电路处于工作状态。根据局部振荡器41的输出信号，利用解调器33解调从发送系统电路模块的输入端子54输入的发送信号后，由带通滤波器32去除不需要的频率成分，输入到混频器31。利用混频器31将此发送信号和局部振荡器42的输出信号混合，降频变频为期望的频率，由PA30放大后，从发送系统电路的输出端子52输出。再有，PLL40将局部振荡器41、42的输出信号的振荡频率设定为期望的频率。
在本实施例中，示出了LNA 20和PA 30的组、接收系统电路模块的混频器21和发送系统电路模块的混频器31的组、解调器23和调制器33的组这三个组共用GND线的例子。具体而言，对LNA20和PA30通过GND端子51供给接地电压GND。对接收混频器21和混频器31通过GND端子53供给接地电压GND。对解调器23和调制器33通过GND端子55供给接地电压GND。在此，对于这样的三个组，虽然说明了共用GND线的结构，但不限定于此，也可为由构成不是并行工作状态的接收系统电路模块24的电路和构成发送系统电路模块34的电路的任意组共用GND线的结构。
通常，将高频通信电路集成在同一半导体衬底上时，由于存在很多电路模块，因而就需要很多的引线端子。但是，高频通信电路如上述那样，在发送状态和接收状态下电路工作有差异，由于存在上述接收系统电路模块和发送系统电路模块的组，通过共用GND线，就能够减少键合焊盘的数量，由此，作为结果，能够减少引线端子数量。
实施例6
使用图6说明根据本发明的实施例6的集成电路芯片TPb和引线端子的连接关系。
参照图6，在本实施例中，示出了引线端子RD3～RD6。而且，还示出了第一电路模块1和第二电路模块2共用的GND线G1。
如图6所示，由于焊接线的长度是由连接导线的键合焊盘和引线端子的位置来决定的，因而各条导线的长度不同。例如，连接在半导体芯片的四个角附近焊盘的导线，与其它导线相比较，有变长的趋势。为了减少寄生电感，希望尽可能地缩短焊接线。
通过连接焊接线长度为最短的位置的焊盘和共用GND线，来减少寄生电感。具体而言，使用焊接线WR连接比邻接于引线端子RD的多个焊盘中的其它焊盘的长度更短的位置的焊盘和相应的引线端子RD。
此外，半导体芯片上的GND线，由于按众所周知的情况，若长度增长时，就会增加寄生电阻、寄生电容和寄生电感，所以希望尽可能地缩短GND线的长度。
因此，靠近和引线端子RD连接的键合焊盘以缩短GND线，通过配置与GND线连接的第一及第二电路模块1、2，就能够进一步地减少寄生阻抗。
实施例7
在上述实施例中，虽然说明了通过共用GND线结构来防止GND端子数量的增加和减少寄生电感的结构，但不仅仅是GND线，也是完全适用于VDD线。
参照图7，根据本发明的实施例7的集成电路芯片TPc是将第一电路模块和第二电路模块的VDD线V1#与GND线G1同时共用的集成电路芯片。
本发明的半导体集成电路器件，共用第一电路模块和第二电路模块的VDD线。因此，通过共用VDD线就能够缩小芯片的面积和减少封装的引线端子数量。再有，该结构同样可以适用于上述实施例1～6。
如上述所说明的那样，本发明的半导体集成电路器件能够抑制芯片面积的增大和封装的引线端子数量的增多，并且能够减少寄生电感成分。
虽然详细地明示了本发明，但仅仅是示例性的，并不是限定性的，可明确理解为仅根据所附的权利要求来限定上述精神和范围。

Claims (8)

1、一种半导体集成电路器件，包括在半导体衬底上设置的多个电路，其特征在于：
上述多个电路包括彼此不并行工作的第一电路(1)和第二电路(2)；并且
该半导体集成电路器件还包括一条共用的第一电源线(G1)，该第一电源线(G1)将电源电压及接地电压之一供给到在上述半导体衬底上设置的上述第一电路和上述第二电路。
2、根据权利要求1的半导体集成电路器件，还包括与上述第一电源线电连接的至少一个键合焊盘(PD)。
3、根据权利要求2的半导体集成电路器件，还包括引线(RD)和多条焊接线(WR)，
该引线设置于容纳上述半导体衬底的封装中并接收来自外部电压的供给，该焊接线电连接上述引线和各个上述至少一个键合焊盘；并且
该多条焊接线用于电连接上述引线和各个上述至少一个键合焊盘。
4、根据权利要求2的半导体集成电路器件，还包括引线(RD)和焊接线(WR)，
该引线设置于容纳上述半导体衬底的封装中并接收来自外部电压的供给，该焊接线电连接上述引线和各个上述至少一个键合焊盘；
上述半导体衬底包括多个键合焊盘(PD)，该多个键合焊盘(PD)包含上述至少一个键合焊盘；并且
上述引线电连接到上述至少一个键合焊盘，上述至少一个键合焊盘可使上述焊接线的长度短于所述多个键合焊盘中的其它键合焊盘的焊接线的长度。
5、根据权利要求2的半导体集成电路器件，靠近上述至少一个键合焊盘配置上述第一电路和上述第二电路，以便缩短上述第一电源线的长度。
6、根据权利要求1的半导体集成电路器件，上述第一及第二电路中的至少一个电路包括发射极接地放大电路(10)。
7、根据权利要求1的半导体集成电路器件，上述第一电路对应于高频通信电路的接收系统电路(24)，上述第二电路对应于与高频通信电路的上述接收系统电路的不并行工作的发送系统电路(34)。
8、根据权利要求1的半导体集成电路器件，还包括共用的第二电源线(V1#)，该第二电源线(V1#)将上述电源电压及上述接地电压的另一个供给到上述第一电路及第二电路。
CNA2005101132348A 2004-09-02 2005-09-02 改善芯片面积和封装引线端子数量及寄生电感的ic器件 Pending CN1770451A (zh)

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CN109273424A (zh) * 2018-10-15 2019-01-25 矽力杰半导体技术(杭州)有限公司 一种封装组件

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CN102313862B (zh) * 2010-07-08 2013-09-11 上海华虹Nec电子有限公司 片上型四端口射频器件射频测试的去嵌方法
CN109273424A (zh) * 2018-10-15 2019-01-25 矽力杰半导体技术(杭州)有限公司 一种封装组件
CN109273424B (zh) * 2018-10-15 2024-02-02 矽力杰半导体技术(杭州)有限公司 一种封装组件

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