CN1759488B - 窄鳍片场效应晶体管 - Google Patents

窄鳍片场效应晶体管 Download PDF

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CN1759488B
CN1759488B CN2004800026970A CN200480002697A CN1759488B CN 1759488 B CN1759488 B CN 1759488B CN 2004800026970 A CN2004800026970 A CN 2004800026970A CN 200480002697 A CN200480002697 A CN 200480002697A CN 1759488 B CN1759488 B CN 1759488B
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fin structure
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field effect
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CN1759488A (zh
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Z·克里沃卡皮奇
J·X·安
S·达克希纳-默西
汪海宏
B·于
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GlobalFoundries US Inc
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
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    • H01L29/66818—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the channel being thinned after patterning, e.g. sacrificial oxidation on fin
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure

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Abstract

一种具有小于6纳米的沟道宽度的窄沟道鳍式场效晶体管(FinFET)。该FinFET可包含一鳍片(140)，其中是利用氨水(NH4OH)蚀刻或活性离子蚀刻(RIE)来削减该沟道区。

Description

窄鳍片场效应晶体管
技术领域
本发明大致涉及一种半导体器件及制造半导体器件的方法，更特别地，涉及双栅极金属氧化物半导体场效晶体管(Metal OxideSemiconductor Field Effect Transistor；简称MOSFET)。
背景技术
诸如MOSFET等的晶体管是大多数半导体器件的核心建构单元。诸如高性能处理器等的某些半导体器件可包含数百万个晶体管。对于这些器件而言，减小晶体管的尺寸并因而增加晶体管的密度在传统上已是半导体制造领域中的高优先项目。
传统的MOSFET在尺寸小于50纳米的制造工艺上有其困难度。为了开发小于50纳米的MOSFET，已有人提议双栅极MOSFET。在几个方面中，双栅极MOSFET提供了比传统块体(bulk)硅MOSFET更佳的性能。因为双栅极MOSFET在沟道的两边都有一栅极电极，并非是如同传统的MOSFET只在一边有栅极电极，所以有了这些改良。
发明内容
根据本发明的实施例提供了一种具有窄沟道区的双栅极MOSFET及其制造方法。
本发明的一个面向涉及一种MOSFET器件，该MOSFET器件包含在绝缘层上形成的源极及漏极结构。在该绝缘层上且在该源极与漏极之间形成一鳍片结构。该鳍片结构包含在该鳍片结构的沟道区中形成的削薄区。至少在该鳍片结构的该削薄区上形成保护层。该保护层的宽度大于该削薄区的宽度。在该鳍片结构的至少一部分周围形成介电层，且在该介电层及该鳍片结构周围形成栅极。
本发明的另一面向涉及一种形成MOSFET器件的方法。该方法包含下列步骤：在绝缘层上形成源极、漏极、和鳍片结构。该鳍片结构的各部分用来作为该MOSFET的沟道。该方法进一步包含下列步骤：在该鳍片结构上形成保护层；以及将该鳍片结构削减到大约3纳米至6纳米的宽度，但并不显著地削减该保护层。该方法进一步包含下列步骤：在该鳍片结构周围生长介电层；以及在该介电层周围沉积多晶硅层。该多晶硅层用来作为该MOSFET的栅极区。
附图说明
以下将参照附图进行说明，而在所有的附图中，具有相同参考标记的组件可代表类似的组件。
图1及图2是形成根据本发明的各方面的FinFET的剖面图；
图3是图2所示FinFET的透视图；
图4是图3所示FinFET的俯视图；
图5是沿着图4中的A-A’线的剖面图；
图6是图3所示FinFET的俯视图；
图7是沿着图4中的A-A’线的剖面图；
图8是图7所示FinFET的俯视图；
图9及图10是FinFET的剖面图；
图11是完成的FinFET的俯视图；
图12至图15是根据本发明的第二实施例的FinFET的剖面图；以及
图16至图18是在硅锗层周围建构的双栅极FinFET的剖面图。
具体实施方式
下文中将参照各附图对本发明进行详细说明。可将相同的参考标记用于不同的附图，以便识别相同的或类似的组件。此外，下文中的详细说明并非对本发明加以限制。应以最后的权利要求及其等效范围来界定本发明的范围。
作为本文所使用名词的FinFET意指一种在垂直硅“鳍片”中形成导电沟道的MOSFET。FinFET是本领域公知的。
图1是FinFET100的起始结构掺杂时的剖面图。FinFET100可包括绝缘体上硅(Silicon On Insulator；简称SOI)结构，该SOI结构包含在硅和/或锗衬底110上形成的埋入氧化物(BOX)层120、以及在BOX层120上的硅层130。或者，层130可包含锗、或硅-锗。在一实施例中，BOX层120的厚度范围可从大约200纳米至大约400纳米，且硅层130的厚度范围可从大约30纳米至大约100纳米。然后可沉积诸如氧化物层(例如，二氧化硅)和/或氮化物层(例如，氮化硅)等的保护层，以便用来作为后续蚀刻期间的保护盖。
然后可蚀刻硅层130及各保护层，以便形成硅鳍片140、以及在鳍片140上的保护层150及160(请参阅图2)。保护层150可以是氧化物层，且保护层160可以是氮化物层。层150的厚度可例如为大约15纳米，且层160的厚度范围可以是大约50至75纳米间。
然后可在邻近鳍片140末端处形成源极/漏极区。在一个实施例中，可在硅层130上产生图形并蚀刻硅层130，以便在形成鳍片140的同时也形成源极及漏极区。在其它的实施例中，可以传统的方式沉积并蚀刻另一硅层，以便形成源极及漏极区。图3是FinFET100的透视图，该FinFET100具有在邻近鳍片140末端处形成的源极及漏极区310及320。
图4是具有源极区310、漏极区320、及鳍片140的FinFET100的俯视图。图1和图2是的沿着图4中的A-A’线的剖面图。
然后可在FinFET100上形成硅酸四乙酯(TEOS)层501。图5是沿着图4中的A-A’线的FinFET100的剖面图，用以显示TEOS层501。可对TEOS层501进行退火及平坦化，以便在FinFET100的顶部产生较平坦的表面。
可在TEOS层501中界定镶嵌(damascene)栅极掩膜，并在该掩膜中产生图形。尤其可在TEOS层501中形成沟槽。然后可经由蚀刻而在TEOS层501中打开栅极区。图6是FinFET100的俯视图，其中TEOS层501中的区域602表示该被打开的部分。更具体而言，可利用该掩膜来蚀刻区域602中的TEOS层，并保持其余的TEOS层501。在一个实施例中，可通过在区域602中的TEOS层上沉积深度大约为50至70纳米的多晶硅层，来图形化该栅极区，以得到较小的栅极长度。可图形化该多晶硅层，而留下极薄的多晶硅线。然后可沉积厚度大约为120至150纳米的氧化物层，然后将该氧化物层剖光到该多晶硅层的顶部。接着将该多晶硅蚀刻掉。然后蚀刻区域602中的TEOS，且利用剩余的氧化物层作为该TEOS蚀刻的掩膜。
然后可削薄鳍片140。在一个实施例中，可使FinFET100接触氨水(NH4OH)，直到鳍片140的宽度从10纳米至15纳米减少到大约3纳米至6纳米为止，而将鳍片140削薄。可在较慢的速率且受控制的进度下，执行该削薄工艺，使该鳍片以大约2埃/分钟的速率下被削减。被以此种方式削薄的鳍片显示在图7中，而图7是沿着图4的A-A’线的剖面图。图8是对应图7的俯视图。如图7及图8所示，在削薄鳍片140之后的FinFET100包含形成在氧化物层150及保护层160下的凹处。
如图9所示，可在鳍片140的侧表面上生长栅极介电层901。栅极介电层901的厚度可薄至0.6至1.2纳米。在替代实施例中，可在鳍片140的侧表面上形成具有0.6至1.2纳米的等效氧化物厚度(EquivalentOxide Thickness；简称EOT)的高介电常数(k)值层。
请参阅图10，然后可以一种传统的方式在FinFET100上沉积多晶硅层。可利用栅极掺杂掩膜来掺杂该多晶硅层。可利用磷来掺杂NMOS器件，且可利用硼来掺杂PMOS器件。可将该多晶硅层平坦化至氮化物层160的高度，而形成两个独立的多晶硅区1001A及1001B。可图形化多晶硅区1001A及1001B，并蚀刻多晶硅区1001A及1001B，以便形成FinFET100的栅极。多晶硅区1001A及1001B可因而形成两个在电性独立的栅极。在其它的实施例中，可不将多晶硅区1001A及1001B剖光到氮化硅层160的高度。替代性地，单一的多晶硅层可覆盖氮化硅层160。在此种情形中，该多晶硅层形成FinFET100的单一可寻址的栅极。
之后可将掩膜施加至栅极区602。使用该掩膜保护区域602，该TEOS层501以及保护二氧化硅与氮化硅层150与160沉积在该源极/漏极区域310与320上，接着可使用各向同性湿法蚀刻方式予以蚀刻以移除该TEOS层501。
在露出源极/漏极区310及320的表面之后，可对FinFET100执行离子注入，以便掺杂源极310及漏极320。更具体而言，在NMOS的FinFET中，可在1015原子/平方厘米的剂量以及5至10kev(千电子伏特)的能量下注入磷。在PMOS的FinFET中，可在1015原子/平方厘米的剂量以及2至5kev的能量下注入硼。
在离子注入之后，可对FinFET100执行自对准硅化(salicidation)工艺(即，自对准硅化物工艺)。在该步骤中，可在多晶硅(栅极)区1001A及1001B以及源极及漏极区310及320上沉积诸如钨、钴、钛、钽、钼、镍、铒、或铂等金属。然后可执行热退火，以便产生金属硅化物化合物。图11示出了在退火之后的FinFET100的俯视图。请参阅图11，该剖面阴影线代表在源极/漏极区310及320以及两个栅极区上的金属硅化物化合物。这些栅极区可包含在多晶硅区1001A及1001B的末端上形成的栅极垫1101及1102。所形成的FinFET100包含图11中以虚线示出的薄鳍片沟道区140。然而，如图10所示，保护层150及160的宽度大于鳍片140的宽度。有利之处在于：所形成的薄沟道MOSFET提供了较佳的短沟道控制。
请再参阅图5，在替代实施例中，并不是使鳍片140接触氨水将鳍片140削薄，而是可利用活性离子蚀刻(Reactive Ion Etching；简称RIE)工艺来削减鳍片140。一般而言，且如本领域所熟知的，RIE是离子蚀刻的一种变形，这是因为在RIE蚀刻期间，将半导体晶片放置在发出射频的电极上。在该实施例中，最初可利用RIE将鳍片140的宽度减少到大约3纳米至6纳米，而将鳍片140削薄。
然后可利用蚀刻工艺来去除保护层150及160，以便露出图12中被标示为鳍片1240的鳍片。
如图13所示，为了消除因蚀刻层150及160而引发的蚀刻损坏，然后可在鳍片1240的露出表面上形成牺牲氧化物层1301。可使牺牲氧化物层生长至或形成至大约0.6至1.2纳米的厚度，且也可将该牺牲氧化物层用来作为栅极介电层。在替代实施例中，可在鳍片140的侧表面上形成具有0.6至1.2纳米的等效氧化物厚度(EOT)的额外的氧化物层或高k值层，该额外的氧化物层或高k值层被标示为层1401。
请参阅图15，然后可以一种传统的方式在FinFET1200上沉积多晶硅层。可将该多晶硅层平坦化至氧化物层1301的高度，而形成两个独立的多晶硅区1201A及1201B。多晶硅区1201A及1201B可形成FinFET1200的栅极。多晶硅区1201A及1201B可因而形成两个电性独立的栅极。在其它的实施例中，可不将多晶硅区1201A及1201B剖光至氧化物层1301的高度。替代性地，单一的多晶硅层可覆盖氧化物层1301。在此种情形中，该多晶硅层形成FinFET1200的单一可寻址的栅极。
然后可将掩膜施加到FinFET1200的栅极区。使用该掩膜来保护该栅极区，然后可从其余的FinFET1200蚀刻掉TEOS层501以及在源极/漏极区310及320上沉积的额外保护层。
在露出源极/漏极区310及320的表面之后，可对FinFET1200执行离子注入。如此可有效地掺杂源极310及漏极320。更具体而言，在NMOS的FinFET中，可在1015原子/平方厘米的剂量以及5至10kev的能量下注入磷。在PMOS的FinFET中，可在1015原子/平方厘米的剂量以及2至5kev的能量下注入硼。
在离子注入之后，可对FinFET1200执行自对准硅化(salicidation)工艺(即，自对准硅化物工艺)。在该步骤中，可在多晶硅(栅极)区1201A及1201B以及源极及漏极区310及320上沉积诸如钨、钴、钛、钽、或钼等的金属。然后可执行热退火，以便产生金属硅化物化合物。此时，FinFET1200的俯视图类似于图11所示的FinFET200。
其它实施例
在某些情形中，可能需要形成应变硅(strained silicon)FinFET。图16至18是沿着图4中的A-A’线的FinFET1600的剖面图。
请参阅图16，可在埋入氧化物层1601上形成硅锗层1610。然后可在硅锗层1610上形成氮化物层1620。可以诸如一种形成类似于图7所示的薄鳍片的方式形成硅锗层1610及氮化物层1620的配置。因此，可初步将硅锗层1610及氮化物层1620蚀刻成具有相同的宽度，然后可横向蚀刻硅锗层1610，以便形成薄硅锗层1610。硅锗层1610的宽度可以是大约5纳米至15纳米。
请参阅图17，然后可在该硅锗层附近以外延生长方式生长出宽度大约为5纳米至10纳米的硅层1611。在生长出硅层1611之后，可接着形成栅极介电层1612。栅极介电层1612的厚度可薄至0.6至1.2纳米。
请参阅图18，然后可以一种传统的方式在FinFET1600上沉积一多晶硅层1801。然后图形化该多晶硅层，并蚀刻该多晶硅层，以便形成FinFET1600的栅极。也可将多晶硅层1801向下平坦化到氮化物层1620的高度。此时，可以前文所述的方式完成FinFET1600。
某些MOSFET具有被放置在单一埋入氧化物层上的PMOS及NMOS的FinFET。在该实施例中执行自对准硅化工艺(例如前文所述的自对准硅化工艺)时，可对适当的金属进行无电镀(electrolessplating)，而完成选择性的自对准硅化。此外，可使用两种或更多种不同的硅化物。可将一种硅化物(例如钴、镍、稀土金属的铒、铕、镓、钐硅化物)用于NMOS的FinFET，且可将另一种硅化物(例如铂硅化物)用于PMOS的FinFET。在此种情形中，可先以光刻胶层覆盖该PMOS的FinFET，接着可沉积NMOS金属。然后可去除该PMOS的FinFET上的光刻胶层，接着可在该NMOS的FinFET上施加另光刻胶层。此时，可施加PMOS金属。然后可执行热退火，以便产生金属硅化物化合物。
结论
本文已说明了具有窄鳍片的FinFET及制造该窄鳍片FinFET的方法。该窄鳍片将其中包括短沟道控制的多个优点提供给FinFET。
在前文的说明中，述及了诸如特定材料、结构、化学品、工艺等的许多特定细节，以便使本发明能够彻底被了解。然而，可在不依靠本文所述的这些特定细节的情形下实施本发明。在其它的情形中，并未详细说明一些传统的处理结构，以免非必要地模糊了本发明的重点。
可以传统的沉积技术来沉积用来制造根据本发明的半导体器件的介电层及导电层。例如，可采用诸如其中包括低压化学气相沉积(LowPressure Chemical Vapor Deposition；简称LPCVD)及增强型化学气相沉积(Enhanced Chemical Vapor Deposition；简称ECVD)的各种类型的化学气相沉积(Chemical Vapor Deposition；简称CVD)工艺等的金属化技术。
可将本发明应用于制造半导体器件，尤其是应用于制造设计的特征尺寸为100纳米或更小的半导体器件，而可得到提高的晶体管及电路速度、以及较佳的可靠性。可将本发明应用于各种类型的半导体器件的形成，因而并未述及细节，以免模糊了本发明的要点。在实施本发明时，采用了传统的光刻及蚀刻技术，因而本文并未详细述及此类技术的细节。
本发明的揭示事项中只示出及说明了本发明的较佳实施例及其多用途。所当应了解，本发明可用于各种其它的组合及环境，且可在本文所陈述的本发明的观念的范围内对本发明加以修改。

Claims (8)

1.一种金属氧化物半导体场效晶体管器件，该金属氧化物半导体场效晶体管器件包含在绝缘层(120)上形成的源极(310)及漏极(320)，并包含在该绝缘层上且在该源极(310)与漏极(320)之间形成的鳍片结构(140)，该金属氧化物半导体场效晶体管器件的特征在于：
在该鳍片结构的沟道区中形成的削薄区；
至少在该鳍片结构的削薄区上形成的保护层(150，160)，该保护层的宽度大于该削薄区的宽度；
在该鳍片结构的至少一个沟道部分周围形成的介电层(901)；以及
在该介电层及该鳍片结构周围的绝缘层上由两个分开的多晶硅区(1001A，1001B)形成的电性独立的栅极(1101，1102)，其中该削薄区的宽度大约为3至6纳米间。
2.如权利要求1所述的器件，其中该保护层包含：
氧化物层(150)；以及
在该氧化物层上形成的氮化物层(160)。
3.如权利要求2所述的器件，其中该氧化物层(150)被沉积至大约15纳米的深度，且该氮化物层(160)被沉积至大约50纳米至75纳米间的深度。
4.如权利要求1所述的器件，其中该介电层(901)的厚度约为0.6纳米至1.2纳米间。
5.如权利要求1所述的器件，其中该栅极包含多晶硅。
6.如权利要求1所述的器件，其中该金属氧化物半导体场效晶体管器件是鳍片场效晶体管。
7.一种形成金属氧化物半导体场效晶体管器件的方法，包含下列步骤：
在绝缘层(120)上形成源极(310)、漏极(320)、及鳍片结构(140)，该鳍片结构的部分用来作为该金属氧化物半导体场效晶体管的沟道；
在该鳍片结构上形成保护层(150，160)；
在不显着地削减该保护层的情况下将该鳍片结构削减到大约3纳米至6纳米间的宽度；
在该鳍片结构周围生长介电层；
在该介电层周围沉积两个分开的多晶硅层(1001A，1001B)；以及蚀刻该两个分开的多晶硅层以形成用于该金属氧化物半导体场效晶体管的电性独立的栅极(1101，1102)。
8.如权利要求7所述的方法，其中形成该保护层的该步骤包含下列步骤：
将氧化物层沉积至大约15纳米的深度；以及将氮化物层沉积至大约50纳米至75纳米间的深度。
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US6921963B2 (en) 2005-07-26
KR101035421B1 (ko) 2011-05-20
US6762483B1 (en) 2004-07-13
JP2006516820A (ja) 2006-07-06
EP1588422A1 (en) 2005-10-26
CN1759488A (zh) 2006-04-12
US20040197975A1 (en) 2004-10-07
KR20050096156A (ko) 2005-10-05
TW200418180A (en) 2004-09-16

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