CN1753151A - 制造薄膜晶体管的方法 - Google Patents
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Abstract
本发明公开了一种制造薄膜晶体管的方法，该方法可以包括在形成非晶硅层和帽盖层的衬底上形成金属催化剂层。使用溅射靶材可以形成金属催化剂，其中可以在形成溅射靶材的工艺中控制金属催化剂的成分比。靶材可以由金属催化剂和具有大于金属催化剂的原子量的金属组成。该合金可以用预定的成分比形成。可以退火衬底以结晶非晶硅层成为多晶硅层。
Description
技术领域
本发明涉及，例如制造薄膜晶体管的方法。本发明更具体地涉及，例如包括在衬底上形成预定组成的金属催化剂层的制造薄膜晶体管的方法。
背景技术
一般地，如下制造用于平板显示装置的薄膜晶体管(TFT)。在如玻璃或石英的透明衬底上沉积非晶硅。然后脱水该非晶硅且注入用于形成沟道的杂质离子。随后，结晶非晶硅以形成半导体层。形成栅极绝缘层和栅电极。之后，进行离子注入工艺以形成源极和漏极区域。然后形成层间绝缘层以及源电极和漏电极。
将非晶硅结晶为多晶硅的方法可以包括固相结晶、准分子激光结晶、金属诱发结晶和金属诱发横向结晶。固相结晶法是将非晶硅层在约700℃或更低的温度(极限温度通常是衬底材料的变形温度)下退火几个至几十个小时。准分子激光结晶法是在硅层上照射准分子激光以高温和极短的时间局部地加热被结晶的硅层。
金属诱发结晶法是其中将如镍、钯、金或铝的金属注入非晶硅层或与非晶硅层接触以诱发非晶硅经过相变成为多晶硅的一种方法。金属诱发横向结晶法是通过使金属和硅之间的反应获得的硅化物横向延伸以诱发随后的硅的结晶来结晶硅层。
但是，固相结晶法具有的缺点是当在高温下长时间退火衬底时可能产生严重的衬底变形，而准分子激光结晶法具有的缺点是不仅需要高的设备成本和高的维护成本，而且多晶硅层的表面粗糙度差。在金属诱发结晶和金属诱发横向结晶中，诱发结晶的金属材料留在多晶硅层中且可以增加在半导体层中的漏电流。
为了解决上述的缺点，公开了一种依靠溅射在非晶硅层上形成帽盖层和形成做为薄金属催化剂层的金属催化剂且退火来结晶的方法(Korean PatentPublication No.2003-0060403)，但是，存在的缺点是金属催化剂层应当形成得极薄，即，它应当以极低的密度形成。
发明内容
因此，本发明可以通过提供制造TFT的方法帮助解决与传统的器件相关的问题。例如，可以使用包括金属催化剂和原子量大于金属催化剂的金属的合金的溅射靶材形成金属催化剂层。金属催化剂和其它金属可以以预定的组成比存在。然后，可以退火TFT的衬底。可以以均匀和稳定的方式保持在多晶硅层的界面处诱发结晶的金属催化剂的低密度。该控制可以不仅提高尺寸均匀度和多晶硅层的晶粒尺寸而且可以最小化金属催化剂的残留量。
本发明提供例如制造TFT的方法。该方法可以包括：在衬底上形成非晶硅层和帽盖层；使用由第一金属和原子量大于第一金属的第二金属的合金组成的溅射靶材在帽盖层上形成金属催化剂层；退火衬底以结晶非晶硅层成为多晶硅层；和构图多晶硅层以形成半导体层。
附图说明
图1是在衬底上形成缓冲层、非晶硅层和帽盖层的工艺的剖面图；
图2是通过溅射法使用由包含金属催化剂和异质金属的合金形成的靶材的在帽盖层上形成金属催化剂层的工艺的剖面图；
图3是退火衬底以结晶非晶硅层成为多晶硅层的工艺的剖面图；
图4是使用通过本发明形成的多晶硅层制造薄膜晶体管的工艺的剖面图；
图5A、5B、5C和5D是显示基于由只有一种金属催化剂组成的金属催化剂层的厚度的非晶硅层的结晶度的照片。
具体实施方式
将参考其中显示本发明的示范实施例的附图更详细地说明本发明。但是本发明可以以不同的形成实现且不应解释为限于所显示和描述的实施例。在附图中，为了清晰夸大了尺寸。使用同样的附图标记在说明书中指示同样的元件。
图1是在衬底上形成缓冲层、非晶硅层和帽盖层的工艺的剖面图。如图1所示，利用化学气相沉积(CVD)或物理气相沉积(PVD)在如玻璃或塑料的透明衬底101上可以形成单一或多层的氧化硅或氮化硅。缓冲层102可以防止湿气或下方衬底产生的杂质扩散。它还可以(或可选地)通过调整在结晶时的热传导速率促进半导体层的结晶。
随后，利用例如CVD或PVD可以在缓冲层102上形成非晶硅层103。非晶硅层103可能包含如氢气的气体，其可以在结晶工艺期间导致硅层的爆裂故障。因此，它们可以产生可以减小结晶后多晶硅层的电子迁移率的缺陷。因此，一般地应进行脱水工艺。用于脱水的退火可以在炉子中在约400℃或更高的温度进行从几十分钟至几小时。
随后，在非晶硅层103上可以形成如氮化硅层或氧化硅层的绝缘层的单一或多层，由此形成帽盖层104。帽盖层104可以导致随后形成的金属催化剂层的金属催化剂的选择性的扩散(或渗透)。例如，具有小原子量的金属催化剂在帽盖层104内具有较快的扩散速度，而具有较大原子量的异质金属在帽盖层104内具有较低的扩散速度。因此，它可以不允许非晶硅层103到达界面。
图2是通过溅射法使用由作为金属催化剂的第一金属和具有大于金属催化剂的原子量的第二金属的合金形成的靶材在帽盖层上形成金属催化剂层的工艺的剖面图。如图2所示，可以在靶材105上进行溅射106。靶材105可以是具有一种成分的合金以使第一金属(如金属催化剂)具有约109至约1015原子/cm2的表面密度。优选地，第一金属具有1013至1015原子/cm2的表面密度。通过调整靶材的第一金属的成分比或调整金属催化剂层的厚度可以控制第一金属的表面密度。例如，通过减小靶材的第一金属的成分比或减小金属催化剂层的厚度可以减小表面密度。
第一金属可以是例如Ni(镍)、Pd(钯)、Ti(钛)、Ag(银)、Au(金)、Al(铝)、Sn(锡)、Sb(锑)、Cu(铜)、Co(钴)、Mo(钼)、Tr(铽)、Ru(钌)、Rh(铑)、Cd(镉)或Pt(铂)。可以形成靶材以使第一金属具有约0.1至约50at％的成分比且其余部分由第二金属形成。优选地，第一金属具有约1至约2at％的成分比。这是因为这样的比例可以是当通过现有技术制造合金靶材时，允许第一金属在合金靶材内被均匀地分布的最小成分比。如果用更低的比例可以获得这样的结果，则可以使用更低的比例。
第二金属可以具有大于第一金属的原子量。例如，当第一金属是镍(Ni；元素No.28、原子量53.70)时，可以使用具有大于镍的原子量的原子量的金属(例如，在元素周期表时铜之后的所有金属)作为第二金属。当第一金属是镍时，合金可以例如使用钼(Mo；元素No.42、原子量95.94)或钨(W；元素No.74、原子量183.84)作为第二金属制造。这是因为Mo和W每个具有的原子量大约是Ni的两或三倍大。因此，它们在帽盖层内的扩散速率大约是Ni的两或三倍小。一般地，在帽盖层内的扩散速率可以与原子量成反比。
当利用第一金属靶材(在传统的方法中)形成具有1013至1015原子/cm2的表面密度的金属催化剂层为1厚时，非常难于控制形成金属催化剂层的溅射方法。但是当依据本发明形成包含具有约为0.1至50at％的成分比的第一金属的合金靶材时，可以形成具有约1013至约1015原子/cm2的表面密度的金属催化剂层为约2至约1000厚。因此，可以形成包含具有低密度的第一金属的金属催化剂层且可以形成较厚的金属催化剂层。
可以控制第一金属催化剂层的第一金属以具有约1013至约1015原子/cm2的表面密度是为了以下原因。如图5A、图5B、图5C和图5D所示，通过表面密度或金属催化剂层的量可以显著地影响非晶硅层的结晶。即，当形成只有第一金属组成的金属催化剂层为约0.5厚或更薄时，大多数非晶硅层150a可以保持非结晶，且结晶的部分可以或者不出现或者不均匀，如图5A所示。相反，如果控制金属催化剂层为约1厚，则可以均匀地结晶大多数区域成为多晶硅层151b，如图5B所示。当厚度约1.5(图5C)或约为2.0(图5D)，结晶可能不容易发生(152a和153a)且即使当结晶发生时(152b、153b)，结晶可能不均匀。
因此，当使用其中第一金属具有依据本发明的预定成分比的靶材形成金属催化剂层时，在金属催化剂层中出现具有约1013至约1015原子/cm2的表面密度的第一金属，这与1厚的传统的金属催化剂层相同，尽管本发明的金属催化剂层可以为约100厚。
因此，当使用本发明的靶材取代传统靶材时，(通过调节在靶材中所含的第一金属的成分比在约0.1at％至约50at％的范围)可以容易地控制约2至约1000倍的第一金属的浓度。
图3是退火衬底以结晶非晶硅层成为多晶硅层的工艺的剖面图。如图3所示，可以退火(108)在其上已经形成缓冲层、非晶硅层、帽盖层和金属催化剂层的衬底以便能将非晶硅层结晶为多晶硅层。在该情况中，可以分两步进行退火。第一退火工艺可以在约200℃至约800℃的温度下进行而第二退火工艺可以在约400℃至约1300℃的温度下进行。
在第一退火工艺中，金属催化剂层内的第一金属110a被移动至非晶硅层的界面(111a)以形成诱发非晶硅层的结晶的籽晶110b。通过第一退火工艺在金属催化剂层内的第二金属112a也可以在帽盖层内被扩散(111b)。但是，第二金属具有低于第一金属的扩散速率的扩散速率，从而无法移动至非晶硅层的界面而可以保留在帽盖层内(112b)。
第二退火工艺可以是依靠通过第一退火工艺形成的籽晶将非晶硅层结晶为多晶硅层的工艺。
图4是使用通过本发明形成的多晶硅层制造薄膜晶体管的工艺的剖面图。如图4所示，非晶硅层可以依靠退火工艺被结晶为多晶硅层，可以去除金属催化剂层和帽盖层，以及可以构图多晶硅层以形成半导体层131。
随后，栅极绝缘层可以使用CVD或PVD在衬底上由氧化硅层或氮化硅层的单层或多层132形成。
然后可以在衬底上沉积栅电极形成材料且可以构图栅电极形成材料以形成栅电极133。然后可以使用氧化硅或硅的单层或多层以形成层间绝缘层134。
然后可以蚀刻栅极绝缘层和层间绝缘层的预定区域以形成暴露半导体层的预定区域的接触孔。然后可以形成源和漏电极形成材料以填充接触孔且接触所暴露的半导体层的预定区域。
可以构图源和漏电极形成材料以形成源电极和漏电极135。由此，完成TFT。
本发明提供了例如使用金属催化剂层制造TFT的方法。使用具有第一金属和具有大于第一金属的原子量的第二金属的合金的溅射靶材可以获得金属催化剂层。由此，浓度可以以过去可以调整的量的约2至约1000倍被容易地调整。这不仅允许金属催化剂层形成得较厚，而且促进均匀和稳定的控制以及显著地提高了多晶硅层的均匀度和晶粒尺寸。
尽管参考本发明某些实施例具体地描述了本发明，但是在不背离本发明的范围的情况下，可以对这些实施例作出改变。
本申请要求于2004年9月22日提交的Korean Patent ApplicationNo.2004-76109的优先权和权益，其全部内容引入作为参考。
Claims (12)
1.一种制造薄膜晶体管的方法，包括：
在衬底上形成非晶硅层和帽盖层；
使用包括含有第一金属和具有大于所述第一金属的原子量第二金属的合金的溅射靶材在所述帽盖层上形成金属催化剂层；
退火所述衬底以结晶所述非晶硅层成为多晶硅层；和
构图所述多晶硅层以形成半导体层。
2.如权利要求1的方法，其中所述金属催化剂层包括表面密度为约109至约1015原子/cm2的第一金属。
3.如权利要求1的方法，其中所述金属催化剂层包括表面密度为约1013至约1015原子/cm2的第一金属。
4.如权利要求1的方法，其中所述金属催化剂层为约2至约1000厚。
5.如权利要求1的方法，其中所述退火工艺包括第一退火阶段和第二退火阶段。
6.如权利要求5的方法，其中所述第一退火阶段在约200℃至约800℃的温度进行，且所述第二退火阶段在约400℃至约1300℃的温度进行。
7.如权利要求5的方法，其中所述第一退火阶段扩散所述第一金属至所述非晶硅层的表面，且所述第二退火阶段将所述非晶硅层结晶为多晶硅。
8.如权利要求1的方法，其中在所述退火期间，所述第一金属的扩散速率大于所述第二金属的扩散速率。
9.如权利要求1的方法，其中所述第一金属从包括Ni、Pd、Ti、Ag、Au、Al、Sn、Sb、Cu、Co、Mo、Tr、Ru、Rh、Cd和Pt的组中选择。
10.如权利要求1的方法，其中所述第一金属是镍，且所述第二金属是钼或钨。
11.如权利要求1的方法，其中所述第一金属以约0.1至50at％的成分比存在，且其余是所述第二金属。
12.如权利要求1的方法，其中所述第一金属以约1至2at％的成分比存在，且其余是所述第二金属。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR76109/04 | 2004-09-22 | ||
| KR1020040076109A KR100659758B1 (ko) | 2004-09-22 | 2004-09-22 | 박막트랜지스터 제조 방법 |
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| CN1753151A true CN1753151A (zh) | 2006-03-29 |
| CN100536075C CN100536075C (zh) | 2009-09-02 |
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| US (1) | US7557020B2 (zh) |
| JP (1) | JP4369391B2 (zh) |
| KR (1) | KR100659758B1 (zh) |
| CN (1) | CN100536075C (zh) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8044401B2 (en) | 2007-06-27 | 2011-10-25 | Samsung Mobile Display Co., Ltd. | Thin film transistor, method of fabricating the same, organic light emitting diode display device including the same and method of fabricating the same |
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| TW200701336A (en) * | 2005-06-28 | 2007-01-01 | Chunghwa Picture Tubes Ltd | Manufacturing method of polysilicon |
| KR100731752B1 (ko) * | 2005-09-07 | 2007-06-22 | 삼성에스디아이 주식회사 | 박막트랜지스터 |
| KR20080015666A (ko) | 2006-08-16 | 2008-02-20 | 삼성전자주식회사 | 박막 트랜지스터 표시판의 제조 방법 |
| KR100878284B1 (ko) * | 2007-03-09 | 2009-01-12 | 삼성모바일디스플레이주식회사 | 박막트랜지스터와 그 제조 방법 및 이를 구비한유기전계발광표시장치 |
| KR101146995B1 (ko) * | 2010-06-16 | 2012-05-22 | 삼성모바일디스플레이주식회사 | 다결정 실리콘층의 형성 방법 및 이를 이용한 박막 트랜지스터의 형성방법 |
| US9818607B2 (en) * | 2014-07-18 | 2017-11-14 | The Hong Kong University Of Science And Technology | Metal-induced crystallization of amorphous silicon in an oxidizing atmosphere |
| KR20230127703A (ko) | 2022-02-25 | 2023-09-01 | 주식회사 블레스드프로젝트 | 아몬드 부산물을 이용한 합판 및 이의 제조 방법 |
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| JP3107941B2 (ja) | 1993-03-05 | 2000-11-13 | 株式会社半導体エネルギー研究所 | 薄膜トランジスタおよびその作製方法 |
| JP3269738B2 (ja) * | 1994-09-21 | 2002-04-02 | シャープ株式会社 | 半導体装置およびその製造方法 |
| JP3540251B2 (ja) | 1994-06-07 | 2004-07-07 | 株式会社半導体エネルギー研究所 | 薄膜トランジスタ |
| JPH0869967A (ja) * | 1994-08-26 | 1996-03-12 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
| US5851920A (en) * | 1996-01-22 | 1998-12-22 | Motorola, Inc. | Method of fabrication of metallization system |
| KR980012639A (ko) * | 1996-07-29 | 1998-04-30 | 윌리엄 비. 켐플러 | 초박 적층형 게이트 유전체 구조물 |
| KR19980021639A (ko) * | 1996-09-18 | 1998-06-25 | 구자홍 | 비정질 실리콘 박막의 결정화 방법 |
| US6558986B1 (en) * | 1998-09-03 | 2003-05-06 | Lg.Philips Lcd Co., Ltd | Method of crystallizing amorphous silicon thin film and method of fabricating polysilicon thin film transistor using the crystallization method |
| JP4801249B2 (ja) | 1999-11-19 | 2011-10-26 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
| US20030003694A1 (en) | 2001-06-28 | 2003-01-02 | Apostolos Voutsas | Method for forming silicon films with trace impurities |
| KR100662493B1 (ko) * | 2001-07-10 | 2007-01-02 | 엘지.필립스 엘시디 주식회사 | 비정질막의 결정화방법 및 이를 이용한 액정표시소자의제조방법 |
| JP3942878B2 (ja) | 2001-11-28 | 2007-07-11 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
| KR100473996B1 (ko) | 2002-01-09 | 2005-03-08 | 장 진 | 비정질 실리콘의 결정화 방법 |
| KR100504538B1 (ko) * | 2002-08-28 | 2005-08-04 | 엘지.필립스 엘시디 주식회사 | 비정질 실리콘의 결정화 방법 및 이를 이용한액정표시장치의제조방법 |
| GB0224871D0 (en) * | 2002-10-25 | 2002-12-04 | Plastic Logic Ltd | Self-aligned doping of source-drain contacts |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8044401B2 (en) | 2007-06-27 | 2011-10-25 | Samsung Mobile Display Co., Ltd. | Thin film transistor, method of fabricating the same, organic light emitting diode display device including the same and method of fabricating the same |
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| US7557020B2 (en) | 2009-07-07 |
| JP2006093648A (ja) | 2006-04-06 |
| CN100536075C (zh) | 2009-09-02 |
| US20060063315A1 (en) | 2006-03-23 |
| KR20060027243A (ko) | 2006-03-27 |
| JP4369391B2 (ja) | 2009-11-18 |
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| CF01 | Termination of patent right due to non-payment of annual fee |