CN1713368A - 用于制造半导体器件的方法 - Google Patents
用于制造半导体器件的方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 71
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 230000004888 barrier function Effects 0.000 claims abstract description 49
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 24
- 239000010703 silicon Substances 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims description 75
- 239000002184 metal Substances 0.000 claims description 75
- 238000005530 etching Methods 0.000 claims description 31
- 238000009792 diffusion process Methods 0.000 claims description 29
- 239000012535 impurity Substances 0.000 claims description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 24
- 239000010936 titanium Substances 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 16
- 229910052721 tungsten Inorganic materials 0.000 claims description 16
- 239000010937 tungsten Substances 0.000 claims description 16
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 15
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 14
- 229910021332 silicide Inorganic materials 0.000 claims description 14
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 13
- 229910008484 TiSi Inorganic materials 0.000 claims description 11
- 239000007792 gaseous phase Substances 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 8
- 229910052785 arsenic Inorganic materials 0.000 claims description 7
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 4
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 1
- 229910052786 argon Inorganic materials 0.000 claims 1
- 238000001465 metallisation Methods 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 16
- 238000005229 chemical vapour deposition Methods 0.000 description 12
- 238000009413 insulation Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 239000005388 borosilicate glass Substances 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
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- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- -1 tungsten nitride Chemical class 0.000 description 1
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Abstract
本发明提供了一种用于制造半导体器件的方法,该半导体器件能防止在形成被直接接触于包括导电图形和硅的N型导电区的导电图形的过程中接触电阻在被接触于N型导电区的区中增加,并且防止依照阻挡层的厚度的增加而造成的导电图形的寄生电容的增加。
Description
技术领域
本发明涉及一种用于制造半导体器件的方法;并且更具体而言,涉及一种制造能降低包括硅的导电区和导电图形之间的接触电阻的半导体器件的方法。
背景技术
半导体存储器件的动态随机存取存储器(DRAM)被分成两个区。一个是单元区(cell region),其包括由晶体管和电容器(1T1C)组成的多个单位单元,另一个是外围区。
例如,位线是实际发送数据的线并且被连接于单元晶体管的源。对于单元区,位线被电互连于单元接触插头,其通过位线接触插头而接触于栅电极的源/漏结区。对于包括用于感测并放大通过位线发送的单元数据的位线感测放大器的外围区,位线感测放大器,更具体而言是形成位线感测放大器和源/漏结的晶体管的栅,与位线之间的电互连是必要的。
图1是说明一个半导体器件的图,该半导体器件包括被直接接触于基片的掺杂扩散区的位线。
参考图1,栅绝缘层101、栅导电层102和绝缘硬掩模103被堆叠在基片100上并且在侧面被提供有间隔物104和刻蚀停止层105的栅电极G被形成。在此,存在表示数字104和105两者均指示间隔物的可能性。继续地说,诸如从基片表面扩大的源/漏的杂质扩散区106通过将其与栅电极的侧面自对准而形成。绝缘层107被形成于栅电极G上,并且绝缘层被刻蚀以形成开口,即接触孔108,从而暴露杂质扩散区106。沿被形成有开口108的轮廓,形成具有通过堆叠钛(Ti)层109和氮化钛(TiN)层110和111而形成的结构的阻挡层,并且钨层112被形成于阻挡层上。因此,钨层112形成通过阻挡层而电接触于基片100的杂质扩散区112的位线(B/L)。
形成图1的组成的过程被简要说明。
绝缘层107被沉积于所提供的栅电极G上并且通过化学机械抛光(CMP)方法或回刻蚀(etch back)过程而平面化绝缘层107。之后,光致抗蚀剂图形(未示出)被形成于经平面化的绝缘层107上,然后暴露杂质扩散区106的开口108通过借助使用光致抗蚀剂图形作为刻蚀掩模来刻蚀绝缘层107而形成。
随后,沿被形成有开口108的轮廓,Ti层109和TiN层110被依次沉积。然后,通过实施热工艺而诱发杂质扩散区106和Ti层109之间的反应,并由此形成以上两层的界面处的硅化钛(TiSi2)层。
在形成TiSi2层之后形成随后的钨层112的过程中,作为附加阻挡层的TiN层111被形成以防止钨的扩散。此时,TiN层111是通过采用化学气相沉积(CVD)方法而形成的,并且钨层112亦通过使用CVD方法而形成。
随后,通过堆叠光致抗蚀剂图形或多晶硅硬掩模和光致抗蚀剂图形而形成的掩模图形被形成于钨层112上。之后,通过使用掩模图形来选择性地刻蚀钨层112和阻挡层,由此形成位线。
对于形成半导体器件的位线接触,在被接触于P型杂质扩散区的位线接触区中进行附加离子注入以提高接触周围的硼(B)的掺杂浓度。然而,砷(As)或磷(Ph)离子注入在被接触于N型杂质扩散区的位线接触区中是不必要的。
因此,对于具有小于近似800的尺寸的高集成器件,电流容量由于N沟道金属氧化物半导体(NMOS)晶体管的电阻的增加而减小,因此器件的操作速度变慢。同时,对于接触区中阻挡层,即扩散阻挡层的形成,依照现有技术,Ti层和TiN层是通过物理气相沉积(PVD)方法而形成的,由此形成TiSi2。此时,由于PVD方法,阻挡层很难被形成于接触的侧壁上,因此通过CVD方法来另外沉积TiN层以覆盖接触的侧壁。因此,具有范围从近似500到近似600的厚度的厚阻挡层被形成于形成位线的钨层之下,由此提高整个位线的高度。因此,位线的寄生电容增加,由此降级了器件的操作特性。
发明内容
因此,本发明的目的是提供一种用于制造半导体器件的方法,该半导体器件能防止在形成被直接接触于包括导电图形和硅的N型导电区的导电图形的过程中接触电阻在被接触于N型导电区的区中增加,并且防止依照阻挡层的厚度的增加而造成的导电图形的寄生电容的增加。
依照本发明的一个方面,提供了这样一种用于制造半导体器件的方法,包括以下步骤:通过在包括硅的N型导电区上掺杂N型杂质而形成N型高掺杂区;通过使用化学气相沉积方法将第一金属层沉积于N型掺杂区上,其中通过使第一金属层的金属与N型掺杂区的硅进行反应,金属硅化物被形成于N型掺杂区和第一金属层之间的界面处;在第一金属层上形成导电层;以及通过选择性地刻蚀导电层和第一金属层来形成导电图形。
依照本发明的另一个方面,提供了这样一种用于制造半导体器件的方法,包括以下步骤:在基片上形成N型高度掺杂扩散区;通过将N型杂质另外掺杂到N型掺杂扩散区中来形成N型高掺杂区;通过使用化学气相沉积方法将第一金属层作为阻挡而沉积于N型掺杂区上,其中通过使第一金属层的金属与N型掺杂区的硅进行反应,金属硅化物被形成于N型掺杂区和第一金属层之间的界面处;在第一金属层上形成导电层;以及通过选择性地刻蚀导电层和第一金属层来形成导电图形。
依照本发明进一步的方面,提供了这样一种用于制造半导体器件的方法,包括以下步骤:在被提供有包括硅的N型导电区的下结构上形成绝缘层;通过选择性地刻蚀绝缘层来形成开口以暴露N型导电区;通过将N型杂质掺杂于通过开口而暴露的N型导电区上来形成N型高掺杂区;通过使用化学气相沉积方法将第一金属层作为阻挡而沉积于N型掺杂区上,其中通过使第一金属层的金属与N型掺杂区的硅进行反应,金属硅化物被形成于N型掺杂区和第一金属层之间的界面处;在第一金属层上形成导电层;以及通过选择性地刻蚀导电层和第一金属层来形成导电图形。
依照本发明仍进一步的方面,提供了这样一种用于制造半导体器件的方法,包括以下步骤:在基片上形成N型掺杂扩散区;在被提供有包括硅的N型导电区的下结构上形成绝缘层;选择性地刻蚀绝缘层,由此形成开口以暴露N型导电区;通过将N型杂质掺杂于通过开口而暴露的N型导电区上来形成N型高掺杂区;通过使用化学气相沉积方法将第一金属层作为阻挡而沉积于N型高掺杂区上,其中通过使第一金属层的金属与N型高掺杂区的硅进行反应,金属硅化物被形成于N型高掺杂区和第一金属层之间的界面处;在第一金属层上形成导电层;以及通过选择性地刻蚀第一金属层和导电层来形成导电图形。
附图说明
参照结合附图给出的对优选实施例的以下描述将较为清楚地理解本发明的以上和其它目的和特点,在附图中:
图1是说明一个半导体器件的横截面视图,该半导体器件包括被直接接触于基片的杂质扩散区的位线;并且
图2A到2E是说明依照本发明用于形成位线的过程的横截面视图。
具体实施方式
以下将参照附图来提供对本发明优选实施例的详述。
图2A到2E是说明依照本发明用于形成位线的过程的横截面视图。
以下参照图2A到2E,在举例说明用于形成位线的过程时来说明本发明。
参考图2A,栅绝缘层201被形成于基片200上,该基片被提供有用于形成半导体器件的各种元件。栅绝缘层201使用基于氧化物的绝缘层。在此,基片200是典型的硅基片。
导电层和绝缘层,其用于硬掩模,被依次沉积于栅绝缘层201上,然后用于栅电极图形形成的掩模图形通过照相制版而形成。之后,通过使用掩模图形作为刻蚀掩模来刻蚀用于硬掩模的导电层和绝缘层,由此形成具有通过堆叠栅导电层202和硬掩模203而形成的结构的栅电极。
栅导电层202由从多晶硅、钨、硅化钨、钛和氮化钛或者以上所列材料的组合的组中选择的材料制成。栅硬掩模203由基于氮化物层或基于氧化物的绝缘层制成。
随后,由氮化物层和氧化物层或者氮化物层和氧化物层的组合制成的绝缘层沿被形成有栅电极结构的轮廓被沉积。然后进行深刻蚀过程,由此形成间隔物204。间隔物204用来防止栅电极受到由随后刻蚀过程导致的冲击。接下来,刻蚀停止层205被形成于间隔物204上。
刻蚀停止层205起到在诸如自对准接触(SAC)过程的刻蚀过程中的刻蚀停止的作用,并且由基于氮化物的层制成。
在此,刻蚀停止层可被认为是间隔物的双结构。
随后,离子注入过程206被采用,然后N型杂质被掺杂在基片200上以将其本身与栅电极的侧面对准。之后,所掺杂的杂质通过热工艺而扩散,由此形成N型掺杂扩散区207,如源/漏结。
此时,砷(As)被用作N型杂质,并且As的浓度范围是从近似2×1015原子/cm2到近似5×1015原子/cm2。还有,离子注入需要范围从近似12KeV到近似18KeV的能量。
参考图2B,绝缘层208被形成于栅绝缘层201和刻蚀停止层205上。绝缘层208由基于氧化物的绝缘层或基于有机或无机的低介电常数层制成。
基于氧化物的绝缘层通过采用从一组中选择的材料而形成,该组由以下组成:硼硅酸盐玻璃(BSG)层、硼磷硅酸盐玻璃(BPSG)层、磷硅酸盐玻璃(PSG)层、原硅酸四乙酯(TEOS)层、高密度等离子体(HDP)氧化物层、旋涂玻璃(SOG)层和高级平面化层(APL)或其组合。
同时,依照本发明举例说明了低压原硅酸四乙酯(LP-TEOS)层,并且LP-TEOS的沉积厚度范围是从近似1,200到近似2,000。
随后,通过使用化学机械抛光(CMP)方法和深刻蚀过程来平面化绝缘层208的上部以在随后的光刻过程中保证余量。
接下来,光致抗蚀剂图形209被形成于经平面化的绝缘层208上。然后,使用光致抗蚀剂图形209作为刻蚀掩模来刻蚀绝缘层208,由此形成开口210,其暴露N型掺杂扩散区207,位线接触将在这里被形成。
接下来,通过光致抗蚀剂剥离过程来去除光致抗蚀剂图形209。此时,在仅使用光致抗蚀剂图形209作为掩模图形的情况下,光致抗蚀剂图形209应具有范围从近似2,500到近似3,500的足够厚度以在刻蚀时起到阻挡层的作用。
同时,尽管本发明的优选实施例举例说明了光致抗蚀剂图形209被专门用作掩模图形,牺牲硬掩模可被用在光致抗蚀剂209下以根据由光致抗蚀剂的厚度降级而导致的刻蚀阻挡层的特性和高分辨率来解决光致抗蚀剂图形209的厚度降级。可通过主要使用氮化物层、钨层和多晶硅层来形成牺牲硬掩模。
随后,参考图2C,通过对依照开口210的形成被暴露用于位线接触的N型掺杂扩散区207进行离子注入211来离子注入N型杂质。之后,N型高度掺杂扩散区212被形成于N型掺杂扩散区207中。因此,随后位线接触所形成的区中的过剩电子的浓度增加。
此时,As被用作N型杂质并且As的浓度范围是从近似2×1015原子/cm2到近似5×1015原子/cm2。此外,离子注入使用范围从近似7KeV到近似12KeV的能量。由于与在形成杂质扩散区使用的离子注入能量相比,该离子注入能量是低的,N型高度掺杂扩散区212被形成于N型掺杂扩散区207的内部。
在热工艺期间,在范围从近似20秒到近似40秒的时间段内在范围从近似750℃到近似850℃的温度处进行快速热工艺。还有,优选的是在N2或Ar的气氛中进行热工艺。
接下来,参考图2D,通过使用化学气相沉积(CVD)方法沿被形成有210的轮廓来沉积钛(Ti)层213。此时,由于CVD方法的特性,Ti层213的钛和N型高度掺杂扩散区212的硅起反应,由此形成硅化物TiSi2 215。在此,优选的是TiSi2的沉积温度应被维持在高于约690℃的温度以便于平稳地形成TiSi2 215。Ti层213的沉积厚度在绝缘层上的范围是从近似5到近似15,并且TiSi2的沉积厚度在硅基片上的范围是从近似40到近似100。当沉积Ti层213时,TiCl4和H2被用作源气。
随后,通过使用CVD方法沿被形成有Ti层213的轮廓来形成TiN层214。此时,TiN层214的沉积厚度很薄,具有范围从近似100到近似200的厚度。
由此完成了用于欧姆接触的具有阻挡层下的TiN层214和Ti层213和TiSi2 215的结构的阻挡层。之后,用于改进阻挡层特性的附加热工艺被实施。在该热工艺期间,在范围从近似20秒到近似40秒的时间段内在范围从近似750℃到近似850℃的温度处进行快速热处理。
同时,尽管本发明的优选实施例举例说明了通过堆叠TiN层和Ti层形成的阻挡层,可通过以下来形成阻挡层:使用具有极佳特性的各种类型的金属层,并且使其有可能通过与硅如Ta或TaN反应而形成硅化物,或者堆叠该金属层。
随后,参考图2E,作为用于位线的导电层的钨层216被形成于被形成有阻挡层的所有侧面上,然后掩模图形通过堆叠光致抗蚀剂图形或多晶硅硬掩模而形成,并且光致抗蚀剂图形被形成于其上。之后,通过使用掩模图形来选择性地刻蚀钨层216和阻挡层,由此形成位线。
同时,可通过使用从多晶硅层、硅化钨层、氮化钨层、TiN层、Ta层和TaN层或者以上所列材料的组合的组中选择的材料来形成位线导电层。
在通过CVD方法来沉积钨层216的情况下,WF6是通过借助使用H2和SiH4或Si2H6还原其本身来沉积的。钨层216的沉积厚度的范围是从近似500到近似800。
尽管本发明的优选实施例举例说明了用于形成位线的过程,用于形成被直接接触于包括硅的N型导电区的所有导电层,如单元接触、插头、金属接触和金属互连的过程可被应用于本发明。
如以上所说明的,依照本发明,N型杂质As被另外掺杂在被接触于导电图形的包括硅的N型导电区中,由此提高杂质的浓度并降低接触电阻。然后,通过CVD方法来薄沉积用于阻挡的第一金属层,如Ti层,同时,杂质扩散区的下部中的硅和第一金属层相互反应,由此形成金属硅化物,如TiSi2。同样,通过CVD方法来沉积用于阻挡的第二金属层,如TiN层,然后形成金属硅化物,如TiSi2。因此,有可能相对降低导电图形中阻挡层的高度并且当沉积用于阻挡的第一金属层时最优化温度和厚度,由此获得很低的接触电阻。
还有,本发明提供了增加操作速度和电流容量的效果,这是因为通过掺杂N型附加杂质,接触电阻可被降低近似25%。
此外,通过借助CVD方法来沉积阻挡层,有可能最明显地降低导电层的厚度,由此降低导电图形的寄生电容。因此,就是说,在器件的导电图形是位线的情况下,存在改进特性如半导体存储器件的刷新的效果。
本申请包含了涉及2004年6月25日提交于韩国专利局的韩国专利申请No.KR 2004-0048368的主题,其全部内容在此引入作为参考。
尽管已参照某些优选实施例描述了本发明,对本领域的技术人员来说将显而易见的是,可在不脱离被限定于以下权利要求中的本发明的精神和范围内做出各种改变和修改。
Claims (18)
1.一种用于制造半导体器件的方法,包括以下步骤:
通过在包括硅的N型导电区上掺杂N型杂质而形成N型高掺杂区;
通过使用化学气相沉积方法将第一金属层沉积于N型掺杂区上,其中通过使第一金属层的金属与N型掺杂区的硅进行反应,金属硅化物被形成于N型掺杂区和第一金属层之间的界面处;
在第一金属层上形成导电层;以及
通过选择性地刻蚀导电层和第一金属层来形成导电图形。
2.权利要求1的方法,其中对于形成N型高掺杂区的步骤,砷(As)被离子注入,然后通过使用热工艺来形成N型高掺杂区。
3.权利要求2的方法,其中对于形成N型高掺杂区的步骤,砷(As)的浓度范围是从近似2×1015原子/cm2到近似5×1015原子/cm2,并且离子注入能量需要范围从近似7KeV到近似12KeV的能量。
4.权利要求2的方法,其中对于形成N型高掺杂区的步骤,在热工艺期间,快速热工艺在范围从750℃到近似850℃的温度处被采用并且被采用近似20秒到近似40秒。
5.权利要求4的方法,其中热工艺在氮(N2)或氩(Ar)的气氛中进行。
6.权利要求1的方法,其中第一金属层在至少690℃的温度被沉积。
7.权利要求1的方法,其中第一金属层以范围从近似5到近似15的厚度被形成于绝缘层上,并且金属硅化物以范围从近似40到近似100的厚度被形成于在硅基片上。
8.权利要求1的方法,其中在沉积第一金属层的步骤之后,进一步包括以下步骤:
将用于阻挡的第二金属层沉积于第一金属层上;以及
实施热工艺。
9.权利要求8的方法,其中第二金属层是以范围从近似10到近似20的厚度被形成的。
10.权利要求8的方法,其中热工艺被采用在范围从750℃到近似850℃的温度处并且被采用近似20秒到近似40秒。
11.权利要求8的方法,其中第一金属层是钛(Ti)层;第二金属层是氮化钛(TiN)层;并且金属硅化物是硅化钛(TiSi2)。
12.权利要求2的方法,其中对于形成N型掺杂区的步骤,砷(As)被离子注入,然后通过进行热工艺在N型掺杂扩散区上形成砷(As)。
13.权利要求12的方法,其中对于形成N型掺杂扩散区的步骤,砷(As)的浓度范围是从近似2×1015原子/cm2到近似5×1015原子/cm2,并且离子注入能量需要范围从近似12KeV到近似18KeV的能量。
14.权利要求1的方法,其中导电层包括钨层。
15.权利要求14的方法,其中导电层是以范围从近似500到近似800的厚度被形成的。
16.一种用于制造半导体器件的方法,包括以下步骤:
在基片上形成N型高度掺杂扩散区;
通过将N型杂质另外掺杂到N型掺杂扩散区中来形成N型高掺杂区;
通过使用化学气相沉积方法将第一金属层作为阻挡而沉积于N型掺杂区上,其中通过使第一金属层的金属与N型掺杂区的硅进行反应,金属硅化物被形成于N型掺杂区和第一金属层之间的界面处;
在第一金属层上形成导电层;以及
通过选择性地刻蚀第一金属层和导电层来形成导电图形。
17.一种用于制造半导体器件的方法,包括以下步骤:
在被提供有包括硅的N型导电区的下结构上形成绝缘层;
通过选择性地刻蚀绝缘层来形成开口以暴露N型导电区;
通过将N型杂质掺杂于通过开口而暴露的N型导电区上来形成N型高掺杂区;
通过使用化学气相沉积方法将第一金属层作为阻挡而沉积于N型掺杂区上,其中通过使第一金属层的金属与N型掺杂区的硅进行反应,金属硅化物被形成于N型掺杂区和第一金属层之间的界面处;
在第一金属层上形成导电层;以及
通过选择性地刻蚀第一金属层和导电层来形成导电图形。
18.一种用于制造半导体器件的方法,包括以下步骤:
在基片上形成N型掺杂扩散区;
在被提供有包括硅的N型导电区的下结构上形成绝缘层;
选择性地刻蚀绝缘层,由此形成开口以暴露N型导电区;
通过将N型杂质掺杂于通过开口而暴露的N型导电区上来形成N型高掺杂区;
通过使用化学气相沉积方法将第一金属层作为阻挡而沉积于N型高掺杂区上,其中通过使第一金属层的金属与N型高掺杂区的硅进行反应,金属硅化物被形成于N型高掺杂区和第一金属层之间的界面处;
在第一金属层上形成导电层;以及
通过选择性地刻蚀第一金属层和导电层来形成导电图形。
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Also Published As
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CN100346465C (zh) | 2007-10-31 |
JP2006013424A (ja) | 2006-01-12 |
KR20050122740A (ko) | 2005-12-29 |
US7338871B2 (en) | 2008-03-04 |
KR100562650B1 (ko) | 2006-03-20 |
US20050287799A1 (en) | 2005-12-29 |
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