CN1707793A - 具有电感线圈的半导体器件 - Google Patents

具有电感线圈的半导体器件 Download PDF

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Publication number
CN1707793A
CN1707793A CNA2005100780216A CN200510078021A CN1707793A CN 1707793 A CN1707793 A CN 1707793A CN A2005100780216 A CNA2005100780216 A CN A2005100780216A CN 200510078021 A CN200510078021 A CN 200510078021A CN 1707793 A CN1707793 A CN 1707793A
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China
Prior art keywords
chip
semiconductor device
inductance coil
screen
masking layer
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CNA2005100780216A
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English (en)
Inventor
大黑达也
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Toshiba Corp
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Toshiba Corp
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Publication of CN1707793A publication Critical patent/CN1707793A/zh
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Abstract

一种半导体器件，包括：具有电感线圈的第1芯片，和所述第1芯片重叠、具有导电层的第2芯片，以及设置于所述第1及第2芯片之间的磁屏蔽层。

Description

具有电感线圈的半导体器件
相关申请书的互相参照
这个申请书是基于并要求利益优先权从归档于2004.06.11的优先权日本专利申请书No.2004-174390。全部内容如下所列作为参照。
技术领域
本发明涉及具有电感线圈的半导体器件。
背景技术
近年来，对使用于手机的芯片的面积缩小的要求日益提高。这是因为要不断谋求手机的小型化，要求性能的提高和功能的增加。在此，为了满足这样的要求，研究出了使芯片的膜厚变薄，芯片彼此重叠的SIP(封装内系统)技术。
但是，在SIP技术中，由于使芯片薄膜化而使得电路间的距离变近，故产生了干扰的问题。特别是，具有电感线圈的芯片和其它芯片层叠的情况下，若电感线圈的附近存在其它芯片的布线，则由于电感线圈产生的磁场的影响，所述布线中会流动感应电流。其结果是，产生了电感线圈的Q值劣化的问题。
另外，与本申请的发明有关联的现有技术信息，如下所示。
专利文献1  特开2002-16209号公报
发明内容
基于本发明的一个视点的半导体器件，装配有：具有电感线圈的第1芯片，和所述第1芯片重叠、具有导电层的第2芯片，设置于所述第1和第2芯片之间的第1磁屏蔽层。
附图说明
图1是与本发明的第1实施例有关的SIP构造的半导体器件的概略剖视图。
图2是与本发明的第1实施例有关的电感线圈的外径和屏蔽层的大小的关系的平面图。
图3至图8是与本发明的第1实施例有关的SIP构造的半导体器件的制造工序的剖视图。
图9(a)是在与本发明的第1实施例有关的在薄膜基板上淀积屏蔽层之后的TEM照片。
图9(b)是把图9(a)的框内区域扩大的TEM照片。
图10是用EPMA分析图9(a)，(b)的屏蔽层的分量比得到的结果的图。
图11是与本发明的第1实施例有关的屏蔽层由NiFe膜形成的情况下的Fe的含量与电阻率关系的图。
图12是与本发明的第1实施例有关的伴随屏蔽层的膜厚的变化的电感线圈的Q值的频率依存性的图。
图13(a)是没有屏蔽层的情况下，与本发明的第1实施例有关的SIP构造的半导体器件的概略剖视图。
图13(b)是有屏蔽层的情况下，与本发明的第1实施例有关的SIP构造的半导体器件的概略剖视图。
图14(a)是没有屏蔽层的情况下，与本发明的第1实施例有关的电感线圈的Q值的频率特性的图。
图14(b)是有屏蔽层的情况下，与本发明的第1实施例有关的电感线圈的Q值的频率特性的图。
图15是用于说明与本发明的第1实施例有关的半导体器件的效果的图，显示的是在没有设置屏蔽层的情况下电感线圈的Q值劣化的芯片的膜厚与电感线圈的外径关系的图。
图16是用于说明与本发明的第1实施例有关的半导体器件的效果的图，显示的是高度为500μm的空间里层叠的芯片的数量与硅基板的膜厚的关系的图。
图17是与本发明的第2实施例有关的SIP构造的半导体器件的概略剖视图
图18至图23是与本发明的第2实施例有关的SIP构造的半导体器件的制造工序的剖视图。
图24是与本发明的各实施例有关的封装后的半导体器件的剖视图。
图25是与本发明的各实施例有关的半导体器件，是第1及第2芯片被用含有磁性材料的粘合剂粘合的状态下的剖视图。
图26是与本发明的各实施例有关的半导体器件，是第2芯片也设置屏蔽层的情况下的剖视图。
图27是与本发明的各实施例有关的半导体器件，是第1芯片的背面部分性的形成屏蔽层的情况下的剖视图。
图28是与本发明的各实施例有关的半导体器件，是电感线圈的周围形成屏蔽层的情况下的剖视图。
图29，图30是与本发明的各实施例有关的半导体器件，是4个芯片层叠的情况下的剖视图。
具体实施方式
以下参照附图说明本发明的实施例。在说明之际，全图共同的部分付与共同的参照符号。另外，图中，为了便于说明，电感线圈、芯片等用模式图图示，形状、膜厚及大小与实际不同的情况也有。
第1实施例
第1实施例指如下情况，即，由于利用了SIP(System inpackage封装内系统)技术而使得具有用于高频率电路的电感线圈的芯片和其它的芯片重叠的情况下，将用于切断由电感线圈产生的磁力线的屏蔽层设在两片芯片之间。
图1显示的是与本发明的第1实施例有关的SIP构造的半导体器件的概略剖视图。图2显示的是与本发明的第1实施例有关的电感线圈的外径和屏蔽层的大小的关系的平面图。以下，说明与第1实施例有关的SIP构造的半导体器件。
如图1所示，根据SIP技术，第1和第2芯片10，20重叠。第1芯片10包含：半导体基板11，设置于这个半导体基板11的表面上的元件12，设置于半导体基板11的上方的电感线圈14。第2芯片20是包含导电层22。另外，第1芯片的背面(半导体基板11的背面)形成了绝缘膜18，绝缘膜18和第1芯片相对的面和相反侧的面以及第1芯片10的侧面上形成了例如由磁性材料构成的屏蔽层19。像这样，为了抑制由电感线圈14发出的磁力线对导电层22产生不良影响，第1和第2芯片10，20之间，具体地说电感线圈14和导电层22之间，设置屏蔽层19。
在此，作为由磁性材料构成的屏蔽层19的材料，例如，优选Ni单质、Fe单质、Co单质或含Ni、Fe、Co之中至少一种金属的材料。这个包含Ni、Fe、Co之中至少一种金属的材料，包含Ni、Fe、Co之中任何一种金属的合金，以及由Ni、Fe、Co的组合构成的合金(例如NiFe，CoFe等)。
此外，作为屏蔽层19的材料，可以是自旋极化率大的四氧化三铁、CrO2，RXMnO3-y(R；稀土类、X；Ca、Ba、Sr)等的氧化物系的材料，也可以是NiMnSb，PtMnSb的锰铝铜磁性合金材料。另外，屏蔽层19的磁性材料中，只要不失去磁性，可以含一些Ag，Cu，Au，Al，Mg，Si，Bi，Ta，B，C，O，N，Pd，Pt，Zr，Ir，W，Mo，Nb等的非磁性元素。
电感线圈14，例如是平面型的螺旋形线圈(参照图2)，由低电阻的材料如Al，Cu，Au等形成。
导电层22，例如是金属布线，晶体管的栅电极，接触等，例如由Al，Cu，W，多晶硅等形成。
元件12，例如是MOS晶体管。这个MOS晶体管的栅电极的最小栅长，例如在110nm以下。另外，作为元件12的一个例子图示了晶体管，但并不仅限于此，例如也可以将布线、接触、电容器等设在第1芯片10中。
绝缘膜18，例如由氧化硅膜形成。这个绝缘膜18并不一定是必要的，屏蔽层19，比起直接形成于半导体基板11的背面，优选隔着绝缘膜18形成。这是因为，若不设置绝缘膜18，则在导电性的屏蔽层19的情况下相邻的元件之间有导通的可能性，与此相对，通过设置绝缘膜18，使相邻元件之间不导通，能够抑制噪音进入相邻元件内。像这样，为了使绝缘膜18有不导通的功能，绝缘膜18优选例如具有大于等于3nm的膜厚。
如图2所示，为了切断由电感线圈14发出的磁力线，屏蔽层19的面积优选比电感线圈14存在的面积大。即，屏蔽层19的面积，优选从电感线圈14的最外侧的布线起朝外至少扩展到电感线圈14的外径X的大小。换言之，屏蔽层19的宽Y，优选大于等于电感线圈14的外径X的3倍。这是因为，可以认为由电感线圈14的最外侧的布线发出的磁力线向电感线圈14的外侧扩展到电感线圈14的外径X左右，为了可靠地把扩展到最外侧的磁力线切断，需要上述宽度。例如，电感线圈14的外径X在100μm至400μm的情况，屏蔽层19的宽Y在300μm至1200μm以上即可。
图3至图8，显示的是与本发明的第1实施例有关的SIP构造的半导体器件的制造工序的剖视图。以下，说明与本发明的第1实施例有关的半导体器件的制造方法。在此，芯片的切割使用了半切断切割法。
首先，如图3所示，第1芯片例如如下形成。在半导体基板(例如硅基板)11上例如形成MOS晶体管等的元件12，在半导体基板11及元件12上形成绝缘膜(例如氧化硅膜)13。接着，在这个绝缘膜13上形成电感线圈14，在绝缘膜13及电感线圈14上形成绝缘膜(例如氧化硅膜)15。像这样形成的第1芯片10的膜厚C1例如为750μm左右，半导体基板11的膜厚S1例如为747μm左右。
接着，如图4所示，第1芯片10通过例如像RIE(Reactive IonEtching反应离子刻蚀)这样的各向异性刻蚀加工，形成槽16。这个槽16从芯片10的表面(绝缘膜15的表面)到半导体基板11内都是贯通的，具有例如50μm左右的深度D。
接着，如图5所示，在第1芯片10的表面(绝缘膜15的表面)上粘贴保护带17。
接着，如图6所示，例如用研磨机研磨没有保护带17的芯片10的背面(半导体基板11的背面)。通过研磨，第1芯片11的膜厚C2薄至例如23μm左右，半导体基板11的膜厚S2例如薄至20μm左右。因此，芯片10的背面被研磨到槽16的深度D以上，槽16的底面开口，第1芯片10被切割。
接着，如图7所示，为了减缓刻蚀速度，由研磨改为干法刻蚀或湿法刻蚀，进一步刻蚀半导体基板11的背面。其结果是，第1芯片11的膜厚C3进一步薄至例如4.6μm左右，半导体基板11的膜厚S3进一步薄至例如1.6μm左右。
这个刻蚀，可以是各向同性刻蚀、也可以是各向异性刻蚀，但优选各向异性刻蚀。这是因为，比起各向同性刻蚀，各向异性刻蚀能够保证半导体基板11的薄膜化的均一性。
另外，像这样刻蚀之后，半导体基板11的背面自然形成了氧化膜(氧化硅膜)18，这个氧化膜18的绝缘性不充分时，溅射氧的等离子体等使其氧化即可。
接着，如图8所示，例如使用溅射法，在绝缘膜18上、保护带17上及槽16的侧面上淀积由磁性材料构成的屏蔽层19。在此，屏蔽层19、除了溅射法以外也可以使用CVD(Chemical VaporDeposition化学气相淀积法)等形成，但优选溅射法。这是因为，比起高温处理的CVD法，低温处理的溅射法不用担心保护带17溶化。而且，比起CVD法，溅射法更容易使由磁性材料构成的屏蔽层19附着。
接着，如图1所示，例如利用切割等将第1芯片10切成个个芯片。接着，准备好绝缘膜21内设置了导电层22的第2芯片20之后，粘贴第1芯片和第2芯片。此时，为了使屏蔽层19存在于电感线圈14和导电层22之间，将形成于半导体基板11的背面的屏蔽层19和第2芯片粘贴。其后，剥去保护带17。这样，两片芯片10，20重叠的SIP(System in package封装内系统)构造完成。
图9(a)，(b)显示的是在与本发明的第1实施例有关的薄膜基板上淀积屏蔽层之后的TEM(Transmission Electron Microscope：透射型电子显微镜)照片。图10显示的是图9(a)，(b)的屏蔽层的分量比用EPMA(Electron Probe Micro Analysis：电子探针微分析法)分析的结果。在此说明，在所述制造方法中，在半导体基板和屏蔽层之间形成绝缘膜。
图9(a)是用TEM拍摄的在被薄膜化的半导体基板11的背面淀积屏蔽层19之后的状态(图8的工序)。把图9(a)的框内区域扩大，如图9(b)所示，半导体基板11的背面和屏蔽层19之间，形成了绝缘膜18。在这个实验中，将半导体基板11研磨至1.7μm，将50μm的由NiFe膜构成的屏蔽层19淀积在半导体基板11的背面上，在这种情况下，形成了11nm的绝缘膜18。因此，虽然由NiFe膜构成的屏蔽层19是金属层，但是在这个屏蔽层19和半导体基板11之间因为形成了绝缘膜18，所以能够防止屏蔽层19和半导体基板11之间的导通。
另外，本实验，由NiFe膜构成的屏蔽层19的分量比用EPMA分析的结果，如图10所示，Fe是16.1％，Ni是83.9％。
图11显示的是与本发明的第1实施例有关的屏蔽层由NiFe膜形成的情况下的Fe的含量和电阻率的关系。在此说明，屏蔽层例如由NiFe膜形成的情况下，Fe的含量优选多少。
如图11所示，屏蔽层19中Fe的含量即使从100％减少至20％左右，屏蔽层19的电阻率也几乎不变，Fe的含量若降至20％以下，则屏蔽层19的电阻率逐渐上升。
在此，由于由电感线圈14产生的磁场，电感线圈14的下面产生了感应电动势，因为感应电流＝感应电动势/电阻值，所以屏蔽层19的电阻值低，产生于导电层22的感应电流就容易流动。因此，屏蔽层19的电阻，优选尽可能高的。由此，屏蔽层19由NiFe膜形成时，NiFe膜的Fe的含量优选小于等于20％。
因此，屏蔽层19，比起由导电性的磁性材料形成，优选由绝缘性的磁性材料形成。在此，作为导电性的磁性材料的一个例子，可以举出坡莫合金系的磁性材料，作为绝缘性的磁性材料的一个例子，可以举出铁氧体系的磁性材料。另外，由导电性的磁性材料形成屏蔽层19时，金属含量在例如在50％以下即可。
图12显示的是伴随与本发明的第1实施例有关的屏蔽层的膜厚的变化电感线圈的Q值的频率依存性。在此，说明优选的屏蔽层的膜厚在多少左右。另外，图12是半导体基板膜厚为1.7μm，屏蔽层由NiFe膜形成的情况下的结果。
如图12所示，使屏蔽层19的膜厚由10变至50、100至300nm。10，50nm的情况下若频率增大则电感线圈14的Q值也变高，100nm的情况下在800MHz左右电感线圈14的Q值稍微劣化，进而在300nm时，可以知道800MHz至1200MHz左右电感线圈14的Q值大幅度劣化。可以认为这是因为由NiFe膜形成的屏蔽层19的膜厚加厚，屏蔽层19的电阻值下降，使得导电层22内感应电流容易流动。因此，屏蔽层19的膜厚优选较薄的，由NiFe膜形成屏蔽层19时，NiFe膜的膜厚例如优选小于50nm。但是，为了得到切断磁力线的效果，屏蔽层19的膜厚优选大于等于1nm。
图13(a)(b)显示的是与本发明的第1实施例有关的SIP构造的半导体器件的概略剖视图。图13(a)显示的是没有屏蔽层的情况，图13(b)显示的是有屏蔽层的情况。图14(a)，(b)显示的是与本发明的第1实施例有关的电感线圈的Q值的频率依存性的图，图14(a)显示的是没有屏蔽层的情况，图14(b)显示的是有屏蔽层的情况。在此，根据基板的背面有屏蔽层的情况和没有屏蔽层的情况，说明由电感线圈产生的磁场(磁力线)对导电层施加的影响的不同以及伴随基板的薄膜化的电感线圈的Q值的不同。
首先，利用图13(a)及图14(a)，说明没有屏蔽层的情况。
如图13(a)所示，电流I1流过电感线圈14，这个电流I1产生了磁场Ha，这个磁场Ha到达第2芯片20的导电层22的附近。其结果是，由于这个磁场Ha导电层22内产生了感应电流I2。
并且，半导体基板11越薄，电感线圈14和导电层22的距离越短，故导电层22容易受磁场Ha的影响，感应电流I2也增大。
因此，如图14(a)所示，随着半导体基板11变薄，由感应电流I2产生的能量损耗增大，电感线圈14的Q值逐渐下降。
接着，利用图13(b)及图14(b)，说明有屏蔽层的情况。
如图13(b)所示，电流I1流过电感线圈14，这个电流I1产生了磁场Hb。但是，这个磁场Hb通过屏蔽层19之际，由于屏蔽层19的磁化，屏蔽层19的面上水平方向(纸面的横方向)的磁场分量Hbx变大，屏蔽层19的面上垂直方向(纸面的纵方向)的磁场分量Hby变小。由此，磁场Hb被屏蔽层19屏蔽，抑制了磁场Hb扩展到第2芯片20一侧。换言之，即使第1芯片10内的电感线圈14发出了磁力线，通过屏蔽层19的屏蔽效应，可以减少进入第2芯片内20内的导电层22的磁力线的数量，因此可以减小导电层22内产生的感应电流。
因此，即使是在半导体基板11较薄、电感线圈14和导电层22之间的距离较短的情况下，通过屏蔽层19的屏蔽效应，可以抑制导电层22内产生的感应电流的增大。
因此，如图14(b)所示，即使在半导体基板11的膜厚由50～750μm变薄到20μm或1.7μm的情况下，通过屏蔽层19可以抑制由感应电流产生的能量损耗的增加，因此可以抑制电感线圈14的Q值的劣化。
另外，即使不能100％防止磁力线进入导电层22，只要能抑制磁力线的进入，就可以如图14(b)所示充分抑制Q值的劣化。
通过所述第1实施例，可以得到如下效果。
在(a)第1及第2的芯片10，20之间(电感线圈14和导电层22之间)设置有由磁性材料构成的屏蔽层19。因此，可以通过屏蔽层19切断由电感线圈14产生的磁场扩及到导电层22。因此，可以抑制导电层22内感应电流的产生，从而可以抑制电感线圈14的Q值的劣化。而且，可以抑制电感线圈14下面的半导体基板11内感应电动势的产生，因此可以抑制基板噪音的产生。
(b)图15显示的是在没有设置屏蔽层的情况下，电感线圈14的Q值劣化的芯片的膜厚与电感线圈14的外径的关系。由结果可见，电感线圈14的外径为400μm的情况下，芯片的膜厚为500μm左右Q值开始劣化，电感线圈14的外径为200μm的情况下，芯片的膜厚为200μm左右Q值开始劣化，电感线圈14的外径为100μm的情况下，芯片的膜厚为100μm左右Q值开始劣化。即，可以知道电感线圈14的外径和Q值劣化芯片的膜厚几乎是一致的。
在此，一般使用的电感线圈14的外径是由100μm至400μm的大小，可以认为在SIP构造中使用比电感线圈14的外径薄的薄膜化的芯片。但是，由图15的结果可知，为了抑制Q值的下降，芯片的膜厚优选比电感线圈14的外径厚。像这样，在没有设置屏蔽层的情况下，考虑到抑制Q值的劣化，芯片的膜厚受电感线圈14的外径的制约。
与此相对，在第1实施例中，因为设置了屏蔽层19，芯片即使比电感线圈14的外径薄，也可以通过屏蔽层19的屏蔽效应抑制Q值的劣化。因此，在第1实施例中，可以不受电感线圈14的外径的制约地使芯片的膜厚变薄。因此，在SIP构造中，可以不受电感线圈14的外径的制约地增加层叠的芯片的数量。像这样，在第1实施例中，芯片的膜厚可以比电感线圈14的外径薄，即，可以使半导体基板11的膜厚比电感线圈14的外径薄。
(c)图16显示的是高度为500μm的空间内层叠的芯片的数量与硅基板的膜厚的关系。如图3所示，可以知道通过薄化硅基板的膜厚，显著增加芯片的数量。由此可以说，芯片的薄膜化技术是非常重要的。
但是，至今为止的芯片的薄膜化的限度，一般认为在20μm左右。理由如下所示。首先，若用研磨机使硅基板薄膜化，则硅基板的膜厚的可控性差，存在+/-5μm的膜厚的偏差，所以，硅基板一旦减薄至5μm以下，晶片面内就会产生不存在芯片的部分，成品率显著降低。另外，用研磨机刻蚀速度快，有可能把硅基板研磨的过薄，不能精确控制硅基板的膜厚。另外，若用研磨机研磨硅基板，则对芯片的压力大，薄膜化的芯片容易破损。
与此相对，在第1实施例中，在使半导体基板11变薄的刻蚀之际(图6及图7的工序)，由研磨机改为比研磨机速度低的干法刻蚀或湿法刻蚀。因此，因为刻蚀速度变慢，容易控制半导体基板11的膜厚。另外，可以抑制刻蚀时对芯片的压力，可以避免芯片破损的问题。由以上可知，比起只用研磨机进行芯片的薄膜化的情况，芯片容易变薄，可以增加芯片的层叠数。具体来说，芯片10的膜厚C3例如可以薄到4.6μm左右，可以形成历来困难的20μm以下厚度的芯片。
第2实施例
第2实施例，用SOI(Silicon On Insulator绝缘体基硅)基板代替了第1实施例中使用的通常的半导体基板。
图17显示的是与本发明的第2实施例有关的SIP构造的半导体器件的概略剖视图。以下，说明与第2实施例有关的半导体器件。
如图17所示，在第2实施例中，与第1实施例的不同点主要在于：第1芯片10采用了SOI基板30，构成SOI基板30的埋入式绝缘膜32取代了图1的绝缘膜18，第1芯片10的侧面不存在屏蔽层19。
在此，SOI基板30由半导体基板31和埋入式绝缘膜32以及半导体层33构成，在图17中，半导体基板31被研磨至消失。因此，构成SOI基板30的埋入式绝缘膜32上设置了屏蔽层19。另外，埋入式绝缘膜32作为使半导体层33和屏蔽层19不导通的层发挥作用。
另外，通过下述制造方法，屏蔽层19，没有形成于第1芯片10的侧面，只设置于第1芯片10的背面(埋入式绝缘膜32上)。在此，像第1实施例那样第1芯片10的侧面也形成屏蔽层19的情况可以提高屏蔽效应，但像第2实施例那样屏蔽层19即使只形成于第1芯片10的背面，仍具有充分的抑制Q值劣化的屏蔽效应。
图18至图23，显示的是与本发明的第2实施例有关的SIP构造的半导体器件的制造工序的剖视图。以下，说明与第2实施例有关的半导体器件的制造方法。在此，与第1实施例一样，芯片的切割采用的是半切断切割法。
首先，如图18所示，第1芯片10例如如下所示形成。由半导体基板(例如硅基板)31和埋入式绝缘膜32以及半导体层33构成的SOI基板30上形成例如MOS晶体管等的元件12，在半导体基板11及元件12上形成绝缘膜(例如氧化硅膜)13。接着，在这个绝缘膜13上形成电感线圈14，在绝缘膜13及电感线圈14上形成绝缘膜(例如氧化硅膜)15。像这样形成的第1芯片10的膜厚C1’，例如在755μm左右，半导体基板31的膜厚S1’例如在750μm左右。
接着，如图19所示，第1芯片10通过例如RIE这样的各向异性刻蚀加工，形成槽16。这个槽16由芯片10的表面(绝缘膜15的表面)到埋入式绝缘膜32都是贯通的，例如具有5μm的深度D。
接着，如图20所示，在芯片10的表面(绝缘膜15的表面)粘贴保护带17。
接着，如图21所示，例如用研磨机研磨没有保护带17的芯片10的背面(半导体基板31的背面)，使其薄至半导体基板31完全没有的程度。其结果是，第1芯片11的膜厚C2’例如薄至25μm左右，半导体基板31的膜厚S2’例如薄至20μm左右。
在此，第1实施例的图6所示的工序中，芯片10的背面通过研磨至槽16的深度D以上，槽16的底面开口，第1芯片10被切割。与此相对，第2实施例的图20所示的工序中，芯片10的背面没有被研磨至槽16的深度D’以上，在这个阶段第1芯片10还没有被切割
接着，如图22所示，为了减缓刻蚀速度，由研磨改为干法刻蚀或湿法刻蚀，半导体基板31的背面被进一步刻蚀到露出埋入式绝缘膜32。其结果是，第1芯片11的膜厚C3’进一步薄至例如5μm左右。
在此，第1实施例的图7所示的工序中，半导体基板11的背面自然形成了氧化膜(氧化硅膜)18。与此相对，第2实施例的图22所示的工序中，因为存在埋入式绝缘膜，故没有形成自然氧化膜。
接着，如图23所示，例如采用溅射法，在埋入式绝缘膜32上淀积由磁性材料构成的屏蔽层19。
接着，如图17所示，例如利用切割等将第1芯片10切成个个芯片。接着，绝缘膜21内设置了导电层22的第2芯片20准备好之后，将第1芯片和第2芯片粘贴。此时，为了使屏蔽层19存在于电感线圈14和导电层22之间，将形成于第1芯片10的背面的屏蔽层19和第2芯片20贴合。其后，剥去保护带17。这样，两片芯片10，20重叠的SIP构造完成。
根据所述第2实施例，不仅能得到与第1实施例相同的效果，而且还能得到如下效果。
首先，在图19的工序中，形成槽16之际，可以将SOI基板30的埋入式绝缘膜32作为阻挡层来控制刻蚀，因此槽16的深度D’的控制变得容易。
另外，在图22的工序中，刻蚀半导体基板31之际，因为作为硅基板的半导体基板31与作为氧化膜的埋入式绝缘膜的选择比高，故可以用埋入式绝缘膜32使刻蚀停止。因此，半导体基板31的刻蚀的控制变得容易，可以防止由于刻蚀对半导体层33造成的不良影响。
另外，本发明并不仅限于所述各实施例，在实施阶段只要在不脱离宗旨的范围内，可以进行以下种种变形。
(1)在所述第1及第2实施例中，说明了多个芯片重叠的SIP构造，但封装一个芯片的构造也适用于本发明。例如，如图24所示，设在管壳41上的导体板42上搭载芯片10，该芯片10通过金属线43连接于导体板42的情况下，通过屏蔽层19的屏蔽效应，可以防止由电感线圈24发出的磁力线对导体板42施加不良影响。
(2)如图25所示，第1及第2的芯片10，20，也可以用含磁性材料的粘合剂51进行粘贴。由磁性材料形成这个粘合剂51，可以用这个粘合剂51进一步切断磁力线。
(3)在所述第1及第2的实施例中，屏蔽层19只设置于第1芯片10，但如图26所示，还可以在第2芯片20的第1芯片10一侧的面上设置屏蔽层23。在这种情况下，可以进一步提高磁力线的屏蔽效应。
(4)屏蔽层19，并不一定要形成于第1芯片10的背面的整个平面。只要能得到磁力线的屏蔽效应，如图27所示，屏蔽层19部分性地形成于第1芯片的背面也是可以的。其结果，可以利用屏蔽层19的间隙24，将第2芯片的20的焊盘25朝外引出，设在间隙24上。另外，设置贯通第1芯片10的半导体基板11及绝缘膜18的金属层26，通过使这个金属层26和焊盘25连接，可以用最短的距离连接第1及第2芯片10，20。由此，比起把焊盘设置于每个芯片、通过引线进行芯片之间的信号交流的情况(例如参照图29)，在图27的情况下，第1及第2芯片10，20之间的信号线最短，因此可以减少信号传送的延迟及损失。
(5)电感线圈14的周围，还可以设置由磁性材料构成的屏蔽层。例如，如图28所示，也可以在电感线圈14的上面及侧面上设置由磁性材料构成的屏蔽层52。在这种情况下，可以进一步提高磁力线的屏蔽效应。
(6)所述第1及第2实施例中，采用了半切断切割法，通过预先形成的槽16切割芯片，防止芯片的破裂等。但是，并不仅限于半切断切割法，例如，也可以在第1芯片10上粘贴保护带17，研磨第1芯片10的背面之后，将第1芯片10和保护带17一起细分化后与第2芯片贴合在一起。
(7)所述第1及第2实施例中，举出了两个芯片层叠的SIP构造的例子，也可以层叠3个或更多的芯片。例如，如图29及图30所示，4个芯片20，10，60，70层叠，每个芯片20，10，60，70的上面设置焊盘81，82，83，84，用金属线85，86，87，88连接于管壳80上也可。在这种情况下，管壳80上层叠的芯片，优选越往上越小(金字塔状)地层叠。
在此，图29的情况，不具有电感线圈的芯片和具有电感线圈的芯片交替层叠。即，不具有电感线圈的芯片20上重叠具有电感线圈14的芯片10，在这个芯片10上重叠不具有电感线圈的芯片60，并在这个芯片60上重叠具有电感线圈74的芯片70。另外，由电感线圈14产生的磁场，通过屏蔽层19抑制其扩及到芯片20。并且，通过屏蔽层63抑制其扩及到芯片60。同样，电感线圈74产生的磁场通过屏蔽层79抑制其扩及到芯片60。
另一方面，图30的情况，以由具有电感线圈的两个芯片把不具有电感线圈的芯片夹在中间的方式层叠。即，在不具有电感线圈的芯片20上重叠具有电感线圈14的芯片10，在这个芯片10上重叠具有电感线圈74的芯片70，并在这个芯片70上重叠不具有电感线圈的芯片60。另外，由电感线圈14产生的磁场通过屏蔽层19抑制其扩及到芯片20。同样，由电感线圈74产生的磁场，通过屏蔽层79抑制其扩及到芯片10，并且，用屏蔽层63抑制其扩及到芯片60。
另外，具有电感线圈14，74的芯片10，70，例如是具有逻辑电路的芯片，不具有电感线圈的芯片20，60，例如是具有模拟电路的芯片。
(8)屏蔽层19，只要能作为屏蔽磁性的层(磁屏蔽层)而发挥作用，并不一定限定为用磁性材料形成。例如，屏蔽层19可以例如由具有500欧姆以上的高电阻的金属层形成。在此，为了使由金属层构成的屏蔽层19的电阻为500欧姆以上，最好使屏蔽层19的膜厚非常薄，或作为屏蔽层19的材料挑选高电阻的金属材料。

Claims (20)

1.一种半导体器件，具备：具有电感线圈的第1芯片，与所述第1芯片重叠、具有导电层的第2芯片，以及设置于所述第1和第2芯片之间的第1磁屏蔽层。
2.如权利要求1所述的半导体器件，所述第1芯片具备：具有表面和背面的半导体基板，以及形成于所述半导体基板的所述表面的所述电感线圈，所述第1磁屏蔽层，设置于所述半导体基板的所述背面。
3.如权利要求1所述的半导体器件，还具有设置在所述第1芯片的侧面的第2磁屏蔽层。
4.如权利要求1所述的半导体器件，所述第1磁屏蔽层的宽度大于等于所述电感线圈的外径的3倍。
5.如权利要求1所述的半导体器件，所述第1磁屏蔽层的面积，比所述电感线圈的存在面积大。
6.如权利要求1所述的半导体器件，所述第1磁屏蔽层，由磁性材料形成。
7.如权利要求1所述的半导体器件，所述第1磁屏蔽层，由Ni单质、Fe单质、Co单质、或包含Ni、Fe、Co之中的至少一种金属的磁性材料构成。
8.如权利要求1所述的半导体器件，所述第1磁屏蔽层，由铁氧体系磁性材料或坡莫合金系磁性材料构成。
9.如权利要求1所述的半导体器件，所述第1磁屏蔽层，由Fe和Ni的合金形成，所述合金的Fe的含量小于等于20％。
10.如权利要求1所述的半导体器件，所述第1磁屏蔽层，由Fe和Ni的合金形成，所述第1磁屏蔽层的膜厚不到50nm。
11.如权利要求2所述的半导体器件，所述半导体基板的膜厚，比所述电感线圈的外径薄。
12.如权利要求1所述的半导体器件，所述第1芯片的膜厚，比所述电感线圈的外径薄。
13.如权利要求2所述的半导体器件，进一步具备设置于所述第1磁屏蔽层与所述半导体基板的所述背面之间的具有大于等于3nm的膜厚的绝缘膜。
14.如权利要求1所述的半导体器件，所述第1芯片，具有构成SOI基板的埋入绝缘膜和半导体层，所述第1磁屏蔽层，设置于所述埋入绝缘膜上。
15.如权利要求1所述的半导体器件，还具备将所述第1及第2芯片粘贴的含磁性材料的粘合剂。
16.如权利要求1所述的半导体器件，进一步具备设置于所述第2的芯片的位于所述第1芯片一侧的面上的第2磁屏蔽层。
17.如权利要求1所述的半导体器件，所述第1磁屏蔽层，在所述第1芯片的背面局部具有间隙地形成。
18.如权利要求17所述的半导体器件，所述第2芯片的焊盘设置于所述间隙。
19.如权利要求1的半导体器件，进一步具备设置于所述电感线圈周围的第2磁屏蔽层。
20.如权利要求19所述的半导体器件，所述第2磁屏蔽层，设置于所述电感线圈的上面及侧面。
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