CN1630032B - 设计图形校正方法、掩模制造方法及半导体器件制造方法 - Google Patents

设计图形校正方法、掩模制造方法及半导体器件制造方法 Download PDF

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CN1630032B
CN1630032B CN2004101013575A CN200410101357A CN1630032B CN 1630032 B CN1630032 B CN 1630032B CN 2004101013575 A CN2004101013575 A CN 2004101013575A CN 200410101357 A CN200410101357 A CN 200410101357A CN 1630032 B CN1630032 B CN 1630032B
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layer
shape
pattern
graphic
design
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CN1630032A (zh
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小谷敏也
姜帅现
市川裕隆
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Toshiba Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
CN2004101013575A 2003-12-17 2004-12-17 设计图形校正方法、掩模制造方法及半导体器件制造方法 Expired - Fee Related CN1630032B (zh)

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JP419600/2003 2003-12-17
JP2003419600A JP2005181523A (ja) 2003-12-17 2003-12-17 設計パターン補正方法、マスクパターン作成方法、半導体装置の製造方法、設計パターン補正システム、及び設計パターン補正プログラム

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CN1630032A CN1630032A (zh) 2005-06-22
CN1630032B true CN1630032B (zh) 2010-05-12

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US (1) US7266801B2 (enExample)
JP (1) JP2005181523A (enExample)
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TW (1) TWI256527B (enExample)

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JP4817746B2 (ja) * 2005-07-27 2011-11-16 株式会社東芝 半導体装置の設計データ処理方法、そのプログラム、及び半導体装置の製造方法
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Publication number Publication date
US20050235245A1 (en) 2005-10-20
TWI256527B (en) 2006-06-11
TW200532398A (en) 2005-10-01
CN1630032A (zh) 2005-06-22
US7266801B2 (en) 2007-09-04
JP2005181523A (ja) 2005-07-07

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