CN1604278B - 处理栅极结构的方法 - Google Patents

处理栅极结构的方法 Download PDF

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CN1604278B
CN1604278B CN2004100739255A CN200410073925A CN1604278B CN 1604278 B CN1604278 B CN 1604278B CN 2004100739255 A CN2004100739255 A CN 2004100739255A CN 200410073925 A CN200410073925 A CN 200410073925A CN 1604278 B CN1604278 B CN 1604278B
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CN1604278A (zh
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王铭芳
侯拓宏
麦凯玲
姚亮吉
陈世昌
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种处理栅极结构的方法，以改善电效能特性，此栅极结构包括高介电常数栅极堆栈介电层，此处理栅极结构的方法包括提供一栅极堆栈介电层于硅基底上，此栅极堆栈介电层包括一二元(binary)氧化物；形成一多晶硅层于上述栅极堆栈介电层上；进行光刻图案化与蚀刻以形成一栅极结构；以及对上述栅极结构进行至少一等离子处理，此等离子处理包括一等离子源气体是择自于氢气、氮气、氧气与氨气所组成的族群中。

Description

处理栅极结构的方法
技术领域
本发明是有关于一种在微集成电路制程里的高介电常数CMOS晶体管的栅极堆栈层的制程，且特别有关于一种处理栅极结构的方法，包括高介电常数介电栅极堆栈层，以改善CMOS组件中的平带电压的电性。
背景技术
金属氧化物半导体(MOS)集成电路的制造涉及许多制程步骤，其中栅极氧化层通常是位于硅基底上的热成长二氧化硅，而此硅基底掺杂n型或p型掺杂质；为了形成个别MOS场效晶体管(MOSFET)，其中的栅极电极形成于栅极介电层上，然后引入掺杂质于半导体基底中以形成源极与漏极。许多现代半导体微电子的制程可形成具有小于0.25微米的临界尺寸(criticaldimensions)，例如包括特征尺寸(features sizes)小于0.13微米的较新组件。当设计标准(design rule)减小时，晶体管的尺寸也会随晶体管特征一样根据尺寸关系(scaling relationships)减小，如栅极长度；当栅极长度减小时，电流漏电的问题就会变得更加严重，如栅极引发漏极漏电(gateinduced drain leakage，简称GIDL)，此问题属于低功率组件的问题，需要增加晶体管的关闭电流(off current)来解决。
为了克服此现象，可在栅极堆栈介电层中利用高介电常数材料以得到与低介电常数材料相当的等效氧化层厚度(equivalent oxide thickness，简称EOT)，而EOT在半导体电子组件制造中有增加的趋势。由于高穿遂电流的因素，小于20埃的二氧化硅膜在CMOS组件中无法确实地当作栅极氧化层使用，所以现在业界努力地想以高介电材料来取代传统的二氧化硅栅极介电膜，使得较厚的栅极介电层得以形成，以大幅地地降低穿遂电流与栅极漏电流，进而克服在较小组件临界尺寸中以二氧化硅作为栅极介电层的严重限制。
然而，CMOS组件中的高介电常数栅极介电层的形成的困难点在于难以得到可令人接受的启始电压行为，如当高介电常数材料在NMOS与PMOS组件中作为栅极堆栈介电层时，平带电压或当量启始电压会常发生相对大的偏移，例如以氧化铪用作栅极堆栈介电层时，比一般用于NMOS组件中的二氧化硅栅极介电层具有300mV的偏移，而在PMOS组件则有700mV的偏移。
界面状态(interfacial states)不佳的存在被认为是造成平带电压与启始电压偏移的原因之一，有许多方法已被提出用来处理此现象，从基层(base)氧化层的处理至在多晶硅电极层沉积前的高介电常数介电质的后沉积退火，但这些方法迄今的成功有限，如其启始电压与一般或达成预期行为的二氧化硅栅极介电层的启始电压相比还是有很大的偏差，因此，具有令人可接受的电性的高介电常数的栅极堆栈介电层依然具有问题需克服，此令人可接受的电性包括在低功率CMOS组件中具有令人可接受的启始电压。
因此需要发展一种用于形成栅极结构的改良方法，包括用于CMOS组件中的高介电常数堆栈介电层，且其具有改良的电性，包括启始电压效能。
因此本发明的目的就是提供一种用于形成栅极结构的改良方法，包括在CMOS组件中的高介电常数堆栈介电层，且其具有改良的电性，包括启始电压效能，同时克服先前技艺中的其它缺点与不足。
发明内容
为达上述、其它与本发明的目的，本发明提供一种处理栅极结构的方法，此栅极结构包括高介电常数栅极堆栈介电层以改善电效能特性。
在一第一实施例中，处理栅极结构的方法包括提供一栅极堆栈介电层于硅基底上，此栅极堆栈介电层包括一二元(binary)氧化物；形成一栅极电极层于上述栅极堆栈介电层上；进行光刻图案化与蚀刻上述栅极堆栈介电层与上述栅极电极层以形成一栅极结构；以及对上述栅极结构进行至少一等离子处理，此等离子处理包括一等离子源气体是择自于氢气、氮气、氧气与氨气所组成的族群中。
附图说明
图1为本发明实施例的CMOS组件，此组件包括高介电常数堆栈介电层的形成。
图2A～图2C为本发明实施例栅极结构部分的剖面图，包括多层高介电常数堆栈介电层的制造步骤。
图3A为藉由较佳实施例所形成的CMOS组件的电容-电压(CV)数据图，以对应本发明实施例的制程方法。
图3B为藉由较佳实施例所形成的CMOS组件中，由CV数据所得的平带电压图，以对应本发明实施例的制程方法。
图4为本发明实施例的制程流程图。
符号说明：
12、22～半导体基底           14A～轻掺杂区
14B～源极漏极区              16～浅沟隔离区
18A～界面二氧化硅层          18B～高介电常数介电部分
18C  多晶硅栅极电极部分      20A～侧壁间隙壁
24～热成长SiO2界面层         26～高介电常数介电层
26B～高介电常数栅极介电部分  28～多晶硅栅极电极部分
具体实施方式
本发明这些与其它实施例、观点与特征可由下列更详尽地描述与附图的发明较佳实施例得以更清楚地了解。
虽然本发明的方法是以高介电常数栅极堆栈介电层的形成来作说明，但也可将本发明的方法应用在MOSFET组件中高介电常数栅极介电层的形成与微集成电路制程中的堆栈电容。
虽然本发明的方法是以高介电常数栅极介电层的使用来作说明，但也可将本发明的方法用在任何高介电常数的氧化物上，例如用于栅极介电层的形成的二元(binary)氧化材料，在此所称的高介电常数介电质是表示此材料具有的介电常数高于10，而基底是定义为任何的半导体基材材料，包括一般的硅半导体晶片。
图1为本发明实施例的CMOS晶体管剖面图，此晶体管具有的栅极结构包括高介电常数介电的栅极堆栈区域。如所示的半导体基底12，例如此基底可为硅基底，且包括以现有技艺方法在硅基底中形成轻掺杂区，即14A、源极漏极区，即14B，与浅沟隔离区，即16，其中的区域14A与14B常在栅极结构形成后形成。栅极结构的栅极介电部分为多层结构，如包括界面二氧化硅层18A、高介电常数介电部分18B。多晶硅栅极电极部分18C形成在上述栅极介电部分上。上述栅极结构是藉由现有方法所形成，包括先进行一全面性的多层沉积，且其最上层为多晶硅层，再进行光光刻图案化与各向异性蚀刻步骤。
在栅极结构形成后，再进行一般的第一离子注入制程以在硅基底中形成LDD区域，即14A。然后形成侧壁间隙壁，即20A，例如包括至少为氧化硅(即SiO2)、氮氧化硅(即SiON)与氮化硅(SiN)之一，此也包括藉由利用现有技艺中的一般沉积与回蚀刻制程以形成多层间隙壁的方法。然后再进行一自行对准的第二离子注入制程以形成源极/漏极区，即14B，此时侧壁间隙壁，即20A，作为注入掩模且根据所要形成的PMOS或NMOS型的组件来形成N型或P型掺杂区。
图2A为本发明实施例的栅极堆栈区域制造的局部放大(expanded)剖面图。在本实施例中所示的半导体基底22，可为(111)或(100)配向(orientation)的单晶硅，可为层状的半导体基底，如Si/SiGe或Si/SiO2/Si；此基底可为n或p型且较佳包括许多有源区，如N或P掺杂区以形成有源电荷载子区，以形成MOSFET组件的一部分。
请依然参阅本发明实施例中的图2A；在一第一步骤中，于硅基底22上方形成热成长SiO2界面层(也称为基层(base)氧化层)24前，先进行清洁步骤，例如，以标准清洁1(SC-1)与/或标准清洁2(SC-2)对硅基底进行清洁步骤，此清洁步骤可逐个或相继使用清洁溶液，包括NH4OH-H2O2-H2O与HCl-H2O2-H2O的混合液。
依然请参阅本发明实施例的图2A；在硅基底清洁制程后，界面氧化(SiO2)层24藉由湿或干热氧化或化学氧化方法形成于硅基底20上，其较佳的厚度约为5埃至30埃，其中高温湿或干热氧化成长方法可成长较佳高品质的Si/SiO2界面。
请参阅图2B；接下来至少一高介电常数介电层，即26，藉由一般方法沉积于界面氧化层22上；而界面氧化层24可选择性地进行表面处理，包括化学、等离子与/或退火处理，这些表面处理为现有技艺中用于高介电常数材料沉积里；此外，高介电常数介电层或高介电常数堆栈介电层也可直接沉积在硅基底上；然而，当使用二元(binary)氧化高介电常数介电质，如氧化铪时，界面氧化层，即24，具有较佳高介电常数介电稳定性。
高介电常数介电层或高介电常数堆栈介电层26可藉由一般方法沉积，包括原子层化学气相沉积(atomic layer chemical vapor deposition，简称ALCVD)、雷射镕削(Laser Ablation)与反应性直流电溅镀(reactive DCsputtering)。较佳的高介电常数介电质为二元金属氧化物，如氧化钽(Ta2O5)、氧化钛(TiO2)、氧化铪(HfO2)、氧化钇(Y2O3)、氧化镧(La2O5)、氧化锆(ZrO2)与其硅酸盐及铝酸盐。
上述的ALCVD沉积制程较佳在晶片基底被加热至约200℃～400℃时进行，此较佳的ALCVD制程可提供高等级的界面与膜的品质，例如，分子层相继地沉积，此分子层包括金属前驱物的分子层，而此前驱物可为金属-有机前驱物，接着控制金属-有机分子层的分解与氧化，以形成高介电常数介电层的一部分，此制程一直重复至完全形成高介电常数介电层；其它制程如利用金属-有机前驱物的MOCVD或PECVD也适用，但由于其电性品质较差，故为较不理想的沉积方法。
在一最佳实施例中，高介电常数介电材料可藉由ALCVD方法沉积单层或堆栈层氧化铪，此沉积温度需小于约300℃，较佳约为200℃，以减少晶格不相称的问题产生，而氧化铪的厚度与所需的等效氧化层厚度(equivalentoxide thickness，简称EOT)相当有关系，如为约5～30埃间，也可能在40～100埃间；接下来高介电常数介电层或多层高介电常数介电质可进行一次或多次退火步骤，较佳为一次介于约550～900℃间的氮气、氢气或氧气的退火步骤。
请参阅图2C；在高介电常数介电层，即26，沉积后，接着藉由一般方法沉积多晶硅层，如小于约580℃的LPCVD；接着再利用一般光刻图案化与蚀刻以蚀刻多晶硅层与氧化铪层，即26的一厚度，以形成多晶硅栅极电极部分28与高介电常数栅极介电部分26B；此蚀刻方式较佳为活性离子蚀刻(RIE)与/或化学蚀刻(chemically dependent etching，简称CDE)，同时留下至少部分的界面氧化层24以覆盖硅基底，以在随后的等离子处理制程中用以保护硅基底22。
根据本发明实施例的目的，在栅极蚀刻制程后，晶片的处理包括对栅极结构进行等离子处理制程；此等离子处理的压力较佳为100mTorr与10Torr间，更佳为1Torr与5Torr间；此等离子处理较佳的等离子源气体为氢气、氮气、氧气、氨气或上述的混合物，更佳为氢气、氮气或上述的混合物，最佳为氢气，因为它可以减少等离子所造成的损害，且在随后的退火制程中具有较有效率的热活性扩散特性。
等离子处理可包括一般等离子操作条件与等离子反应组件，其中等离子反应组件可包括诱导偶合等离子(inductively coupled plasma，简称ICP)源、平行板、电子回旋加速器共振(electron cyclotron resonance，简称ECR)、双等离子源(dual plasma source，简称DPS)与磁性增强结构(configurations)，较佳的等离子反应组件包括一DPS以容许个别晶片的偏压(biasing)；一般的等离子操作条件包括约100～600瓦的射频(RF)能量，且晶片的偏压介于0～300瓦间。
视反应组件的结构而定，如DPS反应组件，等离子处理的实行时间约为10～60分钟；在此等离子处理后，较佳再执行一后等离子处理退火制程，其气氛包括至少氢气、氮气、氧气与氨气之一，更佳为氢气、氮气与氨气的等离子处理且其以氮气或氢气为主要气氛，此退火步骤较佳在550℃～750℃下执行5～30分钟，且可在等离子处理原处(in-situ)或是在等离子处理外处(ex-situ)执行，当在等离子处理外处(ex-situ)执行时，可在分别单一晶片处理工具或一般炉管的批次晶片退火制程中执行。根据本发明的较佳实施例，栅极结构的等离子处理包括对多晶硅栅极电极与高介电常数堆栈介电层侧壁部分作等离子处理，接着再藉由后等离子处理退火以对平带电压以及与平带电压相关的启始电压作最佳的调整，以使与二氧化硅栅极介电质相关的CMOS组件的电性操作参数落在操作范围中。以下讨论未受特定理论限制；如因晶格不相称效应而在二元氧化物(即氧化铪)与多晶硅界面所产生的不连接或未饱和配位硅键，可藉由进行至少一等离子处理减少；在较佳实施例中，在等离子处理后更加再进行一退火处理；等离子植入原子如氢、氮与氧，更佳为氢与/或氮以渗入及热扩散至氧化铪/多晶硅界面，以保护不连续键或与不连续键键结，使界面态作为电子/电洞陷阱(traps)的情形可有效降低，进而改善PMOS与NMOS组件中的平带电压与平带电压相关的启始电压的行为。
如图3A为NMOS组件中的电容电压曲线(CV curve)图，其中纵轴为电容值，而横轴为供给在栅极上的电压，且A、B、C线分别表示沉积(A)：无等离子处理、沉积(B)：在氢气中进行30分钟等离子处理、沉积(C)：在氢气中进行60分钟等离子处理，而D线表示较佳实施例中在等离子处理后再进行氮气退火步骤；由图3A可知本发明较佳实施例(D线)所使用的方法的确可大幅改善CV曲线的特性，包括平带电压。
在图3B中，纵轴为平带电压的数据，横轴为则个别的栅极处理条件，其中栅极处理条件A1为单纯的沉积(无等离子处理或退火处理)，而栅极处理条件B1、C1、D1则分别对应较佳实施例中进行10、30、60分钟的氢气等离子处理，而栅极处理条件E1为较佳实施例中进行60分钟氢气等离子处理后再进行退火处理，而得到大幅改善的平带电压。
回到图1，在退火处理后再进行一般制程以完成CMOS组件，包括利用离子注入制程以在硅基底中形成LDD区，即14A，接着藉由侧壁间隙壁的形成，即20A，与随后的离子注入制程以形成源极/漏极，即14B。
图4为本发明实施例的制程流程图。在第一制程401中，提供界面氧化层于硅基底上；在制程403中，沉积至少一高介电常数介电层于界面氧化物上，其中的高介电常数介电层较佳为氧化铪；在制程405中沉积多晶硅层；在制程407中，图案化多晶硅层，且蚀刻多晶硅与高介电常数介电质的一厚度部分，以形成栅极结构；在制程409中，根据较佳实施例进行等离子处理；在制程411中，根据较佳实施例进行后等离子处理退火；在制程413中，进行一般制程以完成CMOS组件。
虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明，任何熟习此技艺者，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当视所附的权利要求范围所界定者为准。

Claims (20)

1.一种处理栅极结构的方法，以改善电效能特性，此栅极结构包括高介电常数栅极堆栈介电层，此处理栅极结构的方法包括：
提供一栅极堆栈介电层于硅基底上，此栅极堆栈介电层包括一二元氧化物；
形成一栅极电极层于上述栅极堆栈介电层上；
进行光刻图案化与蚀刻上述栅极堆栈介电层与上述栅极电极层以形成一栅极结构；以及
对上述栅极结构进行至少一等离子处理，此等离子处理包括一等离子源气体是择自于氢气、氮气、氧气与氨气所组成的族群中。
2.根据权利要求1所述的处理栅极结构的方法，尚包括在该至少一等离子处理后对该栅极结构的退火步骤。
3.根据权利要求2所述的处理栅极结构的方法，其中该退火步骤的温度为600℃～750℃。
4.根据权利要求2所述的处理栅极结构的方法，其中该退火步骤的气氛基本为氮气。
5.根据权利要求1所述的处理栅极结构的方法，其中该栅极堆栈介电层包括一最下方的二氧化硅层形成于硅基底上。
6.根据权利要求1所述的处理栅极结构的方法，其中该栅极堆栈介电层包括一高介电常数材料，是择自于氧化钽、氧化钛、氧化铪、氧化钇、氧化镧、氧化锆与其硅酸盐及铝酸盐所组成的族群中。
7.根据权利要求1所述的处理栅极结构的方法，其中该堆栈介电层基本由一最下层的二氧化硅层与一于其上的氧化铪层所组成。
8.根据权利要求7所述的处理栅极结构的方法，其中该氧化铪层以原子层化学气相沉积在300℃以下形成。
9.根据权利要求1所述的处理栅极结构的方法，其中该等离子源气体是择自于氢气与氮气所组成的族群中。
10.根据权利要求1所述的处理栅极结构的方法，其中该等离子处理所进行的时间为10～90分钟。
11.根据权利要求1所述的处理栅极结构的方法，其中该等离子处理所进行的压力为100mTorr～10Torr。
12.根据权利要求11所述的处理栅极结构的方法，其中该等离子处理所进行的压力为100mTorr～5Torr。
13.一种处理栅极结构的方法，以改善CMOS组件的平带电压与启始电压特性，此栅极结构包括高介电常数栅极堆栈介电层，此处理栅极结构的方法包括：
提供一栅极堆栈介电层于硅基底上，此栅极堆栈介电层包括至少一高介电常数介电质，此介电常数为10以上；
形成一多晶硅层于上述栅极堆栈介电层上；
进行光刻图案化与蚀刻以形成一栅极结构；
对上述栅极结构进行至少一等离子处理，此等离子处理包括一等离子源气体是择自于氢气、氮气、氧气与氨气所组成的族群中；以及
在上述至少一等离子处理后对上述栅极结构进行退火。
14.根据权利要求13所述的处理栅极结构的方法，其中该退火步骤的温度为600℃～750℃。
15.根据权利要求14所述的处理栅极结构的方法，其中该退火步骤的气氛是择自于氢气、氮气、氧气与氨气所组成的族群中。
16.根据权利要求13所述的处理栅极结构的方法，其中该栅极堆栈介电层包括一最下方的二氧化硅层形成于硅基底上。
17.根据权利要求13所述的处理栅极结构的方法，其中该高介电常数介电质是择自于氧化钽、氧化钛、氧化铪、氧化钇、氧化镧、氧化锆与其硅酸盐及铝酸盐所组成的族群中。
18.根据权利要求13所述的处理栅极结构的方法，其中该堆栈介电层基本由一最下层的二氧化硅层与一于其上的氧化铪层所组成。
19.根据权利要求13所述的处理栅极结构的方法，其中该等离子源气体基本由氢气所组成。
20.根据权利要求13所述的处理栅极结构的方法，其中该等离子处理所进行的压力为100mTorr～5Torr。
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