CN1531746A - 利用在氢气环境中退火在碳化硅层上制备氧化物层的方法 - Google Patents
利用在氢气环境中退火在碳化硅层上制备氧化物层的方法 Download PDFInfo
- Publication number
- CN1531746A CN1531746A CNA028081072A CN02808107A CN1531746A CN 1531746 A CN1531746 A CN 1531746A CN A028081072 A CNA028081072 A CN A028081072A CN 02808107 A CN02808107 A CN 02808107A CN 1531746 A CN1531746 A CN 1531746A
- Authority
- CN
- China
- Prior art keywords
- coating
- oxide skin
- oxide
- annealing
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000001257 hydrogen Substances 0.000 title claims abstract description 66
- 229910052739 hydrogen Inorganic materials 0.000 title claims abstract description 66
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 title claims abstract description 65
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 58
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title abstract description 3
- 238000000137 annealing Methods 0.000 claims abstract description 106
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims abstract description 46
- 239000007789 gas Substances 0.000 claims abstract description 39
- 150000004767 nitrides Chemical class 0.000 claims abstract description 17
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000001272 nitrous oxide Substances 0.000 claims abstract description 7
- 239000011248 coating agent Substances 0.000 claims description 73
- 238000000576 coating method Methods 0.000 claims description 73
- 238000000034 method Methods 0.000 claims description 36
- 238000007254 oxidation reaction Methods 0.000 claims description 30
- 230000003647 oxidation Effects 0.000 claims description 22
- 230000008569 process Effects 0.000 claims description 18
- 238000002360 preparation method Methods 0.000 claims description 14
- 238000012545 processing Methods 0.000 claims description 11
- 239000011261 inert gas Substances 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 10
- 229910044991 metal oxide Inorganic materials 0.000 claims description 5
- 150000004706 metal oxides Chemical class 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 229920001296 polysiloxane Polymers 0.000 claims description 3
- 238000005984 hydrogenation reaction Methods 0.000 claims description 2
- AZLYZRGJCVQKKK-UHFFFAOYSA-N dioxohydrazine Chemical compound O=NN=O AZLYZRGJCVQKKK-UHFFFAOYSA-N 0.000 claims 1
- 239000012212 insulator Substances 0.000 claims 1
- 239000002243 precursor Substances 0.000 abstract description 4
- 150000002431 hydrogen Chemical class 0.000 abstract 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 12
- 238000009826 distribution Methods 0.000 description 11
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 8
- 235000012431 wafers Nutrition 0.000 description 8
- 229910052757 nitrogen Inorganic materials 0.000 description 7
- 230000001590 oxidative effect Effects 0.000 description 7
- 229960003753 nitric oxide Drugs 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 230000005527 interface trap Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 230000002950 deficient Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000036541 health Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 238000003949 trap density measurement Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 239000002912 waste gas Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
- H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
- H01L21/02326—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen into a nitride layer, e.g. changing SiN to SiON
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/048—Making electrodes
- H01L21/049—Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
- H01L21/3145—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers formed by deposition from a gas or vapour
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Formation Of Insulating Films (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Hydrogen, Water And Hydrids (AREA)
- Solid-Sorbent Or Filter-Aiding Compositions (AREA)
Abstract
通过在一层碳化硅上制备氮化的氧化物层和在含氢气环境中退火该氮化的氧化物层,制备了碳化硅结构。氮化的氧化物层的制备可以通过以下过程提供:在氧化一氮和一氧化二氮至少之一中形成氧化物层和/或在氧化一氮和一氧化二氮至少之一中退火氧化物层。另外,氮化的氧化物层可以通过以下过程提供:制备氧化物层并在氧化物层上制备氮化物层以便提供氮化的氧化物层,在其上制备了氮化物层。此外,退火该氧化物层可以作为单独的步骤提供,和/或与另一个步骤如制备氮化物层或进行接触退火基本同时提供。氢气环境可以是纯氢气与其它气体组合的氢气和/或得自氢气前驱体。400℃或更高的退火温度是优选的。
Description
相关申请
本申请是2001年10月1日提交的美国专利申请序列号No.的题目为“在碳化硅层上氧化物层的N2O生长方法”(代理号5308-157IP)的部分继续,后者要求2001年5月30日提交的美国临时申请No.60/294,307,题目为“在碳化硅层上氧化物层的N2O生长方法”的优先权,并要求2001年4月12日提交的美国临时申请No.09/834,283,题目为“在碳化硅层上氧化物层的N2O生长方法”的优先权,并且是其部分继续。上述引用的申请每一个的公开内容并入本文作为参考,如同本文完全阐述了一样。
政府利益声明
本发明至少部分是在得到美国Air Force Wright Labs合同号F33615-99-C-2914的资助下完成的。政府可以在本发明中拥有一定权利。
技术领域
本发明涉及半导体器件的制备,更特别地涉及碳化硅(SiC)上氧化物层的制备。
背景技术
为了保护器件的暴露SiC表面和/或为了其它目的,用碳化硅制造的器件通常用氧化物层钝化,例如SiO2。然而,SiC和SiO2之间的界面可能不足以获得高表面电子迁移率。更具体地,SiC和SiO2之间的界面通常具有高界面态密度,其可能降低表面电子迁移率。
最近,在一氧化氮(NO)环境中热氧化物的退火表明在不需要p-穴注入的平面4H-SiC MOSFET结构中有前景。参见M.K.Das,L.A.Lipkin,J.W.Palmour,G.Y.Chung,J.R.Williams,K.McDonald和L.C.Feldman,“High Mobility 4H-SiC Inversion Mode MOSFETsUsing Thermally Grown,NO Annealed SiO2,”IEEE Device ResearchConference,Denver,CO,June 19-21,2000和G.Y.Chung,C.C.Tin,J.R.Williams,K.Mc Donald,R.A.Weller,S.T.Pantelides,L.C.Feldmam,M.K.Das和J.K.Palmour的已接收待出版的“Improved Inversion Channel Mobility for 4H-SiC MOSFETsFollowing High Temperature Anneals in Nitric Oxide,”IEEEElectron Device Letters,其公开内容并入本文作为参考,如同本文完全阐述一样。这种退火表明显著减小界面态密度接近导带边缘。G.Y.Chung,C.C.Tin,J.R.Williams,K.McDonald,M.Di Ventra,S.T.Pantelides,L.C.Feldam和R.A.Weller,“Effect of nitricoxide annealing on the interface trap densities near the bandedges in the 4H polytype of silicon carbide,”Applied PhysicsLetters,Vol.76,No.13,pp.1731-1715,March 2000,其公开内容并入本文作为参考,如同本文完全阐述一样。由于改进的MOS界面,在表面倒转层中获得高电子迁移率(35-95cm2/Vs)。
遗憾的是,NO危害健康,具有National Fire ProtectionAssociation(NFPA)的健康危险等级3,并且在其中通常进行氧化后退火的设备是对洁净室的大气敞开的。它们经常被排出,而且超过室内NO污染安全水平的危险是不可忽略的。
在N2O中生长氧化物是可能的,如J.P.Xu,P.T.Lai,C.L.Chan,B.Li和Y.C.Cheng,“Improved Performance andReliability of N2O-Grown Oxynitride on 6H-SiC,”IEEE ElectronDevice Letters,Vol.21,No.6,pp.298-300,June 2000中所述的,其公开内容并入本文作为参考,如同本文完全阐述一样。Xu等描述在纯N2O环境中在1100℃使SiC氧化360分钟并且在N2气中在1100℃退火1小时。
在1100℃的温度在6H-SiC上氧化物的生长后氮化也已经由Lai等研究。P.T.Lai,Supratic Chakraborty,C.L.Chan和Y.C.Cheng,“Effects of nitridation and annealing on interfaceproperties of thermally oxidized SiO2/SiC metal-oxide-semiconductor system,”Applied Physics Letters,Vol.76,No.25,pp.3744-3746,June 2000,其公开内容并入本文作为参考,如同本文完全阐述一样。但是,Lai等人推断,这样的处理使得界面质量变差,其可以用随后在O2中湿或干退火来改善,这种退火可以修复由于在N2O中的氮化诱导的损伤。而且,即使使用后续的O2退火,与没有在N2O中氮化的情况相比,Lai等人也没有看到界面态密度的任何明显减小。
除NO和N2O生长和退火之外,对其它环境中的生长后退火也进行了研究。例如,Suzuki等研究了在氢气中的氧化后退火。Suzuki等人的”Effect of Post-oxidation-annealing in Hydrogen onSiO2/4H-SiC Interface”,Material Science Forum,Vols.338-342,pp.1073-1076,2000。这些研究者报告了平带电压漂移和界面态密度可以通过在氩气和氢气中的氧化后退火来改善。在该研究中,4H-SiC在1200℃的干燥O2中氧化。然后在氩气或氢气中在400、700、800和1000℃进行30分钟的氧化后退火。但是,其它研究者已经报道,在氢气中的氧化后退火不能比其它气体中的氧化后退火提供更多的益处。Mrinal Das,“Fundamental Studies of the Silicon CarbideMOS Structure”Doctoral Thesis,Purdue University,1999年12月提交。
发明内容
本发明的实施方案通过以下过程制备一种碳化硅结构:即在一层碳化硅上制备一个氮化的氧化物层,和在含氢气的环境中使该氮化的氧化物层退火。通过在氧化一氮、一氧化二氮和/或含有反应性氮物质的环境至少之一中,形成、退火或者形成并退火氧化物层,可以制备这种氮化的氧化物层。另外,氮化的氧化物层可以通过以下过程提供:通过制备一个氧化物层并在该氧化物层上制备一个氮化物层,以便提供氮化的氧化物层,其上已经制备了氮化物层。氮化物层的这种形成可以提供氮化的氧化物层,并且可以氢化所述氮化的氧化物层,因为氢气可能是氮化物层形成的副产物。此外,在这样的实施方案中,氢气退火氧化物层基本可以与制备氮化物层同时提供。
在本发明的具体实施方案中,碳化硅层包含4H多型体碳化硅。碳化硅层可以是在非碳化硅基质上的碳化硅层、在碳化硅基质上的碳化硅层和/或一部分碳化硅基质。
在本发明的其它实施方案中,通过后续处理步骤提供对氧化物层退火,后续处理步骤在含氢气环境中把氧化物层加热到高于约400℃的温度,而不管该步骤是单独的退火步骤的一部分还是其它的处理步骤。在本发明的其它实施方案中,氧化物层在含氢气环境中在高于约400℃的温度下退火。氧化物层也可以在含氢气环境中在约400℃-约1000℃的温度下退火。在本发明的特定实施方案中,氧化物层在含氢气环境中在低于约900℃的温度下退火。优选地,氧化物层在含氢气环境中在约400℃-约800℃的温度下退火。另外,退火进行的时间可以大于约2分钟。
在本发明进一步的实施方案中,在含氢气环境中退火后的处理步骤,即高温处理步骤也可以在含氢气环境中进行。
在本发明的其它实施方案中,通过对与氧化物层相关的半导体器件形成金属化进行氢气退火。在这样的实施方案中,氧化层的氢气退火可以提供如下:在含氢气环境中在低于约900℃的温度下退火氧化物层。在这样的实施方案中,氧化物层的退火可以是接触退火。另外,可以形成碳化硅金属氧化物半导体器件,使其具有氧化物层作为金属氧化物半导体器件的门氧化物。
在本发明的特定实施方案中,氮化的氧化物在含有约4%氢气和约96%惰性气体的合成气体中退火。
在本发明的进一步的实施方案中,在碳化硅层上的氧化物层制备如下:用氧化一氮和一氧化二氮的至少一种氮化碳化硅层上的氧化物层,并在含氢气环境中在约400℃-约900℃的温度下使氮化的氧化物层退火至少约2分钟。
附图说明
图1A是说明根据本发明实施方案的氢气退火处理步骤的流程图;
图1B是说明根据本发明的进一步实施方案引入具有氢气退火的附加处理步骤的流程图;
图2是适用于本发明实施方案的管式炉的示意图;
图3是对于各种热氧化、生长后N2O退火和N2O氧化,来自导带的DIT与能级的关系图。
图4A和4B是根据本发明的实施方案,在4%氢气和96%惰性气体的合成气体中在800℃退火前后测定的,已经在1300℃进行N2O退火的氧化物的界面态密度图。
图5是根据本发明的实施方案,在4%氢气和96%惰性气体的合成气体中在800℃退火前后测定的电容器的电容与电压关系图,所述电容器具有已经在1300℃进行N2O退火的氧化物。
图6是根据本发明的实施方案,在4%氢气和96%惰性气体的合成气体中在800℃退火前后测定的,MOSFET的场效应迁移率与门电压的关系图,所述MOSFET具有已经在1300℃进行N2O退火的门氧化物。
发明详述
下文参考表示本发明的优选实施方案的附图更充分描述本发明。但是,该发明可以用许多不同形式实施,并且不应当认为限于本文阐述的实施方案;相反,提供这些实施方案使得该公开内容更充分完全,并且更充分地向本领域技术人员通报本发明的范围。在附图中,为了清楚,放大了层和区域的厚度。相同的数字在全文中表示相同的元件。将会理解的是,当诸如层、区域或基质的单元被称为在另一个单元“上”时,它可能直接在另一个单元上或者也可能存在插入其间的单元。相反,当一个单元被称为“直接在另一个单元上”时,不存在插入其间的单元。
本发明的实施方案提供可以改善任何器件中氧化层与SiC之间界面的方法,所述器件包含这样的界面。这些方法在SiC上产生的金属-氧化物-半导体(MOS)器件制备中是特别有利的。使用本发明的实施方案,可以急剧减少具有接近SiC导带的能级的界面态,这种缺陷的减少可能是有利的,因为这些缺陷可能限制MOS器件的有效表面通道迁移率。
现在参考图1A和1B描述本发明的实施方案,图1A和1B是表示根据本发明特定实施方案的操作的流程图。如图1A所示,本发明的实施方案利用氮化的氧化物层的退火,以进一步降低在碳化硅氧化物边界处的界面态密度。本文所用的术语氮化的氧化物层是指在化学反应性氮物质如氮前驱体中所形成或后续退火(作为单独的退火步骤和/或后续处理如氮化物或氮氧化物层的沉积)的氧化物层,所述氮前驱体包括氧化一氮(NO)和/或一氧化二氮(N2O),和/或作为处理步骤的一部分所形成或后续退火的氧化物层,其中反应性氮物质是一种副产品,从而使氮引入到所述层中。
参见图1A,提供了碳化硅层(方块70)。SiC层可以是外延生长层和/或基质。在碳化硅层上提供氮化的氧化物层(方块72)。如本文所述,可以通过在N2O和/或NO环境中生长和/或退火提供氮化。类似地,通过在氧化物层上沉积氮化物层的工艺步骤,例如以氧化物-氮化物(ON)或氧化物-氮化物-氧化物(ONO)结构,可以提供氧化物层的氮化。ONO和ON描述在共同转让的美国专利6,246,076中,其公开内容并入本文作为参考,如同在本文中完全阐述一样。对于其中通过退火提供氮化的氧化物层的实施方案,氧化物层可以通过沉积形成,例如低压化学气相沉积(LPCVD)、通过热氧化过程的热生长和/或使用其它技术形成。优选地,氧化物层利用湿法重新氧化法形成,如在美国专利No.5,972,801中所述,其公开内容并入本文作为参考,如同在本文中完全阐述一样。
在含氢气环境中使氮化的氧化物层退火(方块74)。这样的退火可以是单独的工艺步骤,或者可以是后续沉积或其它此类过程的一部分,例如在湿环境中在氧化物层上沉积氮化物层可以提供氮化和退火。退火优选在大于约400℃且小于约1000℃的温度下进行。优选地,退火在约400℃-约800℃的温度进行。退火优选进行约2分钟或更长时间。
在含氢气环境中的退火可以在氮化后立即进行,或者在退火前可以进行中间步骤。因此,如图1B所示,可以以提供接触(contact)退火的后续工艺步骤形式提供退火。如图1B所示,氮化的氧化物层提供在SiC层上(方块80和82)。然后可以进行其它的器件制备,以提供碳化硅半导体器件(方块84)。作为器件制备的一部分,或者与器件制备分开,对器件制备接触金属化(方块86)。接触金属化然后经过在含氢气环境中的接触退火(方块88),优选在大于约400℃且小于约900℃的温度下进行。因此,接触退火提供氮化的氧化物层在含氢气环境中退火的至少一部分。后续的高温工艺步骤然后也在含氢气环境中进行(方块90)。
例如,在碳化硅金属氧化物半导体器件中,通过在小于约900℃的温度下在含氢气环境中进行接触退火,在器件金属化后可以提供退火。因此,例如,氧化物层可以提供金属氧化物半导体场效应晶体管(MOSFET)的门氧化物。接触退火可以退火器件的触点并提供氮化的氧化物的退火。在制备过程中,无论何时发生氮化的氧化物层的退火,后续的高温(即在大于约400℃的温度下处理)处理在含氢气环境中进行可能是优选的。
本文所用的术语含氢气环境是指单独的或与其它气体组合的氢气/或氢气前驱体。例如,4%氢气和96%氩气的合成气体可以用于氢气退火。类似地,氢气可以由氢气前驱体提供,如NH3和/或可以是工艺步骤的副产物。因此,本发明不应当限于纯氢气环境,而是包括氢气和/或氢气前驱体,以及与其它气体一起的组分气体。
图2是适用于提供氮化的氧化物层的本发明特定实施方案的管式炉示意图。从图2中可以看出,炉管10有许多SiC晶片12,或者在其上已经形成氧化物层如SiO2,或者将要在其上形成氧化物层。优选地,碳化硅晶片是4H-SiC。晶片12放在载体14上,使得晶片通常在炉管10内具有固定位置。载体14的定位使得晶片离炉管10进口的距离为L1+L2,并且在炉管10内延伸距离L3。注入气体16可以包含N2O和/或NO,其通过炉管10,并且按照预定的温度分布,当它们通过距离L1时被加热以提供热气体18。热气体18可以保持在按照预定温度分布确定的温度,并且通过距离L2到达第一个晶片12。热气体18继续通过炉管10直至它们通过出口以废气20的形式离开炉管10。因此,热气体18通过距离L3。对于距离L2和L3,热气体18优选保持在基本恒定的温度,但是,本领域技术人员从本公开可以理解,也可以利用各种温度分布。这样的温度分布可以包括温度随时间和/或距离而变化。但是,在通过N2O退火和/或氧化提供氮化的氧化物层的实施方案中,预定的温度分布应当包括高于约1100℃的退火温度或至少约1200℃的氧化温度。
如图2所示,热气体18在L1距离末端可以达到N2O开始分解成其组分的温度。该距离可能取决于炉管10的物理特性、预定的温度分布和流量分布。热气体18在到达晶片12之前还通过距离L2。热气体通过距离L2所需时间在本文中称为“初始停留时间”。优选地,对于初始停留时间,热气体保持与大于约1100℃的退火温度或至少约1200℃的氧化温度相对应的基本恒定的温度。但是,正如本领域技术人员将会理解的,可以利用不同的加热曲线,其可以延长或减少初始停留时间。但是,优选的是加热曲线是迅速的,使得初始停留时间与热气体在通过L3距离之前保持在大于约1100℃的退火温度或至少约1200℃的氧化温度的时间基本相同。
热气体通过距离L2+L3的总时间在本文中称为“总停留时间”。正如本领域技术人员从本公开可以理解的,这些停留时间取决于热气体18通过炉管10的速度,该速度可以根据热气体18的流量和炉管10的横截面积确定。这样的速度是平均速度,例如在获得湍流时,或者在层流系统中可以是实际速度。因此,术语速度在本文中用来指平均速度和实际速度。
如上所讨论的,除了别的方式以外,氮化的氧化物层可以通过在NO和/或N2O环境中生长和/或退火来提供。如上所述的NO生长和/或退火可以单独使用或者与N2O生长和/或退火结合使用。如果氮化的氧化物层通过在N2O环境中的生长和/或退火来提供,则优选的是这样的生长和/或退火以预定温度和预定流量进行,如本文所述。
对于N2O退火,优选使用预定的温度分布使氧化物退火,预定的温度分布包括在腔室中大于约1100℃的退火温度,其中以预定流量范围内的流量分布提供N2O。优选地,退火温度为约1175℃或更高,更优选可以使用约1200℃。N2O的流量范围可以根据使用该方法的特定设备来选择。但是,在特定实施方案中,N2O的流量范围可以低至2标准升/分钟(SLM)或高到约8SLM。在进一步的实施方案中,约3-约5SLM的流量范围可能是优选的。对于图2所示的特定炉子,低至约0.37cm/sec或高到约1.46cm/sec的气体速度或约0.55cm/s-约0.95cm/s的速度可能是合适的。特别地,对于约12英寸(约30.48cm)的L2距离和约18英寸(约45.72cm)的L3距离,这样的速度产生约11秒-约45秒的初始停留时间和约28秒-约112秒的总停留时间。在特别优选的实施方案中,初始停留时间为约16秒-约31秒,总停留时间为约41-约73秒。N2O和/或NO退火可以进行约3小时,但是,也可以利用约30分钟到约6小时的退火,尽管可以利用更长的时间。
对于N2O生长,SiC晶片12优选使用预定的温度分布氧化,预定的温度分布包括在腔室内约1200℃的氧化温度,其中以预定流量范围内的流量分布提供N2O。氧化温度优选约1300℃。N2O的流量范围可以根据使用该方法的特定设备来选择。但是,在特定实施方案中,N2O的流量范围可以低至2标准升/分钟(SLM)或高到约6SLM或更高。在进一步的实施方案中,约3.5-约4SLM的流量范围可能是优选的。因此,对于特定的设备,低至约0.37cm/sec或高到约1.11cm/sec的气体速度可以利用,而约0.65cm/s-约0.74cm/s的速度可能是优选的。特别地,对于约12英寸(约30.48cm)的L2距离和约18英寸(约45.72cm)的L3距离,这样的速度产生约11秒-约33秒的初始停留时间和约28秒-约84秒的总停留时间。在特别优选的实施方案中,初始停留时间为约19秒-约22秒,总停留时间为约49-约56秒。N2O氧化可以进行的时间取决于希望的氧化层厚度,例如,可以使用约3小时的氧化时间。本文所用的N2O是指纯N2O或N2O与其它氧化剂如水蒸气、O2和/或惰性气体的组合。
在NO和/或N2O环境中的氧化和/或在NO和/或N2O环境中的退火之后可以在惰性气体或多种气体中退火,例如氩气和/或N2或其与其它气体的组合。这样的退火可以进行约1小时,然而,还可以使用最多约3小时或更长的退火。
图3-6说明利用本发明的实施方案可以获得的结果。图3说明没有在含有氢气环境中后续退火的N2O生长和N2O退火获得的结果。图4A、4B、5和6说明用氮化的氧化物层的氢气退火获得的结果。
如图3所示,实线代表没有氮化的热生长氧化物。在更低的温度(1100℃)下,把存在的氧化物暴露于N2O增大界面态密度,如通过把代表热氧化物的粗实线与暴露于1100℃N2O退火的相同热氧化物的数据比较所表明的。在1200℃,用N2O退火明显改善热氧化物。在湿环境中处理的热氧化物可以进一步通过1200℃N2O退火改善,如通过把实心圆与空心圆数据相比所看出的。使用1300℃的N2O退火过程(DRY-1300线)和1300℃的N2O生长过程(1300生长线)获得进一步改善的结果。在该温度下,SiC的氧化是明显的。所以,除了在N2O中使存在的氧化物退火以外,一些氧化物在N2O环境中长大(在3小时内长大500埃)。在N2O内使氧化物长大,通过省去氧化步骤,可以在使存在的氧化物在N2O中退火期间节约约9小时的处理时间。正如通过比较Dry-1300线与1300生长线在图3中所看出的,不论氧化物在N2O处理之前长大,还是在N2O中长大,都获得基本相同的结果。
图4A和4B是在4%氢气和96%惰性气体的合成气体中在800℃退火前后测量的,已经在1300℃进行N2O退火的氧化物的界面态密度图。如图4A所示,线180表示在退火前氧化物的界面阱(trap)密度,线182表示退火后的。在图4B中,线184表示在退火前氧化物的界面阱密度,线186表示退火后的。线180和184可以表示在4H-SiC MOS截面上DIT的最低报告值。在合成气体中存在4%氢气在带隙的上半部(图4B)和下半部(图4A)上进一步改善该结果。
图5是在4%氢气和96%惰性气体的合成气体中在800℃退火前后测量的,包含已经在1300℃进行N2O退火的氧化物的电容器的电容与电压关系图。在图5中,线190表示退火前氧化物的电容,线192表示退火后的。如图5所示,合成气体退火使平带电压降低4.5伏,其相当于有效氧化物电荷减少1.7E12cm-2。
图6是在4%氢气和96%惰性气体的合成气体中在800℃退火前后测量的,包含已经在1300℃进行N2O退火的门氧化物的MOSFETs的场效应迁移率与门电压的关系图。在图6中,线200表示在退火前具有氮化的门氧化物的MOSFETs的场效应迁移率,线202表示退火后的。如图6所示,倒转沟道(inversion channel)迁移率增加几乎为20%,阈电压降低2V。
在附图和说明书中,已经公开了本发明的典型优选实施方案,尽管使用专门术语,但是它们仅以一般性的描述意义使用并且不用于限制目的,本发明的范围在所附权利要求中阐述。
Claims (20)
1.一种在碳化硅电子器件中形成绝缘体的方法,包括:
在一层碳化硅上制备氮化的氧化物层;和
在含氢气的环境中退火该氮化的氧化物层。
2.根据权利要求1的方法,其中碳化硅层包含4H多型体碳化硅。
3.根据权利要求1的方法,其中碳化硅层包含在非碳化硅基质上的碳化硅层。
4.根据权利要求1的方法,其中,碳化硅层包含一部分碳化硅基质。
5.权利要求1的方法,其中,制备氮化的氧化物层的步骤包括以下至少之一:在氧化一氮和一氧化二氮至少之一中形成氧化物层和在氧化一氮和一氧化二氮至少之一中退火存在的氧化物层。
6.权利要求1的方法,其中制备氮化的氧化物层的步骤包括以下步骤:
制备氧化物层;和
在氧化物层上制备氮化物层,以便氮化在其上形成氮化物层的氧化物层。
7.权利要求6的方法,其中,在含氢气环境中退火氧化物层的步骤基本与制备氮化物层的步骤同时提供,使得在氧化物层上制备氮化物层的步骤包括在氧化物层上制备氮化物层,以便氮化和氢化在其上形成氮化物层的氧化物层。
8.权利要求1的方法,其中退火氧化物层的步骤包括作为另一个工艺步骤的一部分把氧化物层在含氢气环境中加热到大于约400℃的温度。
9.权利要求1的方法,其中退火氧化物层的步骤包括在含氢气环境中在大于约400℃的温度退火氧化物层。
10.权利要求1的方法,其中退火氧化物层的步骤包括在含氢气环境中在小于约900℃的温度退火氧化物层。
11.权利要求1的方法,其中退火氧化物层的步骤包括在含氢气环境中在约400℃-约1000℃的温度退火氧化物层。
12.权利要求1的方法,其中退火氧化物层的步骤包括在含氢气环境中在约400℃-约800℃的温度退火氧化物层。
13.权利要求1的方法,其还包括在含氢气环境中进行后续高温处理步骤的步骤。
14.权利要求1的方法,其中在退火步骤后进行形成与氧化层相关的半导体器件的金属化的步骤。
15.权利要求14的方法,其中退火氧化物层的步骤包括在含氢气环境中在低于约900℃的温度退火氧化物层。
16.权利要求15的方法,其中退火氧化物层的步骤包括接触退火。
17.权利要求1的方法,其中退火步骤包括在含有约4%氢气和96%惰性气体的合成气体中退火氧化物层。
18.权利要求1的方法,其还包含形成具有氧化物层作为金属氧化物半导体器件的门氧化物的碳化硅金属氧化物半导体器件。
19.权利要求1的方法,其中退火氧化物层的步骤进行至少约2分钟。
20.一种在碳化硅层上制备氧化物层的方法,包括:
用氧化一氮和一氧化二氮至少之一氮化在碳化硅层上的氧化物层;和
在含氢气环境中在约400℃-约900℃的温度使氮化的氧化物层退火至少约2分钟。
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/834,283 US6610366B2 (en) | 2000-10-03 | 2001-04-12 | Method of N2O annealing an oxide layer on a silicon carbide layer |
US09/834,283 | 2001-04-12 | ||
US29430701P | 2001-05-30 | 2001-05-30 | |
US60/294,307 | 2001-05-30 | ||
US10/045,542 US7067176B2 (en) | 2000-10-03 | 2001-10-26 | Method of fabricating an oxide layer on a silicon carbide layer utilizing an anneal in a hydrogen environment |
US10/045,542 | 2001-10-26 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1531746A true CN1531746A (zh) | 2004-09-22 |
CN100517607C CN100517607C (zh) | 2009-07-22 |
Family
ID=27366709
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB028081072A Expired - Lifetime CN100517607C (zh) | 2001-04-12 | 2002-04-12 | 利用在氢气环境中退火在碳化硅层上制备氧化物层的方法 |
Country Status (9)
Country | Link |
---|---|
US (1) | US7067176B2 (zh) |
EP (3) | EP1378006B1 (zh) |
JP (1) | JP4781610B2 (zh) |
KR (1) | KR100855388B1 (zh) |
CN (1) | CN100517607C (zh) |
AT (1) | ATE407449T1 (zh) |
CA (1) | CA2442929C (zh) |
DE (1) | DE60228695D1 (zh) |
WO (1) | WO2002084727A2 (zh) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102810465A (zh) * | 2011-06-02 | 2012-12-05 | 中国科学院微电子研究所 | 一种在SiC材料上生长SiO2钝化层的方法 |
CN103165432A (zh) * | 2013-03-15 | 2013-06-19 | 上海华力微电子有限公司 | 一种栅氧化层的制备方法 |
CN104658903A (zh) * | 2015-01-30 | 2015-05-27 | 株洲南车时代电气股份有限公司 | 一种制备SiC MOSFET栅氧化层的方法 |
CN105428400A (zh) * | 2014-09-12 | 2016-03-23 | 株式会社思可林集团 | 半导体制造方法以及半导体制造装置 |
CN106449392A (zh) * | 2016-11-29 | 2017-02-22 | 东莞市广信知识产权服务有限公司 | 一种SiC表面钝化方法 |
CN115295407A (zh) * | 2022-09-29 | 2022-11-04 | 浙江大学杭州国际科创中心 | 一种SiC功率器件的栅氧结构制备方法和栅氧结构 |
Families Citing this family (54)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6956238B2 (en) * | 2000-10-03 | 2005-10-18 | Cree, Inc. | Silicon carbide power metal-oxide semiconductor field effect transistors having a shorting channel and methods of fabricating silicon carbide metal-oxide semiconductor field effect transistors having a shorting channel |
US7022378B2 (en) * | 2002-08-30 | 2006-04-04 | Cree, Inc. | Nitrogen passivation of interface states in SiO2/SiC structures |
US7141483B2 (en) * | 2002-09-19 | 2006-11-28 | Applied Materials, Inc. | Nitrous oxide anneal of TEOS/ozone CVD for improved gapfill |
US7431967B2 (en) * | 2002-09-19 | 2008-10-07 | Applied Materials, Inc. | Limited thermal budget formation of PMD layers |
US7221010B2 (en) * | 2002-12-20 | 2007-05-22 | Cree, Inc. | Vertical JFET limited silicon carbide power metal-oxide semiconductor field effect transistors |
US6979863B2 (en) * | 2003-04-24 | 2005-12-27 | Cree, Inc. | Silicon carbide MOSFETs with integrated antiparallel junction barrier Schottky free wheeling diodes and methods of fabricating the same |
US7074643B2 (en) * | 2003-04-24 | 2006-07-11 | Cree, Inc. | Silicon carbide power devices with self-aligned source and well regions and methods of fabricating same |
US7709403B2 (en) * | 2003-10-09 | 2010-05-04 | Panasonic Corporation | Silicon carbide-oxide layered structure, production method thereof, and semiconductor device |
US7528051B2 (en) * | 2004-05-14 | 2009-05-05 | Applied Materials, Inc. | Method of inducing stresses in the channel region of a transistor |
US7118970B2 (en) * | 2004-06-22 | 2006-10-10 | Cree, Inc. | Methods of fabricating silicon carbide devices with hybrid well regions |
US7682988B2 (en) * | 2004-08-31 | 2010-03-23 | Texas Instruments Incorporated | Thermal treatment of nitrided oxide to improve negative bias thermal instability |
US7391057B2 (en) * | 2005-05-18 | 2008-06-24 | Cree, Inc. | High voltage silicon carbide devices having bi-directional blocking capabilities |
US7414268B2 (en) | 2005-05-18 | 2008-08-19 | Cree, Inc. | High voltage silicon carbide MOS-bipolar devices having bi-directional blocking capabilities |
US7615801B2 (en) * | 2005-05-18 | 2009-11-10 | Cree, Inc. | High voltage silicon carbide devices having bi-directional blocking capabilities |
US20060261346A1 (en) * | 2005-05-18 | 2006-11-23 | Sei-Hyung Ryu | High voltage silicon carbide devices having bi-directional blocking capabilities and methods of fabricating the same |
US7528040B2 (en) | 2005-05-24 | 2009-05-05 | Cree, Inc. | Methods of fabricating silicon carbide devices having smooth channels |
JP5033316B2 (ja) * | 2005-07-05 | 2012-09-26 | 日産自動車株式会社 | 半導体装置の製造方法 |
JP2007096263A (ja) * | 2005-08-31 | 2007-04-12 | Denso Corp | 炭化珪素半導体装置およびその製造方法。 |
US7727904B2 (en) | 2005-09-16 | 2010-06-01 | Cree, Inc. | Methods of forming SiC MOSFETs with high inversion layer mobility |
KR100790237B1 (ko) * | 2005-12-29 | 2008-01-02 | 매그나칩 반도체 유한회사 | 이미지 센서의 금속배선 형성방법 |
US8432012B2 (en) | 2006-08-01 | 2013-04-30 | Cree, Inc. | Semiconductor devices including schottky diodes having overlapping doped regions and methods of fabricating same |
US7728402B2 (en) | 2006-08-01 | 2010-06-01 | Cree, Inc. | Semiconductor devices including schottky diodes with controlled breakdown |
EP2052414B1 (en) | 2006-08-17 | 2016-03-30 | Cree, Inc. | High power insulated gate bipolar transistors |
JP2010502031A (ja) * | 2006-09-01 | 2010-01-21 | エヌエックスピー ビー ヴィ | 炭化ケイ素mosfetの反転層移動度を改善する方法 |
US8835987B2 (en) | 2007-02-27 | 2014-09-16 | Cree, Inc. | Insulated gate bipolar transistors including current suppressing layers |
JP2008244455A (ja) * | 2007-02-28 | 2008-10-09 | Denso Corp | 炭化珪素半導体装置およびその製造方法 |
TWI335674B (en) * | 2007-07-11 | 2011-01-01 | Univ Nat Taiwan | Methos for forming an insulating layer over a silicon carbide substrate, silicon carbide transistors and methods for fabricating the same |
JP5157843B2 (ja) * | 2007-12-04 | 2013-03-06 | 住友電気工業株式会社 | 炭化ケイ素半導体装置およびその製造方法 |
US8232558B2 (en) | 2008-05-21 | 2012-07-31 | Cree, Inc. | Junction barrier Schottky diodes with current surge capability |
US8217398B2 (en) * | 2008-10-15 | 2012-07-10 | General Electric Company | Method for the formation of a gate oxide on a SiC substrate and SiC substrates and devices prepared thereby |
WO2010103820A1 (ja) * | 2009-03-11 | 2010-09-16 | 三菱電機株式会社 | 炭化珪素半導体装置の製造方法 |
US8288220B2 (en) | 2009-03-27 | 2012-10-16 | Cree, Inc. | Methods of forming semiconductor devices including epitaxial layers and related structures |
US8294507B2 (en) | 2009-05-08 | 2012-10-23 | Cree, Inc. | Wide bandgap bipolar turn-off thyristor having non-negative temperature coefficient and related control circuits |
US8629509B2 (en) | 2009-06-02 | 2014-01-14 | Cree, Inc. | High voltage insulated gate bipolar transistors with minority carrier diverter |
US8193848B2 (en) | 2009-06-02 | 2012-06-05 | Cree, Inc. | Power switching devices having controllable surge current capabilities |
US8541787B2 (en) | 2009-07-15 | 2013-09-24 | Cree, Inc. | High breakdown voltage wide band-gap MOS-gated bipolar junction transistors with avalanche capability |
US8354690B2 (en) | 2009-08-31 | 2013-01-15 | Cree, Inc. | Solid-state pinch off thyristor circuits |
US9117739B2 (en) | 2010-03-08 | 2015-08-25 | Cree, Inc. | Semiconductor devices with heterojunction barrier regions and methods of fabricating same |
US8415671B2 (en) | 2010-04-16 | 2013-04-09 | Cree, Inc. | Wide band-gap MOSFETs having a heterojunction under gate trenches thereof and related methods of forming such devices |
JP2012004270A (ja) * | 2010-06-16 | 2012-01-05 | Sumitomo Electric Ind Ltd | 炭化珪素半導体の洗浄方法、炭化珪素半導体および炭化珪素半導体装置 |
JP2012064873A (ja) * | 2010-09-17 | 2012-03-29 | Rohm Co Ltd | 半導体装置およびその製造方法 |
US9142662B2 (en) | 2011-05-06 | 2015-09-22 | Cree, Inc. | Field effect transistor devices with low source resistance |
US9029945B2 (en) | 2011-05-06 | 2015-05-12 | Cree, Inc. | Field effect transistor devices with low source resistance |
US9984894B2 (en) | 2011-08-03 | 2018-05-29 | Cree, Inc. | Forming SiC MOSFETs with high channel mobility by treating the oxide interface with cesium ions |
US8618582B2 (en) | 2011-09-11 | 2013-12-31 | Cree, Inc. | Edge termination structure employing recesses for edge termination elements |
US8664665B2 (en) | 2011-09-11 | 2014-03-04 | Cree, Inc. | Schottky diode employing recesses for elements of junction barrier array |
US9640617B2 (en) | 2011-09-11 | 2017-05-02 | Cree, Inc. | High performance power module |
US9373617B2 (en) | 2011-09-11 | 2016-06-21 | Cree, Inc. | High current, low switching loss SiC power module |
CN103918079B (zh) | 2011-09-11 | 2017-10-31 | 科锐 | 包括具有改进布局的晶体管的高电流密度功率模块 |
US8680587B2 (en) | 2011-09-11 | 2014-03-25 | Cree, Inc. | Schottky diode |
US9546420B1 (en) * | 2012-10-08 | 2017-01-17 | Sandia Corporation | Methods of depositing an alpha-silicon-carbide-containing film at low temperature |
US9018108B2 (en) | 2013-01-25 | 2015-04-28 | Applied Materials, Inc. | Low shrinkage dielectric films |
DE102016112877B4 (de) | 2015-09-07 | 2021-07-15 | Fuji Electric Co., Ltd. | Verfahren zum Herstellen einer Halbleitervorrichtung und für das Verfahren verwendete Halbleiterherstellungsvorrichtung |
DE102018107966B4 (de) | 2018-04-04 | 2022-02-17 | Infineon Technologies Ag | Verfahren zum Bilden eines Breiter-Bandabstand-Halbleiter-Bauelements |
Family Cites Families (74)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3924024A (en) | 1973-04-02 | 1975-12-02 | Ncr Co | Process for fabricating MNOS non-volatile memories |
CA1075437A (en) * | 1975-07-28 | 1980-04-15 | Malcolm E. Washburn | Porous silicon oxynitride refractory shapes |
US4466172A (en) | 1979-01-08 | 1984-08-21 | American Microsystems, Inc. | Method for fabricating MOS device with self-aligned contacts |
US4875083A (en) | 1987-10-26 | 1989-10-17 | North Carolina State University | Metal-insulator-semiconductor capacitor formed on silicon carbide |
US5030600A (en) * | 1988-10-06 | 1991-07-09 | Benchmark Structural Ceramics Corp. | Novel sialon composition |
JPH0766971B2 (ja) | 1989-06-07 | 1995-07-19 | シャープ株式会社 | 炭化珪素半導体装置 |
JPH03157974A (ja) | 1989-11-15 | 1991-07-05 | Nec Corp | 縦型電界効果トランジスタ |
JPH0718056B2 (ja) * | 1990-04-27 | 1995-03-01 | 株式会社コロイドリサーチ | 酸窒化物セラミックスファイバーの製造方法 |
JP2542448B2 (ja) | 1990-05-24 | 1996-10-09 | シャープ株式会社 | 電界効果トランジスタおよびその製造方法 |
US5170455A (en) | 1991-10-30 | 1992-12-08 | At&T Bell Laboratories | Optical connective device |
US6344663B1 (en) | 1992-06-05 | 2002-02-05 | Cree, Inc. | Silicon carbide CMOS devices |
US5459107A (en) | 1992-06-05 | 1995-10-17 | Cree Research, Inc. | Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures |
US5726463A (en) | 1992-08-07 | 1998-03-10 | General Electric Company | Silicon carbide MOSFET having self-aligned gate structure |
US5587870A (en) | 1992-09-17 | 1996-12-24 | Research Foundation Of State University Of New York | Nanocrystalline layer thin film capacitors |
US5506421A (en) | 1992-11-24 | 1996-04-09 | Cree Research, Inc. | Power MOSFET in silicon carbide |
KR100305123B1 (ko) | 1992-12-11 | 2001-11-22 | 비센트 비.인그라시아, 알크 엠 아헨 | 정적랜덤액세스메모리셀및이를포함하는반도체장치 |
JP2531572B2 (ja) * | 1993-08-09 | 1996-09-04 | 東芝セラミックス株式会社 | 石英ガラスの酸窒化方法および表面処理方法 |
US5479316A (en) | 1993-08-24 | 1995-12-26 | Analog Devices, Inc. | Integrated circuit metal-oxide-metal capacitor and method of making same |
US5510630A (en) | 1993-10-18 | 1996-04-23 | Westinghouse Electric Corporation | Non-volatile random access memory cell constructed of silicon carbide |
JP3521246B2 (ja) | 1995-03-27 | 2004-04-19 | 沖電気工業株式会社 | 電界効果トランジスタおよびその製造方法 |
JPH11261061A (ja) | 1998-03-11 | 1999-09-24 | Denso Corp | 炭化珪素半導体装置及びその製造方法 |
JP4001960B2 (ja) | 1995-11-03 | 2007-10-31 | フリースケール セミコンダクター インコーポレイテッド | 窒化酸化物誘電体層を有する半導体素子の製造方法 |
US5972801A (en) | 1995-11-08 | 1999-10-26 | Cree Research, Inc. | Process for reducing defects in oxide layers on silicon carbide |
US6136728A (en) | 1996-01-05 | 2000-10-24 | Yale University | Water vapor annealing process |
JPH09205202A (ja) | 1996-01-26 | 1997-08-05 | Matsushita Electric Works Ltd | 半導体装置 |
US5877045A (en) | 1996-04-10 | 1999-03-02 | Lsi Logic Corporation | Method of forming a planar surface during multi-layer interconnect formation by a laser-assisted dielectric deposition |
US5763905A (en) | 1996-07-09 | 1998-06-09 | Abb Research Ltd. | Semiconductor device having a passivation layer |
US6002159A (en) | 1996-07-16 | 1999-12-14 | Abb Research Ltd. | SiC semiconductor device comprising a pn junction with a voltage absorbing edge |
US5939763A (en) | 1996-09-05 | 1999-08-17 | Advanced Micro Devices, Inc. | Ultrathin oxynitride structure and process for VLSI applications |
US6091077A (en) * | 1996-10-22 | 2000-07-18 | Matsushita Electric Industrial Co., Ltd. | MIS SOI semiconductor device with RTD and/or HET |
US6028012A (en) * | 1996-12-04 | 2000-02-22 | Yale University | Process for forming a gate-quality insulating layer on a silicon carbide substrate |
US5837572A (en) | 1997-01-10 | 1998-11-17 | Advanced Micro Devices, Inc. | CMOS integrated circuit formed by using removable spacers to produce asymmetrical NMOS junctions before asymmetrical PMOS junctions for optimizing thermal diffusivity of dopants implanted therein |
JP3206727B2 (ja) | 1997-02-20 | 2001-09-10 | 富士電機株式会社 | 炭化けい素縦型mosfetおよびその製造方法 |
DE19809554B4 (de) | 1997-03-05 | 2008-04-03 | Denso Corp., Kariya | Siliziumkarbidhalbleitervorrichtung |
US6063698A (en) | 1997-06-30 | 2000-05-16 | Motorola, Inc. | Method for manufacturing a high dielectric constant gate oxide for use in semiconductor integrated circuits |
JP3180895B2 (ja) | 1997-08-18 | 2001-06-25 | 富士電機株式会社 | 炭化けい素半導体装置の製造方法 |
EP1010204A1 (de) | 1997-08-20 | 2000-06-21 | Siemens Aktiengesellschaft | Halbleiterstruktur mit einem alpha-siliziumcarbidbereich sowie verwendung dieser halbleiterstruktur |
US6239463B1 (en) | 1997-08-28 | 2001-05-29 | Siliconix Incorporated | Low resistance power MOSFET or other device containing silicon-germanium layer |
SE9704150D0 (sv) | 1997-11-13 | 1997-11-13 | Abb Research Ltd | Semiconductor device of SiC with insulating layer a refractory metal nitride layer |
JPH11191559A (ja) | 1997-12-26 | 1999-07-13 | Matsushita Electric Works Ltd | Mosfetの製造方法 |
JPH11251592A (ja) | 1998-01-05 | 1999-09-07 | Denso Corp | 炭化珪素半導体装置 |
JP3216804B2 (ja) | 1998-01-06 | 2001-10-09 | 富士電機株式会社 | 炭化けい素縦形fetの製造方法および炭化けい素縦形fet |
JPH11266017A (ja) | 1998-01-14 | 1999-09-28 | Denso Corp | 炭化珪素半導体装置及びその製造方法 |
JPH11238742A (ja) | 1998-02-23 | 1999-08-31 | Denso Corp | 炭化珪素半導体装置の製造方法 |
JP3893725B2 (ja) | 1998-03-25 | 2007-03-14 | 株式会社デンソー | 炭化珪素半導体装置の製造方法 |
US6627539B1 (en) | 1998-05-29 | 2003-09-30 | Newport Fab, Llc | Method of forming dual-damascene interconnect structures employing low-k dielectric materials |
US6107142A (en) | 1998-06-08 | 2000-08-22 | Cree Research, Inc. | Self-aligned methods of fabricating silicon carbide power devices by implantation and lateral diffusion |
US6100169A (en) | 1998-06-08 | 2000-08-08 | Cree, Inc. | Methods of fabricating silicon carbide power devices by controlled annealing |
JP4123636B2 (ja) | 1998-06-22 | 2008-07-23 | 株式会社デンソー | 炭化珪素半導体装置及びその製造方法 |
US5960289A (en) | 1998-06-22 | 1999-09-28 | Motorola, Inc. | Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region |
US6221700B1 (en) | 1998-07-31 | 2001-04-24 | Denso Corporation | Method of manufacturing silicon carbide semiconductor device with high activation rate of impurities |
JP3959856B2 (ja) | 1998-07-31 | 2007-08-15 | 株式会社デンソー | 炭化珪素半導体装置及びその製造方法 |
JP2000106371A (ja) | 1998-07-31 | 2000-04-11 | Denso Corp | 炭化珪素半導体装置の製造方法 |
US6246076B1 (en) | 1998-08-28 | 2001-06-12 | Cree, Inc. | Layered dielectric on silicon carbide semiconductor structures |
JP2000133633A (ja) | 1998-09-09 | 2000-05-12 | Texas Instr Inc <Ti> | ハ―ドマスクおよびプラズマ活性化エッチャントを使用した材料のエッチング方法 |
US6204203B1 (en) | 1998-10-14 | 2001-03-20 | Applied Materials, Inc. | Post deposition treatment of dielectric films for interface control |
US6048766A (en) | 1998-10-14 | 2000-04-11 | Advanced Micro Devices | Flash memory device having high permittivity stacked dielectric and fabrication thereof |
JP2000201050A (ja) * | 1998-11-02 | 2000-07-18 | Ngk Insulators Ltd | 表面弾性波装置用基板およびその製造方法 |
US6190973B1 (en) | 1998-12-18 | 2001-02-20 | Zilog Inc. | Method of fabricating a high quality thin oxide |
US6228720B1 (en) | 1999-02-23 | 2001-05-08 | Matsushita Electric Industrial Co., Ltd. | Method for making insulated-gate semiconductor element |
JP3443589B2 (ja) | 1999-03-01 | 2003-09-02 | 独立行政法人産業技術総合研究所 | 半導体装置の製造方法 |
US6261976B1 (en) * | 1999-03-18 | 2001-07-17 | Chartered Semiconductor Manufacturing Ltd. | Method of forming low pressure silicon oxynitride dielectrics having high reliability |
US6238967B1 (en) | 1999-04-12 | 2001-05-29 | Motorola, Inc. | Method of forming embedded DRAM structure |
JP2000349081A (ja) | 1999-06-07 | 2000-12-15 | Sony Corp | 酸化膜形成方法 |
JP4192353B2 (ja) | 1999-09-21 | 2008-12-10 | 株式会社デンソー | 炭化珪素半導体装置及びその製造方法 |
US6524877B1 (en) * | 1999-10-26 | 2003-02-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, and method of fabricating the same |
DE10036208B4 (de) | 2000-07-25 | 2007-04-19 | Siced Electronics Development Gmbh & Co. Kg | Halbleiteraufbau mit vergrabenem Inselgebiet und Konaktgebiet |
WO2002029874A2 (en) * | 2000-10-03 | 2002-04-11 | Cree, Inc. | Method of fabricating an oxide layer on a silicon carbide layer utilizing n2o |
US6767843B2 (en) * | 2000-10-03 | 2004-07-27 | Cree, Inc. | Method of N2O growth of an oxide layer on a silicon carbide layer |
US6593620B1 (en) | 2000-10-06 | 2003-07-15 | General Semiconductor, Inc. | Trench DMOS transistor with embedded trench schottky rectifier |
US6600138B2 (en) * | 2001-04-17 | 2003-07-29 | Mattson Technology, Inc. | Rapid thermal processing system for integrated circuits |
US6707011B2 (en) * | 2001-04-17 | 2004-03-16 | Mattson Technology, Inc. | Rapid thermal processing system for integrated circuits |
US6632747B2 (en) * | 2001-06-20 | 2003-10-14 | Texas Instruments Incorporated | Method of ammonia annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile |
US7022378B2 (en) * | 2002-08-30 | 2006-04-04 | Cree, Inc. | Nitrogen passivation of interface states in SiO2/SiC structures |
-
2001
- 2001-10-26 US US10/045,542 patent/US7067176B2/en not_active Expired - Lifetime
-
2002
- 2002-04-12 KR KR1020037013333A patent/KR100855388B1/ko active IP Right Grant
- 2002-04-12 CA CA2442929A patent/CA2442929C/en not_active Expired - Lifetime
- 2002-04-12 EP EP02733980A patent/EP1378006B1/en not_active Expired - Lifetime
- 2002-04-12 CN CNB028081072A patent/CN100517607C/zh not_active Expired - Lifetime
- 2002-04-12 WO PCT/US2002/011691 patent/WO2002084727A2/en active Application Filing
- 2002-04-12 AT AT02733980T patent/ATE407449T1/de not_active IP Right Cessation
- 2002-04-12 DE DE60228695T patent/DE60228695D1/de not_active Expired - Lifetime
- 2002-04-12 EP EP08159857A patent/EP1968119B1/en not_active Expired - Lifetime
- 2002-04-12 JP JP2002581576A patent/JP4781610B2/ja not_active Expired - Lifetime
- 2002-04-12 EP EP10179447A patent/EP2259288B1/en not_active Expired - Lifetime
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102810465A (zh) * | 2011-06-02 | 2012-12-05 | 中国科学院微电子研究所 | 一种在SiC材料上生长SiO2钝化层的方法 |
CN102810465B (zh) * | 2011-06-02 | 2015-09-30 | 中国科学院微电子研究所 | 一种在SiC材料上生长SiO2钝化层的方法 |
CN103165432A (zh) * | 2013-03-15 | 2013-06-19 | 上海华力微电子有限公司 | 一种栅氧化层的制备方法 |
CN103165432B (zh) * | 2013-03-15 | 2016-08-03 | 上海华力微电子有限公司 | 一种栅氧化层的制备方法 |
CN105428400A (zh) * | 2014-09-12 | 2016-03-23 | 株式会社思可林集团 | 半导体制造方法以及半导体制造装置 |
US10028336B2 (en) | 2014-09-12 | 2018-07-17 | SCREEN Holdings Co., Ltd. | Semiconductor manufacturing method and semiconductor manufacturing apparatus |
CN105428400B (zh) * | 2014-09-12 | 2019-01-18 | 株式会社思可林集团 | 半导体制造方法 |
CN104658903A (zh) * | 2015-01-30 | 2015-05-27 | 株洲南车时代电气股份有限公司 | 一种制备SiC MOSFET栅氧化层的方法 |
CN106449392A (zh) * | 2016-11-29 | 2017-02-22 | 东莞市广信知识产权服务有限公司 | 一种SiC表面钝化方法 |
CN115295407A (zh) * | 2022-09-29 | 2022-11-04 | 浙江大学杭州国际科创中心 | 一种SiC功率器件的栅氧结构制备方法和栅氧结构 |
Also Published As
Publication number | Publication date |
---|---|
ATE407449T1 (de) | 2008-09-15 |
EP1968119A3 (en) | 2008-10-22 |
JP4781610B2 (ja) | 2011-09-28 |
EP2259288A2 (en) | 2010-12-08 |
KR100855388B1 (ko) | 2008-09-04 |
EP1378006B1 (en) | 2008-09-03 |
EP1378006A2 (en) | 2004-01-07 |
DE60228695D1 (de) | 2008-10-16 |
US20020102358A1 (en) | 2002-08-01 |
CA2442929C (en) | 2012-06-26 |
CN100517607C (zh) | 2009-07-22 |
EP2259288A3 (en) | 2011-01-05 |
WO2002084727A2 (en) | 2002-10-24 |
WO2002084727A3 (en) | 2003-04-10 |
JP2004532522A (ja) | 2004-10-21 |
EP2259288B1 (en) | 2012-12-05 |
KR20040002908A (ko) | 2004-01-07 |
CA2442929A1 (en) | 2002-10-24 |
EP1968119A2 (en) | 2008-09-10 |
EP1968119B1 (en) | 2011-11-23 |
US7067176B2 (en) | 2006-06-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN100517607C (zh) | 利用在氢气环境中退火在碳化硅层上制备氧化物层的方法 | |
US6767843B2 (en) | Method of N2O growth of an oxide layer on a silicon carbide layer | |
US6610366B2 (en) | Method of N2O annealing an oxide layer on a silicon carbide layer | |
CA2421003C (en) | Method of fabricating an oxide layer on a silicon carbide layer utilizing n2o | |
CN101283439B (zh) | 形成具有高反型层迁移性的碳化硅mosfets的方法 | |
EP2740148B1 (en) | Forming sic mosfets with high channel mobility by treating the oxide interface with cesium ions | |
Chung et al. | Effects of anneals in ammonia on the interface trap density near the band edges in 4H–silicon carbide metal-oxide-semiconductor capacitors | |
KR20050035285A (ko) | 실리콘 이산화막/실리콘 카바이드 구조에 있어서 인터페이스 스테이트의 질소 패시베이션 | |
EP1576672A2 (en) | Silicon carbide power mos field effect transistors and manufacturing methods | |
US8119539B2 (en) | Methods of fabricating oxide layers on silicon carbide layers utilizing atomic oxygen | |
US20060108589A1 (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CX01 | Expiry of patent term | ||
CX01 | Expiry of patent term |
Granted publication date: 20090722 |