CN1474447A - 半导体组件中电容器的制备方法 - Google Patents
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- 239000003990 capacitor Substances 0.000 title claims abstract description 32
- 238000003860 storage Methods 0.000 claims abstract description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 6
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Abstract
本发明提供一种半导体组件中电容器的制备方法,其包括下列步骤:于半导体晶片上形成储存节点电极;于储存节点电极之上形成以环形氮化硅所制成的介电层;以及于此介电层上形成上部电极;减少介电层的厚度Teff且通过使用Si3N4或SiOxNy(其中x在0.1与0.9之间,y在0.1与2之间)为介电层而改进漏泄电流特性;作为介电层具有高抗氧化性和高介电比。
Description
技术领域
本发明涉及一种半导体组件中电容器的制备方法,特别是有关一种使用一种环形Si3N4(或SiOxNy)来制备半导体组件中电容器的方法。
背景技术
如图1所示,本领域常规的N/O(Si3N4/SiO2)电容器如图1所示,夹层绝缘层被沉积于晶片上(未图示),其中,有一些元件被形成,而夹层绝缘层的选择性布局图样被刻划以形成可暴露出半导体晶片部分的接触孔(未图示)。
接着,在接触孔(contact hole)(未图示)中形成接触插头13,且在所形成的整个构造上面形成圆柱形、凹陷形、或其它形状的储存节点15,而在储存节点15上的氧化物层通过使用HF溶液去除(预清洗程序)。
其次,Si3N4薄层17通过实施LPCVD方法(ONO第二方法),和氧化方法(ONO第三方法)以此形成上部电极19,如此完成电容器的制造。
然而,由于设计规则的减少导致晶胞(Cell)面积降低的缘故,降低介电层(dielectric)的厚度(Teff)以获得必要的充电量是必需的。
至于常规的N/O介电层,由于LPCVD方法Si3N4的抗氧化性在厚度低于40时会严重地降低,故发生了位于电容器下方的半导体元件,例如储存节点与位线(bit-line)在第三ONO方法时被氧化的问题,而且,很难使介电层的厚度Teff低于45,因为在厚度低于50时,漏泄电流增加而击穿电压减少。
发明内容
因此,本发明是为解决发生在本领域中的上述问题,本发明的目的是提供一种半导体组件中电容器的制备方法,其可减少介电层的厚度Teff且通过使用Si3N4或SiOxNy(其中x在0.1与0.9之间,y在0.1与2之间)为介电层而改进漏泄电流特性。
为了达成上述的目的,本发明提供了一种半导体组件中电容器的制备方法,其包括下列步骤:在半导体晶片上形成储存节点电极;于储存节点电极的表面上形成以环形氮化硅所制成的介电层;以及于此介电层上形成上部电极。
本发明上述目的,其特征以及优点,从下列依附图所作的详细说明将更为明确。
附图说明
本发明目的,特征以及优点,从下列依附图所作的详细说明将更为明确。
图1为常规半导体组件电容器的制造方法的方法截面图;
图2是说明本发明半导体组件中电容器的制备方法的方法截面图;
图3是本发明半导体组件中电容器的制备方法中,环形Si3N4沉积系统的说明图;
具体实施方式
以下,参照附图详细说明本发明优选的实施方案。下面的说明与附图中,所用相同附图标记表示相同或相似的元件,所以省略说明书中有关相同或相似的元件重复的介绍。
如图2所示,其涉及本发明半导体组件中电容器的制备方法。夹层绝缘层21在晶片(未图示)上沉积,其中,有一些元件被形成,而夹层绝缘层的选择性布局图样被刻划以形成可暴露出半导体晶片部分的接触孔(未图示)。
接着,接触插头23形成于接触孔(未图示)中,且在整个半导体晶片的表面上形成圆柱形、凹陷形等储存节点25。
然后,由环形Si3N4或SiOxNy(其中x在0.1与0.9之间,y在0.1与2之间)制成的介电层25在储存节点电极25上沉积。在此时,储存节点电极25被沉积成具有多于二层的多层状,以将磷(P)浓度最大化,并利用MPS来增加储存节点电极的面积。也就是,储存节点电极的无定形层的形成是首先通过在原位沉积掺杂无定形硅层,其具有高浓度的掺杂剂,然后沉积具有低浓度掺杂剂的无定形硅层,这是通过改变气流量同时在反应加热炉中原位维持半导体基板进行的。
而且,例如SiH4、SiH2Cl2、SiCl4等气体,可用作硅(Si)源而用于沉积介电层,而NH3、N2等,用作氮(N)源,O2、O3、H2O等,可使用作为氧(O)源,如图3所示,在储存节点电极上的Si3N4沉积是通过周期性地供应此源气体至反应室,形成循环方法而进行的。
如上所述,虽然相同的气体源可如常规所使用的LPCVD方法来沉积Si3N4一样,通过循环方法来沉积Si3N4,然而,如图3所示,来源气体的供应会中断而以脉冲形态供应氮源气体与硅源气体至反应室中,从而导致在沉积的薄层中的组成中富含氮(N)。
此时,在使用Si3N4作为介电层的情况下,Si3N4通过包括有硅脉冲与氮气脉冲的循环而被沉积,而且,在使用SiOxNy为介电层的情况下(其中x在0.1与0.9之间,y在0.2与2之间),SiOxNy通过包括有硅脉冲与氮气脉冲与氧气脉冲的循环而被沉积。
另一方面,于沉积介电层27之前,通过在高于沉积温度或压力的条件下加入氮气脉冲,藉由氮化处理储存节点电极的表面,可改善漏泄电流与介电特性。
然后,介电Si3N4层被沉积,其表面被氧化以增加绝缘特性。
接着,实施氧化方法且沉积无定形硅层以形成上部电极29,在此沉积无定形硅的同时,在高于溶液界限实施掺杂,或者,通过增加磷(P)的加入或增加沉积压力,磷(P)的浓度得以提高。
而且,在以沉积硅层为上部电极情况下,可选择使用任何一个选自增加杂质浓度的方法,降低沉积温度的方法,以及增加杂质原料气体注入压力方法中的方法。
在使用增加杂质浓度方法的情况中,DS(Si2H6)或MS(SiH4)气体用作沉积时的基本气体,而浓度为1至5%的PH3/H2(或PH3/SiH4)气体用作杂质原料气体,该方法的压力维持在2乇以下。
在使用降低沉积温度方法的场合下,温度维持在500至570℃以在无定形状态下沉积硅。在此时,使用的气体的量是:基本气体(base gas)为800至2000ml(cc),杂质气体为150至500ml(cc)。
而且,在使用增加杂质气体的注入压力的方法中,温度维持在500至570℃以于无定形状况下沉积硅,在此时,使用的气体的量是:基本气体1000至1500ml(cc),杂质气体为500至1500ml(cc),方法的压力维持在1至2乇。
此外,上部电极的沉积方法包括两个以上的步骤;而上述的方法条件于方法的第1步骤中使用,在此时,沉积的厚度被控制在100至1000之间。
而且,在沉积上部电极与P的离子注入方法以后,沉积温度增加至500至600℃以增加沉积的速度,此时,杂质气体的量减少至300ml(cc)以下。
表1为采用常规LPCVD方法沉积Si3N4与依照本发明通过环形方法沉积得的Si3N4的测试结果表。
从表中得知,当施加相同的充电量时,依照本发明所制得的Si3N4层的击穿电压高于传统的0.35V-0.5V。
表1为采用常规LPCVD方法沉积Si3N4与依照本发明通过环形方法沉积得的Si3N4测试结果。
分类 | Si3N4层(常规) | Si3N4层(本发明) | |
BV(+) | 平均. | 3.69 | 4.24 |
最大 | 3.78 | 4.45 | |
最小 | 3.65 | 4.08 | |
BV(-) | 平均. | -4.12 | -4.47 |
最大 | -4.10 | -4.33 | |
最小 | -4.15 | -4.65 |
结果显示本发明所形成的Si3N4层的充电容量在相同的击穿电压下,高于常规情况3至6fF/cell。
如上所述,依照本发明半导体组件中电容器的制备方法,沉积了的Si3N4薄层若与CVD方法所得的Si3N4层比较时,具有富含氮(N)的组成,藉此增加了抗氧化性与介电比(dielectric ratio)。
因此,可减少介电层的厚度,由此Teff的厚度可减少至40以下,而因此产生NO电容器充电容量最大化且电容器的高度可由于其高的充电容量而降低。可容易地实施一系列方法来降低缺陷的存在机会。
而且,本发明的方法可免除购买高价的制造设备,例如在ALD方法中使用的设备,仅使用目前使用于CVD方法的设备即可。
因此,依照本发明,由于其高的充电容量与低的缺陷发生状况,可提高半导体组件特性的可靠性与恢复(refresh)特性。
本发明上述的优选实施方案仅用来说明本发明而已,对于本领域的技术人员而言,其所作的可能修正、增加或替换而未离开本发明的精神和范围时,应该在本发明的权利范围之内。
Claims (15)
1.一种半导体组件中电容器的制备方法,包括下列步骤:
在半导体晶片上形成储存节点电极;
在储存节点电极的表面上形成以环形氮化硅层所作成的介电层;以及
在介电层上形成上部电极。
2.权利要求1中的半导体组件电容器的制备方法,其中形成储存节点电极的步骤包括:首先以原位的方式形成具有高渗杂浓度的无定型硅层,然后通过改变气体流量并维持半导体基板于反应炉中,同时在原位沉积具有低渗杂浓度的无定型硅层。
3.权利要求1中的半导体组件中电容器的制备方法,其中形成介电层的环形氮化硅层是以环形Si3N4或环形SiOxNy制成,其中,x在0.1与0.9之间,y在0.2与2之间。
4.权利要求1中的半导体组件中电容器的制备方法,其中环形氮化硅层是以沉积环形Si3N4所制成,而环形Si3N4是通过包含硅脉冲与氮脉冲,使用SiH4、SiH2Cl2或SiCl4气体作为硅源,且使用NH3或N2气体作为氮源的循环方法而沉积的。
5.权利要求1中半导体组件中电容器的制备方法,其中环形氮化硅层是以环形SiOxNy,其中x在0.1与0.9之间,y在0.1与2之间,通过包括硅脉冲,氮脉冲与氧脉冲,使用SiH4、SiH2Cl2或SiCl4气体为硅源,NH3或N2气体作为氮源,与O2、O3或H2O作为氧气源的循环方法而制得。
6.权利要求1中半导体组件中电容器的制备方法,其还包括在形成介电层之前,于温度或压力大于沉积温度或压力的情况下,通过加入氮气脉冲至此循环中进行储存节点电极表面的氮化处理的步骤。
7.权利要求1中半导体组件中电容器的制备方法,其还包括在形成介电层以后氧化介电层表面的步骤。
8.权利要求1中半导体组件中电容器的制备方法,其中,上部电极是通过选自增加杂质浓度的方法,降低沉积温度的方法,以及增加杂质原料气体注入压力方法中的任一个方法来沉积硅而形成。
9.权利要求8中半导体组件中电容器的制备方法,其中,在使用增加杂质浓度的方法的情况中,DS(Si2H6)或MS(SiH4)气体用作沉积基本气体,而浓度为1至5%的PH3/H2(或PH3/SiH4)气体被用作杂质原料气体,该方法的压力被维持在2乇以下。
10.权利要求8中半导体组件中电容器的制备方法,其中,在使用降低沉积温度的方法的场合下,温度维持在500至570℃,而使用的气体的量系:基本气体为800至2000ml,杂质气体为150至500ml。
11.权利要求8中半导体组件中电容器的制备方法,其中,在使用增加杂质气体的注入压力的方法中,温度维持在500至570℃,而使用的气体的量系:基本气体1000至1500ml,杂质气体为500至1500ml,处理压力维持在1至2乇。
12.权利要求1中半导体组件中电容器的制备方法,其中在形成上部电极以后注入磷。
13.权利要求1中半导体组件中电容器的制备方法,其中,上部电极的形成通过超过2个以上的步骤而进行,而第一步骤的沉积厚度为100至1000。
14.权利要求13中半导体组件中电容器的制备方法,其中,在第2步骤以后的隋后方法的沉积温度升至550至600℃。
15.权利要求14中半导体组件中电容器的制备方法,其中,杂质气体的使用量在低于300ml以下。
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JP6854260B2 (ja) | 2018-06-20 | 2021-04-07 | 株式会社Kokusai Electric | 半導体装置の製造方法、基板処理装置、およびプログラム |
US11788190B2 (en) | 2019-07-05 | 2023-10-17 | Asm Ip Holding B.V. | Liquid vaporizer |
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GB8516537D0 (en) * | 1985-06-29 | 1985-07-31 | Standard Telephones Cables Ltd | Pulsed plasma apparatus |
JPH0236559A (ja) * | 1988-07-26 | 1990-02-06 | Nec Corp | 半導体装置及びその製造方法 |
JP2903735B2 (ja) | 1991-03-06 | 1999-06-14 | 日本電気株式会社 | 半導体装置 |
JPH06291060A (ja) * | 1993-03-30 | 1994-10-18 | Nissin Electric Co Ltd | 薄膜形成方法 |
US5478765A (en) | 1994-05-04 | 1995-12-26 | Regents Of The University Of Texas System | Method of making an ultra thin dielectric for electronic devices |
US5643819A (en) | 1995-10-30 | 1997-07-01 | Vanguard International Semiconductor Corporation | Method of fabricating fork-shaped stacked capacitors for DRAM cells |
JP3432997B2 (ja) | 1996-04-23 | 2003-08-04 | 株式会社東芝 | 半導体装置に使用する絶縁膜 |
US5876788A (en) | 1997-01-16 | 1999-03-02 | International Business Machines Corporation | High dielectric TiO2 -SiN composite films for memory applications |
TW334611B (en) | 1997-02-24 | 1998-06-21 | Mos Electronics Taiwan Inc | The processes and structure for trenched stack-capacitor (II) |
US5792693A (en) | 1997-03-07 | 1998-08-11 | Vanguard International Semiconductor Corporation | Method for producing capacitors having increased surface area for dynamic random access memory |
KR100304694B1 (ko) * | 1997-09-29 | 2001-11-02 | 윤종용 | 화학기상증착법에의한금속질화막형성방법및이를이용한반도체장치의금속컨택형성방법 |
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US6146938A (en) * | 1998-06-29 | 2000-11-14 | Kabushiki Kaisha Toshiba | Method of fabricating semiconductor device |
TW420871B (en) * | 1999-01-08 | 2001-02-01 | Taiwan Semiconductor Mfg | Process for improving the characteristics of stack capacitors |
JP2000252365A (ja) | 1999-03-02 | 2000-09-14 | Sony Corp | 半導体装置およびその製造方法 |
JP2000349175A (ja) * | 1999-06-03 | 2000-12-15 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
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US6391803B1 (en) * | 2001-06-20 | 2002-05-21 | Samsung Electronics Co., Ltd. | Method of forming silicon containing thin films by atomic layer deposition utilizing trisdimethylaminosilane |
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US6913963B2 (en) | 2005-07-05 |
JP2004072065A (ja) | 2004-03-04 |
KR20040013201A (ko) | 2004-02-14 |
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