CN1469452A - 在金属间介电层构成图形的方法 - Google Patents
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Abstract
一种在金属间介电层上构成图形的方法，包括a)在包含其上形成图形的下层电路的半导体基底上依次排放下层蚀刻阻止层、下层介电层、上层蚀刻阻止层和上层介电层，b)在上层介电层、上层蚀刻阻止层和下层介电层构成图形形成通孔，曝光下层电路上的下层蚀刻阻止层，c)用紫外线辐照通孔，d)在得到的包括通孔的半导体基底上形成光刻胶层，并在光刻胶层上构成图形，e)使用构成图形的光刻胶层作为蚀刻掩模构成图形上层介电层以形成上层介电层通孔周围的线路，和f)曝光下层线路的顶部。该方法容易除去光刻胶残余物，防止水引起的介电常数增加。
Description
1.技术领域
本发明涉及一种在金属间介电层构成图形的方法，更具体地讲，涉及一种通过在形成通孔后紫外线辐照，以完全防止在通孔内壁生成光刻胶残余物的金属间介电层构成图形方法。
2.背景技术
在许多半导体器件制造过程中，双重镶嵌法在构成图形金属电路方面的需求增大，图1例举说明了其常规方法。在该方法中，将双介电层，即上层和下层介电层，涂布在曝光的下层电路的半导体基底上，形成通过下层介电层连接上层电路和下层电路的通孔，并在介电层上形成上层电路图形后，在图形中填入金属形成产品结构。令通过上述方法获得的产品结构经历CMP(化学和机械抛光)过程，从而在半导体基底上获得所需的电路结构。
更准确地说，在半导体基底上形成下层电路1，并且在包括下层电路1的基底上依次排放下层蚀刻阻止层2，下层介电层3、上层蚀刻阻止层4和上层介电层5。将光刻胶涂布在得到的基底上，曝光形成光刻胶图形6。第一次在显影的基底上使用光刻胶图形6作为掩模依次干蚀刻上层介电层5、上层蚀刻阻止层4和下层介电层3，从而形成通孔7以曝光在下层电路1上的下层蚀刻阻止层2。为了形成顶部金属电路，然后将光致抗蚀剂8涂布在包括通孔7的基底上，曝光并显影形成光刻胶图形9。然后，使用光刻胶图形9作为掩模蚀刻上层介电层5，之后第二次同时蚀刻上层和下层蚀刻阻止层4和2形成通孔图形连接顶部金属电路和上层与下层电路。
然而，在常规的双重镶嵌法中，如果第一次刻蚀过程是使用N2气进行的，通孔内壁上会形成胺基(例如NH2-)。由此形成的胺基在形成上层电路的后处理光刻法过程中可以俘获光致H+离子，由此在曝光和显影后在通孔内壁留下无法除去的光刻胶残余物。因此，在第二次刻蚀过程中形成不合需要的图形，产生如图2所示的较差的电子元件。
因此，已经试图在形成通孔时减少N2气的用量。然而，为了适当控制蚀刻速度和在蚀刻下层介电层时改善选择性，在为了获得较好性能的层使用含碳介电层的时候，使用N2气是不可避免的。
在这方面，已经发展了一种防止俘获H+离子的方法，其中将含氟的低介电材料(介电常数k3.2)填入接触孔，并进行光刻过程。该方法利于在低介电层蚀刻和抛光过程后使用HF溶液除去光刻胶的时候，去除光刻胶和含氟低介电材料。因此，该方法可用于使用介电常数(k)2.7的无孔下层介电层的情况。然而，因为当无孔的含氟低介电材料的蚀刻速度不同于蚀刻无孔和多孔介电层的多孔低介电层蚀刻速度的时候，难以保证获得所需的图形，该过程在使用多孔下层介电层的情况下不能胜任。换言之，因为该多孔低介电层的蚀刻速度高于无孔低介电层，所以蚀刻含氟无孔低介电材料缓慢。因此，该方法无法形成合适的镶嵌结构。
同时，在使用含有小尺寸多孔低介电层情况下，由于介电层在刻蚀过程中受等离子体影响产生硅烷醇基团(≡Si-OH)，从而使得通孔内壁亲水。如上所述，当通孔内壁是亲水性的时候，通孔在潮湿的清洗过程中吸收大量水，由此不希望地增加低介电层的介电常数，降低低介电层的可靠性。
发明内容
本发明是基于上述现有技术的问题而进行的，因此本发明的一个目的是通过双重镶嵌法提供一种在金属间介电层构成图形的方法，其中，在介电层形成通孔后，进行紫外线辐照以便改进通孔内壁化学结构并降低其反应性，从而易于除去在显影过程中难以除去的光刻胶残余物。
基于本发明，实现上述目的可以通过提供一种在金属间介电层的构成图形方法而实现，该方法包含步骤a)在包括在其上形成图案的下层电路图形的半导体基底上依次排放下层蚀刻阻止层、下层介电层、上层蚀刻阻止层和上层介电层，b)在上层介电层、上层蚀刻阻止层和下层介电层上构成图形形成通孔，曝光下层电路上的下层蚀刻阻止层，c)使用紫外线辐照通孔，d)在得到的其上包括通孔的半导体基底上形成光刻胶层，并在光刻胶层上构成图形，e)在上层介电层构成图形，使用构成图形光刻胶层作为蚀刻掩模形成上层介电层上通孔周围的线路，和f)曝光下层电路的顶部。
附图说明
从下面的详细说明和附图将更加清楚地理解本发明的上述和其他目的、特征和其他优点，其中：图1例举说明了常规双重镶嵌法的金属间介电层构成图形方法；图2例举说明了常规双重镶嵌法金属间介电层的构成图形方法，其中通孔内光刻胶残余物不完全除去，但是保留在通孔内；图3例举说明了按照本发明，在改进的双重镶嵌法中当紫外线辐照至通孔的时候，构成通孔内壁成分的化学改性；图4是介电层在介电层的沉积和刻蚀过程后，使用实施例1中的TOF-SIMS分析介电层化学成分含量的直方图；图5是在介电层的刻蚀过程和紫外线辐照过程后，使用实施例1中的TOF-SIMS分析介电层化学成分含量的直方图；图6是实施例2紫外线辐照过程后光刻胶图形的电子显微镜照片；和图7是实施例2不进行紫外线辐照的光刻胶图形电子显微镜照片。
具体实施方式
按照本发明，在半导体基底上的上层和下层介电层中形成通孔后，紫外线辐照该通孔以便改进通孔内壁的化学结构并降低其反应性，从而容易地除去在显影中难以除去的光刻胶残余物。此外，对包含纳米级孔的低介电层的通孔内壁进行脱羟基化处理以防止该多孔低介电层在随后的潮湿-清洗过程中吸水。
图3例举说明了当按照本发明使用紫外线辐照通孔时，内壁表面的化学改性。如图3所示，通孔表面上的大部分胺基与低介电材料的烃基结合，紫外线辐射孔表面时，碳-氮键由于吸收光能量被打断。此时，与紫外线一起可以进一步加入热能以便加速键断裂。
同时，在使用如图3所示多孔材料作为低-k(电介质)层的情况下，通孔内壁的表面上形成硅烷醇基。当紫外线辐照通孔内壁的时候，O-H键被打断，得到的氧自由基进攻邻近的硅原子形成Si-O-Si键。由此，使通孔内壁表面成为疏水性，从而防止由吸水进入介电层所引起的介电常数增加，并防止在包含介电层和通孔的半导体基底上装配的电子元件的性能降低。
另外，在本发明中，可以使用激光束作为光源产生具有特定波长范围的紫外线辐照低介电层，或使用紫外线灯作为光源产生相对长的波长约700纳米或更低的紫外线进行辐照。也可以使用多种其他光源产生紫外线辐照低介电层。优选，可以使用波长为150至400纳米的紫外线。此外，为了获得更好的结果，与紫外线一起可以给通孔进一步提供100至300℃的热能。
此外，紫外线可以辐照上层介电层全部，或使用光掩模和曝光装置蚀刻的上层介电层的一部分，也就是说，仅辐照通孔。
此外，按照本发明，优选在通孔形成后，但是在为第二次介电层曝光过程涂布光刻胶之前进行紫外线辐照通孔。然而，在蚀刻或抛光过程后可以进行紫外线辐射通孔。
同时，在本发明中，本领域公知的SiO2层、SiOF层、SiOC层和多孔介电层可用作金属间介电层。
可以由多种方法形成多孔介电层，例如，在半导体基底上的化学蒸气沉积法，或者将含气凝胶或干凝胶物质和表面活性剂或成孔物质的前体溶液涂布和硬化的方法。
可以列举的但是非限定的表面活性剂的例子包括硫酸盐、磺酸盐、磷酸盐、羧酸、烷基铵盐、双生表面活性剂、十六烷基乙基哌啶鎓盐、二烷基二甲基铵、伯胺、聚氧化环氧乙烷、八乙烯基乙二醇单癸基醚、八乙烯基乙二醇单十六烷基醚和其嵌段共聚物。
此外，成孔物质的例子包括聚己酸内酯、环糊精、聚氧化环氧乙烷、八乙烯基乙二醇单癸基醚、八乙烯基乙二醇单十六烷基醚和其嵌段共聚物，但是成孔物质不限于上述实例。
用于本发明的蚀刻阻止层的例子是碳化硅层(SiC层)、碳氮化硅(SiCN)层、氮化硅(SiN)层或非晶态硅碳化物(a-SiC)层。
在形成本发明双镶嵌图形后，填充金属阻隔层和金属罐。金属阻隔层材料的例子包括至少一种金属选自Ti、TiN、Ta、TaN和非晶态硅碳化物(SiC)，金属材料的例子包括铜。
通过下列实施例可以更好地理解本发明，实施例是例举说明，不应解释为对本发明的限定。实施例1：比较紫外线辐射通孔前后构成通孔内壁的化学成分
由于难以分析构成小尺寸通孔内壁的化学成分，将介电层(无孔的SiOC层)放置在半导体基底上，并在N2气氛下进行无光刻胶图形的干蚀刻，然后使用TOF-SIMS分析构成SiOC层表面的化学成分，作为通孔的化学成分。结果列于图4。从图4能够看出，在介电层放置后仅发现烃类，但是在介电层的干蚀刻过程后发现大量的碳氮化氢和含氮氨基物质。
为了比较紫外线辐射通孔前后构成通孔内壁的化学成分，进行下列测试，结果列于图5。也就是说，将介电层(无孔SiOC层)放置在半导体基底上，干蚀刻，并在200℃下加热，同时紫外线辐照介电层90秒，使用TOF-SIMS分析得到的结构。
从图5能够看出，在紫外线辐照通孔后，通孔内壁上的含氮光刻胶残余物极大地减少，并且通孔内壁的SiOH含量减少了一半。
实施例2：通孔的形成
在半导体基底上形成下层电路，并且在下层电路上依次排放下层蚀刻阻止层，下层介电层、上层蚀刻阻止层和上层介电层。此时，无孔碳化硅(SiC)层与SiOC层分别被用作上层和下层蚀刻阻止层与上层和下层介电层。然后将光刻胶涂布上层和下层介电层上，曝光并显影形成光刻胶图形。使用该光刻胶图形作为掩模依次干蚀刻上层介电层、上层蚀刻-阻止层和下层介电层，以曝光在下层线路上的下层蚀刻阻止层2，从而形成介电层内的通孔。
使用水银灯光源进行紫外线辐照通孔60秒，同时在200℃下加热以除去通孔内壁的蚀刻残余物，以及去除在蚀刻介电层后用水清洗通孔时通孔内壁吸附/吸收的水。在这方面，作为对照样品的另一个通孔不受紫外线辐照。对得到的涂有光刻胶的半导体基底进行紫外线辐照，曝光，并显影以在上层介电层上形成光刻胶图形。紫外线辐射通孔和对照样品，然后拍照，结果如图6和7所示。从图6和7能够看出，图7通孔的光刻胶不能除去，而图6中形成的通孔和光刻胶图形是符合需要的。
如上所述，本发明有利于在金属间介电层按照改进的双重镶嵌法形成金属线路，从而容易地除去在光刻胶显影后难以除去的光刻胶残余物，并防止由吸收进入多孔介电层的水引起的多孔介电层介电常数增加。本发明的另一个优点是由于介电层按照干蚀刻法进行蚀刻，所以不需要在湿蚀刻过程中必需进行的干燥过程，由此不用附加干燥装置而容易地在金属间介电层上构成图形。
本发明以例举方式进行了说明，应当理解的是使用的术语是用来说明而不是用来限定。根据上述教导可以对本发明作出许多改进和变化。因此，应当理解的是在附加的权利要求范围内，可以用不同于具体公开的方法实践本发明。
Claims (10)
1.一种在金属间介电层构成图形的方法，包括：
a)在半导体基底上依次排放下层蚀刻阻止层、下层介电层、上层蚀刻阻止层和上层介电层，所述基底包括在其上形成图形的下层电路；
b)在上层介电层、上层蚀刻阻止层和下层介电层上构成图形以形成通孔，所述通孔曝光下层电路上的下层蚀刻阻止层；
c)使用紫外线辐照通孔；
d)在得到的其上包括通孔的半导体基底上形成光刻胶层，并在光刻胶层上构成图形；
e)在上层介电层使用构成图形光刻胶层作为蚀刻掩模构成图形，形成上层介电层上通孔周围的线路；和
f)曝光下层电路的顶部。
2.权利要求1的方法，其中每个介电层选自SiO2层、SiOF层、SiOC层和多孔介电层。
3.权利要求2的方法，其中形成多孔介电层通过以下步骤形成：
1)在半导体基底上涂布前体溶液形成半导体基底上的介电层；
2)烘烤介电层；
3)固化烘烤后的介电层；和
4)在硬化的介电层上使用热能或紫外线形成孔。
4.权利要求2的方法，其中通过化学蒸气沉积法形成多孔介电层。
5.权利要求3的方法，其中前体溶液包含气凝胶或干凝胶物质。
6.权利要求3的方法，其中前体溶液包含表面活性剂物质。
7.权利要求3的方法，其中前体溶液包含成孔物质。
8.权利要求1的方法，其中蚀刻阻止层是碳化硅(SiC层)、碳氮化硅(SiCN)层、氮化硅(SiN)层或非晶态硅碳化物(a-SiC)层。
9.权利要求1的方法，其中紫外线波长为150-400纳米。
10.权利要求1的方法，其中紫外线辐照通孔的同时，以100-300℃的热能加热通孔。
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| CN101140421B (zh) * | 2006-09-04 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | 形成光刻胶图案的方法 |
| CN105702619A (zh) * | 2014-11-27 | 2016-06-22 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
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| WO2007032563A1 (ja) | 2005-09-16 | 2007-03-22 | Nec Corporation | 配線構造並びに半導体装置及びその製造方法 |
| US7514347B2 (en) * | 2005-10-13 | 2009-04-07 | United Microelectronics Corp. | Interconnect structure and fabricating method thereof |
| JP4567587B2 (ja) * | 2005-12-12 | 2010-10-20 | 富士通株式会社 | 半導体装置の製造方法 |
| US7416990B2 (en) * | 2005-12-20 | 2008-08-26 | Dongbu Electronics Co., Ltd. | Method for patterning low dielectric layer of semiconductor device |
| JP5548332B2 (ja) * | 2006-08-24 | 2014-07-16 | 富士通セミコンダクター株式会社 | 半導体デバイスの製造方法 |
| JP2008103586A (ja) * | 2006-10-20 | 2008-05-01 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
| JP4555320B2 (ja) | 2007-06-15 | 2010-09-29 | 東京エレクトロン株式会社 | 低誘電率絶縁膜のダメージ回復方法及び半導体装置の製造方法 |
| US20090042388A1 (en) * | 2007-08-10 | 2009-02-12 | Zhi-Qiang Sun | Method of cleaning a semiconductor substrate |
| KR101412144B1 (ko) * | 2007-11-26 | 2014-06-26 | 삼성전자 주식회사 | 금속 배선의 제조 방법 및 이를 이용한 이미지 센서의 제조방법 |
| KR20100006756A (ko) * | 2008-07-10 | 2010-01-21 | 삼성전자주식회사 | 반도체 장치 및 이의 제조 방법 |
| DE102008035815A1 (de) | 2008-07-31 | 2010-02-04 | Advanced Micro Devices, Inc., Sunnyvale | Verbessern der strukturellen Integrität und Definieren kritischer Abmessungen von Metallisierungssystemen von Halbleiterbauelementen unter Anwendung von ALD-Techniken |
| US20110232677A1 (en) * | 2010-03-29 | 2011-09-29 | Tokyo Electron Limited | Method for cleaning low-k dielectrics |
| CN102237296A (zh) * | 2010-04-29 | 2011-11-09 | 中芯国际集成电路制造(上海)有限公司 | 通孔刻蚀方法 |
| CN102877041B (zh) * | 2011-07-14 | 2014-11-19 | 中国科学院微电子研究所 | 薄膜沉积方法以及半导体器件制造方法 |
| US8871639B2 (en) * | 2013-01-04 | 2014-10-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacture thereof |
| CN109643745B (zh) * | 2015-08-03 | 2023-07-14 | 亮锐控股有限公司 | 具有反射性侧涂层的半导体发光器件 |
| CN108417532A (zh) * | 2018-03-23 | 2018-08-17 | 上海华虹宏力半导体制造有限公司 | 接触插塞的形成方法 |
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| JP3888794B2 (ja) * | 1999-01-27 | 2007-03-07 | 松下電器産業株式会社 | 多孔質膜の形成方法、配線構造体及びその形成方法 |
| US6420441B1 (en) * | 1999-10-01 | 2002-07-16 | Shipley Company, L.L.C. | Porous materials |
| EP1094506A3 (en) * | 1999-10-18 | 2004-03-03 | Applied Materials, Inc. | Capping layer for extreme low dielectric constant films |
| US6319809B1 (en) * | 2000-07-12 | 2001-11-20 | Taiwan Semiconductor Manfacturing Company | Method to reduce via poison in low-k Cu dual damascene by UV-treatment |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101140421B (zh) * | 2006-09-04 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | 形成光刻胶图案的方法 |
| CN105702619A (zh) * | 2014-11-27 | 2016-06-22 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
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