CN1395296A - 避免低介电常数介电层劣化的方法 - Google Patents

避免低介电常数介电层劣化的方法 Download PDF

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CN1395296A
CN1395296A CN02140253A CN02140253A CN1395296A CN 1395296 A CN1395296 A CN 1395296A CN 02140253 A CN02140253 A CN 02140253A CN 02140253 A CN02140253 A CN 02140253A CN 1395296 A CN1395296 A CN 1395296A
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dielectric constant
dielectric layer
low dielectric
layer
low
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CN1170308C (zh
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张鼎张
刘柏村
莫亦先
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United Microelectronics Corp
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Abstract

一种避免低介电常数介电层劣化的方法。该方法是先于低介电常数介电层表面形成一图案化的光阻层；接着利用光阻层作为硬屏蔽，对该低介电常数介电层进行一蚀刻制程；然后去光阻层；最后再对低介电常数介电层进行一表面处理，以去除低介电常数介电层中的Si－OH键，进而避免低介电常数介电层吸附水气而发生介电特性劣化的现象。

Description

避免低介电常数介电层劣化的方法
技术领域
本发明是提供一种避免低介电常数(low k)介电层发生介电特性劣化的方法。
背景技术
随着半导体元件的尺寸不断缩小，以及积体电路密度不断的提高，伴随而来的金属导线间所产生的RC时间延迟(RC time delay)业已严重地影响到积体电路的运作效能，大大降低了积体电路的工作速度，尤其当制程线宽(linewidth)降到0.25微米，甚至0.13微米以下的半导体制程时，RC时间延迟所造成的影响将更为明显。
由于在金属内连线间所产生的RC时间延迟是由金属导线的电阻值(R)与金属导线间的介电层的寄生电容(C)的相乘积，故减少RC时间延迟的方法可利用电阻值较低的金属做为金属导线，或者是降低金属导线间介电层的寄生电容。在降低电阻方面，使用纯铜作为导线材料的铜连结线技术(copperinterconnect technology)以取代传统的铝铜合金[Al∶Cu(0.5％)]为主要材料的多重金属化制程(multilevel metallization process)已成为势在必行的趋势。因为铜本身具有较低的电阻率(1.6 7μΩ-cm)，加上可承载较高的电流密度而不致产生有铝铜合金的电致迁移(electro migration)之虞，因此可以减少金属导线间的寄生电容，以及金属导线的连结层数。其主要缺陷在于：
但是单单以铜连结线技术仍然无法将金属导线间所产生的RC时间延迟大幅降减低，而且铜连结线技术亦有一些制程上的问题尚待解决，所以利用降低金属导线间介电层的寄生电容来减少RC时间延迟的方法便日益重要。
此外，由于介电层的寄生电容与介电层的介电常数(dielectric constant)相关，因此介电层的介电常数越低，形成于介电层中的寄生电容也就相对的越低。而传统的二氧化硅(介电常数为3.9)已渐渐无法满足目前0.13微米以下的半导体制程的需求，是以一些新的低介电常数材料，例如聚酰亚胺(polyimide，PI)、FPI、FLARETM、PAE-2、PAE-3、或LOSP等已被陆续提出。其主要缺陷在于：
然而，这些低介电常数材料虽具有较低的介电常数值(介于2.6-3.2之间)，但是这些一般主成分为碳氢氧的低介电材料，无论在蚀刻及与其它材料的附着力，或是其本身的各项性质都与传统的二氧化硅有明显差异，而且其大部份有附着性不佳以及热稳定性不足等缺点，因此目前尚无法妥善地整合于一般IC常用的制程。
也因为如此，一些以二氧化硅为基础然后于材料内再掺入一些碳氢等元素的低介电常数介电层，例如HSQ(hydrogen silsesquioxane)(K＝2.8)、MSQ(methyl silsesquioxane)(K＝2.7)、HOSP(K＝2.5)、H-PSSQ(hydriopolysilsesquioxane)、M-PSSQ(methyl polysilsesquioxane)、P-PSSQ(phenylpolysilsesquioxane)或多孔性凝胶(porous sol-gel)(K＜2)等材料，便由于其性质与传统二氧化硅相去不远，因此对目前传统的半导体制程有着较高的整合能力，而为日后所看好。其主要缺陷在于：
但是在对这些以二氧化硅为基本结构的低介电常数材料(HSQ、MSQ、HOSP、porous sol-gel等)构成的介电层进行图案转移时，不论在蚀刻介电层或进行去光阻制程中均会对介电层造成伤害。因为去光阻制程通常是同时使用干式氧等离子灰化(ashing)制程与湿式去光阻液来去除光阻，故使得介电层表面的键结容易被氧等离子打断，而与氧离子以及硷性的去光阻液反应，使受损介电层表面形成Si-OH键而吸附水气。由于水的高介电常数值(K＝78)，介电层吸附水气后将导致介电层的介电常数上升，丧失原本低介电常数特性。此外，吸附的水气亦会使介电层的漏电流上升，使介电层绝缘性变差，甚至会有毒害介层洞(poison via)的情形产生，严重影响产品的可靠度。
发明内容
本发明的主要目的在于提供一种避免低介电常数介电层在去光阻制程中发生介电特性劣化的制作方法，通过首先于半导体芯片的基底表面形成低介电常数介电层；接着在低介电常数介电层表面形成图案化的光阻层；并利用光阻层作为硬屏蔽(hard mask)，对低介电常数介电层进行蚀刻制程；最后进行去光阻制程，并利用六甲基二硅氮烷(HMDS)来对该低介电常数介电层进行表面处理，去除低介电常数介电层中的Si-OH键，达到避免低介电常数介电层劣化的目的。
本发明的目的是这样实现的：一种避免低介电常数介电层劣化的方法，其特征是：它是首先于半导体芯片的基底表面形成低介电常数介电层；通过对图案化的低介电常数介电层进行一表面处理，去除该图案化的低介电常数介电层中的Si-OH键，进而避免该图案化的低介电常数介电层吸附水气而发生介电特性劣化。
该基底为硅芯片。形成该图案化的低介电常数介电层的方法包含有下列步骤：
(1)于该基底表面形成低介电常数介电层；
(2)于该低介电常数介电层表面形成图案化的光阻层；
(3)利用该光阻层作为硬屏蔽，对该低介电常数介电层进行蚀刻制程；
(4)进行去光阻制程。
该低介电常数介电层选自hydrogen silsesquioxane、methylsilsesquioxane、hydrio polysilsesquioxane、methyl polysilsesquioxane、phenyl polysilsesquioxane、HOSP或多孔性凝胶。该低介电常数介电层是选自化学气相沉积法或旋涂方式形成于该基底上。该表面处理是去除该图案化的低介电常数介电层表面在完成蚀刻制程及去光阻制程后所形成的Si-OH键。该表面处理是通过含有六甲基二硅氮烷的溶液作用于该图案化的低介电常数介电层的表面，以去除该图案化的低介电常数介电层中的Si-OH键，进而避免该图案化的低介电常数介电层吸附水气而发生介电常数及漏电流上升的现象。该含有六甲基二硅氮烷的溶液是选自5-15％的六甲基二硅氮烷溶解于己烷中所形成。该表面处理之后，另包含有温度400℃，持温30分钟的热烘烤制程，用来去除残留于该图案化的低介电常数介电层表面的六甲基二硅氮烷。该表面处理是选自六甲基二硅氮烷的蒸气作用于该图案化的低介电常数介电层的表面，以去除该图案化的低介电常数介电层中的Si-OH键，避免该图案化的低介电常数介电层吸附水气而发生介电常数以及漏电流上升的现象。该表面处理是选自使该图案化的低介电常数介电层表面形成疏水性层。
本发明还提供另一种避免低介电常数介电层劣化的方法，其特征是：它是首先于半导体芯片的基底表面形成低介电常数介电层；通过六甲基二硅氮烷对该低介电常数介电层进行表面处理，以去除该低介电常数介电层中的Si-OH键，进而避免该低介电常数介电层吸附水气而发生介电特性劣化的现象。
该基底选自硅芯片。该低介电常数介电层是选自hydrogensilsesquioxane、methyl silsesquioxane、hydrio polysilsesquioxane、methylpolysilsesquioxane、phenyl polysilsesquioxane、HOSP或多孔性凝胶。该低介电常数介电层是选自化学气相沉积法或旋涂方式形成于该基底上。该六甲基二硅氮烷是溶解于己烷中，且该六甲基二硅氮烷的体积百分比浓度为5-15％。该六甲基二硅氮烷是以蒸气的方式来完成该表面处理。该低介电常数介电层是为已图案化的薄膜层。该表面处理是用来使该低介电常数介电层表面形成疏水性层。
本发明的创造点是利用化学物质六甲基二硅氮烷(HMDS)来修补在去光阻制程中被损害的低介电常数介电层，使被损害的低介电常数介电层回复原来的介电特性，避免该低介电常数介电层吸附水气而发生介电特性劣化的现象。
下面结合较佳实施例和附图进一步说明。
附图说明
图1-图4为本发明对低介电常数介电层进行蚀刻制程的方法示意图。
图5为多孔性凝胶介电层的红外光的光谱图。
图6为多孔性凝胶介电层的介电常数示意图图。
图7为多孔性凝胶介电层的电场与漏电流的关系曲线图。
具体实施方式
参阅图1-图4所示，本发明的于低介电常数介电层上进行蚀刻制程的方法如下：
如图1所示，半导体芯片10包含有一硅基底12，一利用化学气相沉积法(chemical vapor deposition，CVD)或旋涂方式(spin-on)而形成于硅基底12表面的低介电常数(low k)介电层14。其中，低介电常数(low k)介电层14是由HSQ(hydrogen silsesquioxane)、MSQ(methyl silsesquioxane)、H-PSSQ(hydrio polysilsesqaioxane)、M-PSSQ(methyl polysilsesquioxane)、P-PSSQ(phenyl polysilsesquioxane)、HOSP与多孔性凝胶(porous sol-gel)等以二氧化硅为基本结构的介电材料所构成。
接着如图2所示，于低介电常数介电层14表面形成一光阻层16，并利用微影技术以于光阻层16表面定义一蚀刻图案。
如图3所示，随后利用图案化的光阻层16作为硬屏蔽(hard mask)，以对低介电常数介电层14进行一蚀刻制程，使蚀刻图案转移到低介电常数介电层14之上。
如图4所示，进行一去光阻制程，先利用一氧等离子对光阻层16进行反应性蚀刻，使氧等离子与光阻层16中的碳、氢元素完全反应，形成气态的二氧化碳与水蒸气而剥除光阻，接着再将半导体芯片10浸泡于湿式去光阻液(wetstripper)，如羟胺(NH2OH)或乙醇胺(HOC2H4NH2)等硷性溶液中，以去除残留在低介电常数介电层14表面的光阻层16。其中，由于氧等离子与去光阻液会损伤低介电常数介电层14表面，使低介电常数介电层14生成Si-OH键而吸附水气，造成低介电常数介电层14介电常数上升与漏电流问题。
最后对该低介电常数介电层14进行一表面处理(surface treatment)，亦即将半导体芯片10浸泡在一溶解有5-15％的六甲基二硅氮烷(Hexamethyldisilazane，HMDS)的己烷(hexanc)溶液中，或是将半导体芯片10置于充满六甲基二硅氮烷(HMDS)蒸气的环境中，使HMDS与低介电常数介电层14的表面的Si-OH键反应，而消除Si-OH键，其化学反应式如下：
Figure A0214025300101
其中，Si-OH可于反应后形成Si-OSi(CH3)3，且经过此化学反应步骤后，HMDS不但可消除低介电常数介电层14中的Si-OH键结，以修复低介电常数介电层14在去光阻步骤中所遭受到的损害，而且还可以达到介电层表面改质的功效，由原本的亲水性表面，改为后来的疏水性表面，以防止后续制程环境中水气的吸附，因而可回复原先的介电层电性。后续可利用400℃，持温30分钟的炉管热烘烤(hotFurnace baking)制程，以去除残留于该低介电常数介电层14表面的六甲基二硅氮烷(HMDS)，完成本发明的制程。
参阅图5所示，为多孔性凝胶介电层的红外光的光谱图，由图5可知，曲线A、B分别为氧等离子去光阻制程前、后的红外光的光谱；曲线C为氧等离子去光阻制程后进行HMDS处理所得的红外光的光谱。
吸收峰1代表Si-OH键的吸收，其吸收位置在波数3000-3500cm-1处。
由图5中可知，介电层在经过去光阻制程后，明显生成Si-OH键的吸收峰1，经过HMDS处理过后的介电层，其Si-OH的吸收峰1的强度会随之降低。
参阅图6所示，为多孔性凝胶介电层的介电常数示意图，点状方块A与斜线方块B分别代表利用氧等离子进行去光阻制程前后的介电常数；格状方块C代表利用氧等离子进行去光阻制程后再经HMDS处理的介电常数。由图中可知，介电层在经过去光阻制程后，介电常数由原本的1.9增加到3.8，然而在经过HMDS处理后，介电常数下降回复到2.7，显示HMDS可修复多孔性凝胶介电层受损结构而改善介电常数增加的问题。
参阅图7，为多孔性凝胶介电层的电场与漏电流密度关系曲线图。其中：
圆形符号●、正方形符号■分别代表氧等离子去光阻制程前、后介电层的电场与漏电流密度关系曲线；三角符号▲为氧等离子去光阻制程后再进行HMDS处理的介电层的电场与漏电流密度关系曲线。
由图7中可明显看出，在去光阻制程前的介电层漏电流密度很低，约为10-10-10-9A/cm2，但经过去光阻制程后造成的漏电流密度大幅上升3-4个数量级(order)，最后再利用本发明方法以HMDS处理后，则可回复下降约1-2个数量级，显示可经HMDS修复介电层受损结构，而改善漏电流增加的问题。
综合上述说明，由于以二氧化硅为基础的低介电常数介电层在去光阻制程中极易受到损伤，使低介电常数介电层表面生成Si-OH键，进而影响该低介电常数介电层的介电性质。故本发明于低介电常数介电层完成去光阻制程后，便将已被损害且生成Si-OH的低介电常数介电层浸泡在含有HMDS的溶液中，或是放置在HMDS的蒸气中，使HMDS与Si-OH发生反应，以除去低介电常数介电层中的Si-OH，以抑制低介电常数介电层中的水气吸附，并降低介电常数与漏电流的上升现象，进而维持低介电常数介电层优良的介电性质。
本发明的主要优点是：相较于传统蚀刻低介电常数介电层的制作方法，本发明在去光阻制程后，使用化学物质(HMDS)来修补在去光阻制程中受损害的低介电常数介电层，以消除其中的Si-OH键，并使低介电常数介电层表面改质成疏水性，阻止水气吸附，进而解决传统低介电常数介电层的介电常数与漏电流上升问题，避免发生介电特性劣化的现象。
以上所述仅为本发明的较佳实施例，凡依本发明所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (19)

1、一种避免低介电常数介电层劣化的方法，其特征是：它是首先于半导体芯片的基底表面形成低介电常数介电层；通过对图案化的低介电常数介电层进行一表面处理，去除该图案化的低介电常数介电层中的Si-OH键，进而避免该图案化的低介电常数介电层吸附水气而发生介电特性劣化。
2、根据权利要求1所述的方法，其特征是：该基底为硅芯片。
3、根据权利要求1所述的方法，其特征是：形成该图案化的低介电常数介电层的方法包含有下列步骤：
(1)于该基底表面形成低介电常数介电层；
(2)于该低介电常数介电层表面形成图案化的光阻层；
(3)利用该光阻层作为硬屏蔽，对该低介电常数介电层进行蚀刻制程；
(4)进行去光阻制程。
4、根据权利要求3所述的方法，其特征是：该低介电常数介电层选自hydrogen silsesquioxane、methyl silsesquioxane、hydriopolysilsesquioxane、methyl polysilsesquioxane、phenylpolysilsesquioxane、HOSP或多孔性凝胶。
5、根据权利要求4所述的方法，其特征是：该低介电常数介电层是选自化学气相沉积法或旋涂方式形成于该基底上。
6、根据权利要求3所述的方法，其特征是：该表面处理是去除该图案化的低介电常数介电层表面在完成蚀刻制程及去光阻制程后所形成的Si-OH键。
7、根据权利要求1所述的方法，其特征是：该表面处理是通过含有六甲基二硅氮烷的溶液作用于该图案化的低介电常数介电层的表面，以去除该图案化的低介电常数介电层中的Si-OH键，进而避免该图案化的低介电常数介电层吸附水气而发生介电常数及漏电流上升的现象。
8、根据权利要求7所述的方法，其特征是：该含有六甲基二硅氮烷的溶液是选自5-15％的六甲基二硅氮烷溶解于己烷中所形成。
9、根据权利要求7所述的方法，其特征是：该表面处理之后，另包含有温度400℃，持温30分钟的热烘烤制程，用来去除残留于该图案化的低介电常数介电层表面的六甲基二硅氮烷。
10、根据权利要求l所述的方法，其特征是：该表面处理是选自六甲基二硅氮烷的蒸气作用于该图案化的低介电常数介电层的表面，以去除该图案化的低介电常数介电层中的Si-OH键，避免该图案化的低介电常数介电层吸附水气而发生介电常数以及漏电流上升的现象。
11、根据权利要求1所述的方法，其特征是：该表面处理是选自使该图案化的低介电常数介电层表面形成疏水性层。
12、一种避免低介电常数介电层劣化的方法，其特征是：它是首先于半导体芯片的基底表面形成低介电常数介电层；通过六甲基二硅氮烷对该低介电常数介电层进行表面处理，以去除该低介电常数介电层中的Si-OH键，进而避免该低介电常数介电层吸附水气而发生介电特性劣化的现象。
13、根据权利要求12所述的方法，其特征是：该基底选自硅芯片。
14、根据权利要求12所述的方法，其特征是：该低介电常数介电层是选自hydrogen silsesquioxane、methyl silsesquioxane、hydriopolysilsesquioxane、methyl polysilsesquioxane、phenylpolysilsesquioxane、HOSP或多孔性凝胶。
15、根据权利要求14所述的方法，其特征是：该低介电常数介电层是选自化学气相沉积法或旋涂方式形成于该基底上。
16、根据权利要求12所述的方法，其特征是：该六甲基二硅氮烷是溶解于己烷中，且该六甲基二硅氮烷的体积百分比浓度为5-15％。
17、根据权利要求12所述的方法，其特征是：该六甲基二硅氮烷是以蒸气的方式来完成该表面处理。
18、根据权利要求12所述的方法，其特征是：该低介电常数介电层是为已图案化的薄膜层。
19、根据权利要求12所述的方法，其特征是：该表面处理是用来使该低介电常数介电层表面形成疏水性层。
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