CN1415137A - 用于扩频时钟系统的零延迟缓冲电路以及方法 - Google Patents
用于扩频时钟系统的零延迟缓冲电路以及方法 Download PDFInfo
- Publication number
- CN1415137A CN1415137A CN00818134A CN00818134A CN1415137A CN 1415137 A CN1415137 A CN 1415137A CN 00818134 A CN00818134 A CN 00818134A CN 00818134 A CN00818134 A CN 00818134A CN 1415137 A CN1415137 A CN 1415137A
- Authority
- CN
- China
- Prior art keywords
- signal
- clock signal
- output
- gate
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
- H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B15/00—Suppression or limitation of noise or interference
- H04B15/02—Reducing interference from electric apparatus by means located at or near the interfering apparatus
- H04B15/04—Reducing interference from electric apparatus by means located at or near the interfering apparatus the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B2215/00—Reducing interference at the transmission system level
- H04B2215/064—Reduction of clock or synthesizer reference frequency harmonics
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B2215/00—Reducing interference at the transmission system level
- H04B2215/064—Reduction of clock or synthesizer reference frequency harmonics
- H04B2215/067—Reduction of clock or synthesizer reference frequency harmonics by modulation dispersion
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/442,751 US6731667B1 (en) | 1999-11-18 | 1999-11-18 | Zero-delay buffer circuit for a spread spectrum clock system and method therefor |
| US09/442,751 | 1999-11-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1415137A true CN1415137A (zh) | 2003-04-30 |
Family
ID=23758011
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN00818134A Pending CN1415137A (zh) | 1999-11-18 | 2000-11-11 | 用于扩频时钟系统的零延迟缓冲电路以及方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US6731667B1 (enExample) |
| EP (1) | EP1238461A1 (enExample) |
| JP (1) | JP2003514479A (enExample) |
| KR (1) | KR100380968B1 (enExample) |
| CN (1) | CN1415137A (enExample) |
| WO (1) | WO2001037428A1 (enExample) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100438599C (zh) * | 2003-06-13 | 2008-11-26 | 奇景光电股份有限公司 | 降低电磁波干扰的装置及调整扩频时钟频率的方法 |
| CN100444077C (zh) * | 2004-10-28 | 2008-12-17 | 京瓷美达株式会社 | 时钟信号控制装置 |
| CN101170398B (zh) * | 2007-11-30 | 2010-04-14 | 北京卫星信息工程研究所 | 一种基于压控晶体振荡器的大动态范围的快速时钟恢复系统 |
| CN101729044A (zh) * | 2008-10-29 | 2010-06-09 | 快捷半导体有限公司 | 调制电源扩展频谱 |
| CN102142831A (zh) * | 2010-01-29 | 2011-08-03 | 英飞凌科技股份有限公司 | 片上自校准延迟监控电路 |
| CN101728939B (zh) * | 2008-10-16 | 2012-07-11 | 通嘉科技股份有限公司 | 周期讯号产生电路、电源转换系统以及使用该电路的方法 |
| CN104978297A (zh) * | 2003-10-16 | 2015-10-14 | 英特尔公司 | 自适应输入/输出缓冲器及其使用方法 |
| CN106444345A (zh) * | 2016-12-19 | 2017-02-22 | 深圳大学 | 时间测量电路、方法和测量设备 |
| CN110474633A (zh) * | 2018-05-09 | 2019-11-19 | 三星电子株式会社 | 用于产生时钟的方法和装置 |
| CN110892643A (zh) * | 2017-04-13 | 2020-03-17 | 德州仪器公司 | 用于满足控制信号的建立时间和保持时间的电路 |
| CN111256836A (zh) * | 2020-03-19 | 2020-06-09 | 广州赛恩科学仪器有限公司 | 一种基于锁相捕捉技术的红外测温实时记录传感系统 |
| CN112134559A (zh) * | 2019-06-25 | 2020-12-25 | 硅谷实验室公司 | 虚拟时钟在锁相环中维持闭环系统的用途 |
| WO2024055547A1 (zh) * | 2022-09-16 | 2024-03-21 | 山东浪潮科学研究院有限公司 | 一种基于epld的基站gnss时钟同步方法及系统 |
Families Citing this family (64)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6847640B1 (en) * | 2000-12-22 | 2005-01-25 | Nortel Networks Limited | High speed physical circuits of memory interface |
| GB2397988B (en) * | 2001-11-02 | 2004-12-15 | Toshiba Res Europ Ltd | Receiver processing system |
| US6982707B2 (en) * | 2002-03-14 | 2006-01-03 | Genesis Microchip Inc. | Method and apparatus utilizing direct digital synthesizer and spread spectrum techniques for reducing EMI in digital display devices |
| US7236551B2 (en) * | 2002-09-27 | 2007-06-26 | Nxp B.V. | Linear half-rate phase detector for clock recovery and method therefor |
| KR100926684B1 (ko) | 2002-11-15 | 2009-11-17 | 삼성전자주식회사 | 스프레드 스펙트럼 클럭 발생기 |
| TW589831B (en) * | 2002-12-05 | 2004-06-01 | Via Tech Inc | Multi-port network interface circuit and related method for triggering transmission signals of multiple ports with clocks of different phases |
| US7187705B1 (en) | 2002-12-23 | 2007-03-06 | Cypress Semiconductor Corporation | Analog spread spectrum signal generation circuit |
| DE60328925D1 (de) * | 2002-12-24 | 2009-10-01 | Fujitsu Microelectronics Ltd | Jittergenerator |
| KR100532415B1 (ko) * | 2003-01-10 | 2005-12-02 | 삼성전자주식회사 | 돌발지터 정보를 차단할 수 있는 동기루프 회로 및 이의돌발지터 정보 차단방법 |
| EP1599942A1 (en) * | 2003-02-24 | 2005-11-30 | Koninklijke Philips Electronics N.V. | Timing control circuit for an optical recording apparatus |
| US7477716B2 (en) * | 2003-06-25 | 2009-01-13 | Mosaid Technologies, Inc. | Start up circuit for delay locked loop |
| US7233210B2 (en) * | 2003-08-26 | 2007-06-19 | Toshiba America Electric Components, Inc. | Spread spectrum clock generator |
| US7236057B2 (en) * | 2003-08-26 | 2007-06-26 | Toshiba America Electronic Components, Inc. | Spread spectrum clock generator |
| KR100541548B1 (ko) | 2003-09-08 | 2006-01-11 | 삼성전자주식회사 | 대역 확산 클럭 발생회로 및 방법 |
| US6980932B2 (en) * | 2003-09-25 | 2005-12-27 | Agilent Technologies, Inc. | Digital measurements of spread spectrum clocking |
| TWI251734B (en) * | 2003-10-28 | 2006-03-21 | Via Tech Inc | Combined transmitter |
| WO2005060105A1 (en) * | 2003-12-15 | 2005-06-30 | Philips Intellectual Property & Standards Gmbh | Circuit arrangement and method for locking onto and/or processing data, in particular audio, t[ele]v[ision] and/or video data |
| KR100532498B1 (ko) * | 2004-01-28 | 2005-11-30 | 삼성전자주식회사 | 오실레이터와 카운터를 이용하는 지연 동기 회로 및 클럭동기 방법 |
| GB0403237D0 (en) * | 2004-02-13 | 2004-03-17 | Imec Inter Uni Micro Electr | A method for realizing ground bounce reduction in digital circuits adapted according to said method |
| KR100541685B1 (ko) * | 2004-04-30 | 2006-01-10 | 주식회사 하이닉스반도체 | 지연 동기 루프 장치 |
| US7138845B2 (en) * | 2004-07-22 | 2006-11-21 | Micron Technology, Inc. | Method and apparatus to set a tuning range for an analog delay |
| KR100603180B1 (ko) * | 2004-08-06 | 2006-07-20 | 학교법인 포항공과대학교 | 주파수 트래킹 기법을 이용한 씨모오스 버스트 모드 클럭데이터 복원 회로 |
| US7706496B2 (en) * | 2005-01-31 | 2010-04-27 | Skyworks Solutions, Inc. | Digital phase detector for a phase locked loop |
| US7190201B2 (en) | 2005-02-03 | 2007-03-13 | Mosaid Technologies, Inc. | Method and apparatus for initializing a delay locked loop |
| US7135902B1 (en) * | 2005-04-22 | 2006-11-14 | National Semiconductor Corporation | Differential signal generator having controlled signal rise and fall times with built-in test circuitry |
| US7676197B2 (en) * | 2005-06-30 | 2010-03-09 | Intel Corporation | Signal spectrum steering method, apparatus, and system |
| KR100763389B1 (ko) * | 2005-07-01 | 2007-10-05 | 엘지전자 주식회사 | 플라즈마 디스플레이 패널 및 그 제조방법 |
| KR100813037B1 (ko) * | 2005-07-01 | 2008-03-14 | 엘지전자 주식회사 | 플라즈마 디스플레이 패널 및 그 제조방법 |
| GB2429590A (en) * | 2005-08-23 | 2007-02-28 | Zarlink Semiconductor Ltd | Variable delay circuit |
| US7555085B1 (en) * | 2005-08-23 | 2009-06-30 | Sun Microsystems, Inc. | CDR algorithms for improved high speed IO performance |
| US8327204B2 (en) * | 2005-10-27 | 2012-12-04 | Dft Microsystems, Inc. | High-speed transceiver tester incorporating jitter injection |
| US7759926B2 (en) * | 2006-02-24 | 2010-07-20 | Lattice Semiconductor Corporation | Dynamic phase offset measurement |
| US7681091B2 (en) | 2006-07-14 | 2010-03-16 | Dft Microsystems, Inc. | Signal integrity measurement systems and methods using a predominantly digital time-base generator |
| US7813297B2 (en) * | 2006-07-14 | 2010-10-12 | Dft Microsystems, Inc. | High-speed signal testing system having oscilloscope functionality |
| US7688928B2 (en) * | 2006-09-05 | 2010-03-30 | Lsi Corporation | Duty cycle counting phase calibration scheme of an input/output (I/O) interface |
| US7894564B2 (en) * | 2006-11-07 | 2011-02-22 | Via Technologies, Inc. | Phase modulation method for spread spectrum clock generator |
| KR100852180B1 (ko) * | 2006-11-24 | 2008-08-13 | 삼성전자주식회사 | 타임투디지털컨버터 |
| KR100834398B1 (ko) * | 2007-01-10 | 2008-06-04 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 및 그의 구동방법 |
| KR100837278B1 (ko) * | 2007-02-27 | 2008-06-11 | 삼성전자주식회사 | 클럭 스큐 컨트롤러 및 그것을 포함하는 집적 회로 |
| KR100871640B1 (ko) * | 2007-03-30 | 2008-12-02 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 및 그 구동방법 |
| US8094698B2 (en) * | 2008-01-29 | 2012-01-10 | Realtek Semiconductor Corp. | Method for generating a spread spectrum clock and apparatus thereof |
| US7917319B2 (en) * | 2008-02-06 | 2011-03-29 | Dft Microsystems Inc. | Systems and methods for testing and diagnosing delay faults and for parametric testing in digital circuits |
| US7808418B2 (en) | 2008-03-03 | 2010-10-05 | Qualcomm Incorporated | High-speed time-to-digital converter |
| JPWO2009116296A1 (ja) * | 2008-03-21 | 2011-07-21 | パナソニック株式会社 | 同期制御回路、及び映像表示装置 |
| US7786772B2 (en) * | 2008-05-30 | 2010-08-31 | Motorola, Inc. | Method and apparatus for reducing spurs in a fractional-N synthesizer |
| EP2192689B1 (en) * | 2008-12-01 | 2012-01-18 | Samsung Electronics Co., Ltd. | Time-to-digital converter and all-digital phase-locked loop |
| US8218702B2 (en) * | 2009-02-18 | 2012-07-10 | Oracle America, Inc. | System and method of adapting precursor tap coefficient |
| US8229020B2 (en) * | 2009-03-23 | 2012-07-24 | Oracle America, Inc. | Integrated equalization and CDR adaptation engine with single error monitor circuit |
| JP5213264B2 (ja) * | 2009-06-24 | 2013-06-19 | 株式会社アドバンテスト | Pll回路 |
| US8180006B2 (en) * | 2009-08-13 | 2012-05-15 | Himax Technologies Limited | Spread-spectrum generator |
| KR101196706B1 (ko) * | 2009-10-29 | 2012-11-07 | 에스케이하이닉스 주식회사 | 지연 고정 루프 회로를 포함하는 반도체 집적 회로 |
| US20120218001A1 (en) | 2009-11-12 | 2012-08-30 | Rambus Inc. | Techniques for Phase Detection |
| US8222966B2 (en) * | 2010-09-10 | 2012-07-17 | Intel Corporation | System, method and apparatus for an open loop calibrated phase wrapping phase modulator for wideband RF outphasing/polar transmitters |
| US8913704B2 (en) * | 2011-07-01 | 2014-12-16 | Infineon Technologies Ag | Method and system for jitter reduction |
| US9160350B2 (en) * | 2011-11-15 | 2015-10-13 | Rambus Inc. | Integrated circuit comprising a delay-locked loop |
| US8664994B1 (en) * | 2012-10-10 | 2014-03-04 | Department of Electronics and Information Technology | System to generate a predetermined fractional period time delay |
| TWI483554B (zh) * | 2013-06-19 | 2015-05-01 | Univ Nat Taiwan | 倍頻延遲鎖定迴路 |
| FR3046856B1 (fr) | 2016-01-15 | 2020-06-05 | Continental Automotive France | Procedes et dispositifs de comptage d’une duree de service pour un signal d’horloge etale ainsi que de determination ou generation d’une duree reelle de temps |
| KR20190057191A (ko) * | 2017-11-17 | 2019-05-28 | 삼성디스플레이 주식회사 | 게이트 클록 신호를 변조하는 타이밍 컨트롤러 및 이를 포함하는 표시 장치 |
| US11714127B2 (en) | 2018-06-12 | 2023-08-01 | International Business Machines Corporation | On-chip spread spectrum characterization |
| US11283437B2 (en) | 2019-12-17 | 2022-03-22 | Skyworks Solutions, Inc. | Measuring pin-to-pin delays between clock routes |
| KR102832205B1 (ko) * | 2020-04-10 | 2025-07-10 | 삼성전자주식회사 | 반도체 장치 |
| US12166485B2 (en) * | 2021-09-13 | 2024-12-10 | Rambus Inc. | Methods and circuits for slew-rate calibration |
| US11693446B2 (en) | 2021-10-20 | 2023-07-04 | International Business Machines Corporation | On-chip spread spectrum synchronization between spread spectrum sources |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5544203A (en) | 1993-02-17 | 1996-08-06 | Texas Instruments Incorporated | Fine resolution digital delay line with coarse and fine adjustment stages |
| US5488627A (en) | 1993-11-29 | 1996-01-30 | Lexmark International, Inc. | Spread spectrum clock generator and associated method |
| US5548249A (en) | 1994-05-24 | 1996-08-20 | Matsushita Electric Industrial Co., Ltd. | Clock generator and method for generating a clock |
| US5815016A (en) * | 1994-09-02 | 1998-09-29 | Xilinx, Inc. | Phase-locked delay loop for clock correction |
| US6229861B1 (en) | 1995-06-07 | 2001-05-08 | Intel Corporation | Clock distribution network utilizing local deskewing clock generator circuitry |
| US5663665A (en) | 1995-11-29 | 1997-09-02 | Cypress Semiconductor Corp. | Means for control limits for delay locked loop |
| US5859550A (en) | 1995-12-19 | 1999-01-12 | Cisco Technology, Inc. | Network switching system including a zero-delay output buffer |
| US5727037A (en) | 1996-01-26 | 1998-03-10 | Silicon Graphics, Inc. | System and method to reduce phase offset and phase jitter in phase-locked and delay-locked loops using self-biased circuits |
| US5661419A (en) | 1996-05-23 | 1997-08-26 | Sun Microsystems, Inc. | Dynamic phase-frequency detector circuit |
| US5670869A (en) | 1996-05-30 | 1997-09-23 | Sun Microsystems, Inc. | Regulated complementary charge pump with imbalanced current regulation and symmetrical input capacitance |
| US5943382A (en) * | 1996-08-21 | 1999-08-24 | Neomagic Corp. | Dual-loop spread-spectrum clock generator with master PLL and slave voltage-modulation-locked loop |
| US5771264A (en) * | 1996-08-29 | 1998-06-23 | Altera Corporation | Digital delay lock loop for clock signal frequency multiplication |
| US6101197A (en) * | 1997-09-18 | 2000-08-08 | Micron Technology, Inc. | Method and apparatus for adjusting the timing of signals over fine and coarse ranges |
| US6333659B1 (en) * | 1998-06-01 | 2001-12-25 | Nec Corporation | Clock control method and circuit |
| US6442188B1 (en) * | 1998-07-20 | 2002-08-27 | Intel Corporation | Phase locked loop |
| US6356122B2 (en) * | 1998-08-05 | 2002-03-12 | Cypress Semiconductor Corp. | Clock synthesizer with programmable input-output phase relationship |
| JP3430046B2 (ja) * | 1998-12-17 | 2003-07-28 | エヌイーシーマイクロシステム株式会社 | リング発振器 |
| JP2001007698A (ja) * | 1999-06-25 | 2001-01-12 | Mitsubishi Electric Corp | データpll回路 |
| US6292507B1 (en) * | 1999-09-01 | 2001-09-18 | Lexmark International, Inc. | Method and apparatus for compensating a spread spectrum clock generator |
-
1999
- 1999-11-18 US US09/442,751 patent/US6731667B1/en not_active Expired - Lifetime
-
2000
- 2000-05-13 KR KR10-2000-0025650A patent/KR100380968B1/ko not_active Expired - Lifetime
- 2000-11-11 JP JP2001537871A patent/JP2003514479A/ja not_active Withdrawn
- 2000-11-11 WO PCT/KR2000/001291 patent/WO2001037428A1/en not_active Ceased
- 2000-11-11 CN CN00818134A patent/CN1415137A/zh active Pending
- 2000-11-11 EP EP00978095A patent/EP1238461A1/en not_active Withdrawn
-
2002
- 2002-08-30 US US10/231,312 patent/US6993109B2/en not_active Expired - Lifetime
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100438599C (zh) * | 2003-06-13 | 2008-11-26 | 奇景光电股份有限公司 | 降低电磁波干扰的装置及调整扩频时钟频率的方法 |
| CN104978297B (zh) * | 2003-10-16 | 2019-06-28 | 英特尔公司 | 自适应输入/输出缓冲器及其使用方法 |
| CN104978297A (zh) * | 2003-10-16 | 2015-10-14 | 英特尔公司 | 自适应输入/输出缓冲器及其使用方法 |
| CN100444077C (zh) * | 2004-10-28 | 2008-12-17 | 京瓷美达株式会社 | 时钟信号控制装置 |
| CN101170398B (zh) * | 2007-11-30 | 2010-04-14 | 北京卫星信息工程研究所 | 一种基于压控晶体振荡器的大动态范围的快速时钟恢复系统 |
| CN101728939B (zh) * | 2008-10-16 | 2012-07-11 | 通嘉科技股份有限公司 | 周期讯号产生电路、电源转换系统以及使用该电路的方法 |
| CN101729044A (zh) * | 2008-10-29 | 2010-06-09 | 快捷半导体有限公司 | 调制电源扩展频谱 |
| CN101729044B (zh) * | 2008-10-29 | 2015-01-21 | 快捷半导体有限公司 | 调制电源扩展频谱 |
| CN102142831A (zh) * | 2010-01-29 | 2011-08-03 | 英飞凌科技股份有限公司 | 片上自校准延迟监控电路 |
| CN102142831B (zh) * | 2010-01-29 | 2016-04-13 | 英特尔移动通信有限责任公司 | 片上自校准延迟监控电路 |
| CN105811934A (zh) * | 2010-01-29 | 2016-07-27 | 英特尔移动通信有限责任公司 | 片上自校准延迟监控电路 |
| CN105811934B (zh) * | 2010-01-29 | 2019-07-09 | 英特尔移动通信有限责任公司 | 片上自校准延迟监控电路 |
| CN106444345A (zh) * | 2016-12-19 | 2017-02-22 | 深圳大学 | 时间测量电路、方法和测量设备 |
| CN106444345B (zh) * | 2016-12-19 | 2019-03-08 | 深圳大学 | 时间测量电路、方法和测量设备 |
| CN110892643A (zh) * | 2017-04-13 | 2020-03-17 | 德州仪器公司 | 用于满足控制信号的建立时间和保持时间的电路 |
| CN110892643B (zh) * | 2017-04-13 | 2024-03-29 | 德州仪器公司 | 用于满足控制信号的建立时间和保持时间的电路 |
| CN110474633A (zh) * | 2018-05-09 | 2019-11-19 | 三星电子株式会社 | 用于产生时钟的方法和装置 |
| CN110474633B (zh) * | 2018-05-09 | 2024-06-07 | 三星电子株式会社 | 用于产生时钟的方法和装置 |
| CN112134559A (zh) * | 2019-06-25 | 2020-12-25 | 硅谷实验室公司 | 虚拟时钟在锁相环中维持闭环系统的用途 |
| CN111256836A (zh) * | 2020-03-19 | 2020-06-09 | 广州赛恩科学仪器有限公司 | 一种基于锁相捕捉技术的红外测温实时记录传感系统 |
| WO2024055547A1 (zh) * | 2022-09-16 | 2024-03-21 | 山东浪潮科学研究院有限公司 | 一种基于epld的基站gnss时钟同步方法及系统 |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1238461A1 (en) | 2002-09-11 |
| US6993109B2 (en) | 2006-01-31 |
| KR20000053958A (ko) | 2000-09-05 |
| US20030169086A1 (en) | 2003-09-11 |
| JP2003514479A (ja) | 2003-04-15 |
| US6731667B1 (en) | 2004-05-04 |
| KR100380968B1 (ko) | 2003-04-21 |
| WO2001037428A1 (en) | 2001-05-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1415137A (zh) | 用于扩频时钟系统的零延迟缓冲电路以及方法 | |
| US8081013B1 (en) | Digital phase and frequency detector | |
| US7084681B2 (en) | PLL lock detection circuit using edge detection and a state machine | |
| US7595672B2 (en) | Adjustable digital lock detector | |
| CN101656536B (zh) | 锁相环及其锁定检测装置和方法 | |
| CN1656384A (zh) | 采用组件不变微调延迟线的定时测量系统和方法 | |
| US20120319734A1 (en) | System and method for reducing power consumption in a phased-locked loop circuit | |
| CN1909376A (zh) | 相位及频率检测电路 | |
| CN1315080A (zh) | 调谐锁相环的带宽的方法 | |
| CN1527948A (zh) | 测试系统使用的低抖动时钟 | |
| CN1815892A (zh) | 一种检测相位误差并产生控制信号的电路 | |
| TWI390853B (zh) | 鎖住偵測器與其方法,與應用其之鎖相迴路 | |
| CN1400662A (zh) | 芯片上抖动的测量装置及方法 | |
| CN1152822A (zh) | 用于非整数倍频系统的时钟同步方法 | |
| Son et al. | A 0.42–3.45 Gb/s referenceless clock and data recovery circuit with counter-based unrestricted frequency acquisition | |
| CN1463494A (zh) | 半导体集成电路 | |
| US7590194B2 (en) | Information handling system capable of detecting frequency lock of signals downstream from a signal synthesized by frequency synthesizer | |
| CN105959001B (zh) | 变频域全数字锁相环及锁相控制方法 | |
| CN1292555C (zh) | 一种锁相环的频率锁定检测电路 | |
| WO2006044123A1 (en) | Reducing metastable-induced errors from a frequency detector that is used in a phase-locked loop | |
| CN101183872B (zh) | 全频率宽度的多重相位延迟锁定回路 | |
| KR102509984B1 (ko) | 클락 신호의 주파수 및 위상을 감지하는 집적 회로 및 이를 포함하는 클락 및 데이터 복원 회로 | |
| CN115361014B (zh) | 一种基于数字的锁定检测系统 | |
| US7620126B2 (en) | Method and apparatus for detecting frequency lock in a system including a frequency synthesizer | |
| CN101826870B (zh) | 全频率宽度的多重相位延迟锁定回路 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: YANAPAS COMPANY Free format text: FORMER OWNER: LI JINGHAO Effective date: 20041126 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20041126 Address after: Seoul City, Korea Applicant after: Yann Paz Co. Address before: Seoul City, Korea Applicant before: Li Jinghao |
|
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |