CN1338117A - Multilayer circuit board and semiconductor device - Google Patents

Multilayer circuit board and semiconductor device Download PDF

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Publication number
CN1338117A
CN1338117A CN00803094A CN00803094A CN1338117A CN 1338117 A CN1338117 A CN 1338117A CN 00803094 A CN00803094 A CN 00803094A CN 00803094 A CN00803094 A CN 00803094A CN 1338117 A CN1338117 A CN 1338117A
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China
Prior art keywords
circuit board
conductor
multilayer
via hole
conductive
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Granted
Application number
CN00803094A
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Chinese (zh)
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CN1319157C (en
Inventor
浅井元雄
苅谷隆
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Ibiden Co Ltd
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Ibiden Co Ltd
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Publication date
Priority claimed from JP2000245656A external-priority patent/JP4592891B2/en
Priority claimed from JP2000245648A external-priority patent/JP2001217356A/en
Priority claimed from JP2000245649A external-priority patent/JP4592889B2/en
Priority claimed from JP2000245650A external-priority patent/JP4592890B2/en
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Publication of CN1338117A publication Critical patent/CN1338117A/en
Application granted granted Critical
Publication of CN1319157C publication Critical patent/CN1319157C/en
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/4617—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar single-sided circuit boards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2924/01046—Palladium [Pd]
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    • H01L2924/01078—Platinum [Pt]
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    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

A multilayer printed-circuit board is provided which is formed by stacking one on the other a plurality of circuit boards, each including a hard insulative substrate having a conductor circuit formed on one or either side thereof, and having formed therein via-holes formed through the hard insulative substrate to extend to the conductor circuit and each filled with a conductive substance, with an adhesive applied between the plurality of circuit boards, and heating and pressing the circuit boards together. One of the outermost ones of the stacked circuit boards has formed on the surface thereof conductive bumps each positioned right above the via-hole and electrically connected to the via-hole, and the other outermost one of the stacked circuit boards has formed on the surface thereof conductive pin or balls each positioned right above the via-hole and electrically connected to the via-hole. This multilayer printed-circuit board is used as a package circuit board and electronic components such as LSI chip are mounted on it to form a semiconductor device. The multilayer printed-circuit board is used as a core substrate, and a build-up wiring layer is formed on one or either side of the core multilayer circuit board. Solder bumps are formed on the surface of one outermost conductor circuit of the build-up wiring layer and conductive pins or balls are provided on the surface of the other outermost conductor circuit of the build-up wiring layer. Thus, a multilayer printed-circuit board is provided on which wiring can be made densely and also electronic components can be mounted with a high density.

Description

Multilayer circuit board and semiconductor device
Technical Field
The present invention relates to a multilayer circuit board which is advantageous for ultra-high density wiring, a multilayer printed wiring board on which build-up wiring layers are formed on the multilayer circuit board, and a semiconductor device including a semiconductor element mounted thereon, and particularly to a multilayer circuit board whichis formed by laminating single-sided circuit boards each having a plurality of filled vias or double-sided circuit boards as a core on both sides thereof and heating and pressing the laminated circuit boards together via an adhesive, a multilayer printed wiring board on which build-up wiring layers are formed on at least one side of the multilayer circuit board, and a semiconductor device using these.
Background
In recent years, along with the progress of the electronic industry, electronic instruments are becoming smaller and faster, and in order to meet this situation, higher density and higher reliability of fine patterns of a package substrate on which an IC chip is mounted have been demanded.
As such a package substrate, in the 'surface mounting technology' of No. 1/1997, a circuit board in which a build-up multilayer wiring layer is formed on both sides of a multilayer core board is disclosed.
In the package substrate of the prior art, the conductor layer and the build-up wiring layer in the multilayer core board are connected to each other by providing an inner pad, which is wired from the via hole, on the surface of the multilayer core board and connecting the inner pad to the via hole. Therefore, the land shape of the via is changed to a tumbler shape or a dumbbell shape, and the region of the inner layer pad thereof hinders the increase of the arrangement density of the via, so that the formation number of the via is limited to a certain extent. Therefore, in order to achieve a higher density of wiring, the multilayer core board and the outer-layer composite wiring layer have a problem that good electrical contact with the conductive layer in the multilayer core board cannot be ensured.
In order to solve such a problem, the present inventors have proposed an improvementmethod in Japanese patent application No. 10-15346 (Japanese patent application laid-open No. 11-214846).
The structure of the multilayer printed circuit board according to the improved scheme is as follows: in a multilayer printed wiring board formed by alternately laminating interlayer insulating resin layers and conductor layers on a multilayer core board having a conductor layer as an inner layer and forming a build-up wiring layer in which the conductor layers are connected to each other through a via hole, a through hole is formed in the multilayer core board, a filler is filled in the through hole, an exposed surface of the filler exposed from the through hole is covered with the filler to form a conductor layer, and the via hole is connected to the conductor layer. This can increase the arrangement density of the vias, and ensure connection to the conductor circuit in the core board by the high-density through holes.
However, since the through-hole in the multilayer printed wiring board having the above-described structure is formed by opening a through-hole in the core board with a drill or the like and performing electroless plating on the wall surface of the through-hole and the surface of the base board, the lower limit of the obtainable through-hole diameter is about 300 μm in view of the hole diameter accuracy and the economical efficiency, and in order to realize ultra-high density wiring that can satisfy the current demands in the electronics industry, it is desired to develop a technique that can obtain a small hole diameter of about 50 to 250 μm and a narrower land gap.
Accordingly, the present inventors have found that: in this case, it is not necessary to provide through holes in the multilayer core board, and electrical connection performance between the conductor circuits in the multilayer core board, and between the conductor circuits in the multilayer core board and the build-up wiring layer formed on the multilayer core board can be ensured by the filled vias formed in the multilayer core board and the vias formed in the build-up wiring layer directly above the filled vias.
In addition, various electronic components such as LSI chips are mounted on the outermost surface of such a multilayer circuit board, and examples of a method for mounting such electronic components include a pin mounting method in which a component hole for inserting a terminal portion of an electronic component is formed at a predetermined position of a conductor circuit formed on the outermost surface, and a land for connection having a diameter slightly larger than the diameter of the component hole at a position surrounding the component hole is formed, and a pin of the electronic component is connected to the land by soldering, and a surface mounting method in which a solder paste is applied in advance to the land formed at a predetermined position of the conductor circuit, the electronic component is placed, the terminal portion thereof is brought into contact with the solder paste, and then the electronic component is connected by reflow in a state where the solder is melted.
However, in the above method, it is indispensable to provide a land having an appropriately sized diameter on the conductor circuit. However, with the recent demand for miniaturization and high performance of electronic instruments, the larger the number of electronic components to be mounted, the more the total area of lands cannot be ignored, which becomes a factor that hinders high density.
In addition, when soldering work for connecting electronic components is performed, it is necessary to coat solder resist in advance to prevent solder from flowing to unnecessary places and to prevent short-circuiting, disconnection, and the like. Therefore, in designing, it is necessary to take into account a positional error in solder resist printing and to leave a margin between wirings, which also becomes a factor that hinders densification.
Disclosure of the invention
The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a multilayer circuit board or multilayer printed wiring board which can perform high-density wiring and high-density mounting, and a semiconductor device using the same.
The present inventors have made diligent studies to achieve the above object, and as a result, have accomplished the invention whose main configuration is as follows. That is to say that the first and second electrodes,
(1) the multilayer circuit board of the present invention is a multilayer circuit board formed by laminating a plurality of circuit boards each having a conductor circuit on one or both surfaces of an insulating hard substrate and having a via hole formed by filling a conductive material into an opening penetrating the insulating hard substrate and extending to the conductor circuit with an adhesive and heating and pressurizing the laminated circuit boards together, characterized in that:
in the laminated circuit boards, a conductive flange is formed on the surface of one circuit board located on the outermost side, the conductive flange being located directly above the via hole and electrically connected to the via hole, and a conductive pin or ball is arranged on the surface of the other circuit board located on the outermost side, the conductive pin or ball being located directly above the via hole and electrically connected to the via hole.
(2) The multilayer circuit board of the present invention is a multilayer circuit board formed by laminating a plurality of circuit boards each having a conductor circuit on one surface of an insulating hard substrate and a via hole formed by filling a conductive material into an opening penetrating the insulating hard substrate and extending to the conductor circuit, and a single-sided circuit board each having a conductor circuit on one surface of an insulating hard substrate and an opening penetrating the insulating hard substrate and extending to the conductor circuit, with an adhesive, and heating and pressurizing the laminated circuit boards together, characterized in that:
in the laminated circuit boards, a conductive flange is formed on the surface of one circuit board located on the outermost side, the conductive flange being located directly above the via hole and electrically connected to the via hole, and a conductive pin or ball electrically connected to a conductor circuit of the circuit board is arranged in an opening of the other circuit board located on the outermost side.
In the multilayer circuit board according to the above (1), it is preferable that a solder resist layer is provided on a surface of one circuit board located on an outermost side of the plurality of circuit boards to cover the conductor circuit, a conductive flange is formed directly above the via hole to be connected to the conductor layer/via hole exposed from the opening formed in the solder resist layer, a solder resist layer is also provided on a surface of the other circuit board located on an outermost side to cover the conductor circuit, and a conductive pin or ball is disposed directly above the via hole to be connected to the conductor layer/via hole exposed from the opening formed in the solder resist layer.
In the multilayer circuit board according to the above (1) or (2), it is preferable that the distance between adjacent vias formed in each circuit board gradually increases from one circuit board to another circuitboard.
(3) The semiconductor device of the present invention is characterized in that: the multilayer circuit board of (1) or (2) above, and an electronic component electrically connected to a conductive flange formed on the outermost one of the multilayer circuit boards.
In the semiconductor device according to the above (3), it is preferable that the reinforcing member is disposed in a peripheral portion of the circuit board on which the electronic component is mounted, and the chip capacitor is electrically connected to the via hole in a position facing the electronic component mounting position among the via holes formed in the outermost circuit board facing the circuit board.
(4) A semiconductor device according to the present invention is a semiconductor device including a multilayer circuit board in which a plurality of circuit boards each having a conductor circuit on one or both surfaces of an insulating hard substrate, a via hole formed by filling a plating material into an opening penetrating the insulating hard substrate and extending to the conductor circuit, and a projecting conductor electrically connected to the via hole are laminated together by heating and pressurizing, and an electronic element such as an LSI chip electrically connected to an outermost circuit board of the multilayer circuit board, the multilayer circuit board including:
a conductive flange which is located right above the via hole and is electrically connected to the via hole is formed on the surface of the outermost one of the circuit boards, and the electronic component is electrically connected to the conductive flange,
the chip capacitor is electrically connected to a via hole directly below the electronic component on the outermost surface of the circuit board opposite to the circuit board on which the electronic component is mounted.
In the semiconductor device according to the above (4), it is preferable that a reinforcing member for preventing the bottom plate from being lifted up is bonded and fixed to a peripheral portion of the circuit board on which the electronic component is mounted.
(5) The multilayer circuit board of the present invention is a multilayer circuit board in which interlayer resin insulation layers and conductor layers are alternately laminated on one surface or both surfaces of a multilayer core board having a conductor circuit in an inner layer, and a build-up wiring layer connected by via holes is formed between the conductor layers, characterized in that:
the multilayer core board is formed by laminating a plurality of circuit boards, each having a conductor circuit on both or one surface of an insulating hard substrate and a via hole formed by filling a conductive material into a hole penetrating the insulating hard substrate and extending to the conductor circuit, with an adhesive, and heating and pressurizing the laminated circuit boards together.
In the multilayer circuit board according to the above (5), it is preferable that build-up wiring layers are formed on both surfaces of the multilayer core board, a solder bump is provided on a surface of one outermost conductor layer constituting the build-up wiring layers, and a conductive nail or a ball is arranged on a surface of the other outermost conductor layer constituting the build-up wiring layers.
Further, an outermost conductor layer constituting the build-up wiring layer is covered with a solder resist layer, and the outermost conductor layer exposed from an opening provided in the solder resist layer is formed as a conductor pad (or a connection terminal), thereby providing a multilayer printed wiring board suitable as a motherboard.
Further, in the multilayer circuit board according to the above (5), it is preferable that the build-up wiring layer is formed on one surface of the multilayer core board, a solder bump connected to an electronic component including a semiconductor chip such as an LSI is formed on a surface of an outermost conductor layer of the build-up wiring layer directly above the via hole, and a conductive pin or a ball connected to the motherboard is formed on a conductor circuit exposed from the other surface of the multilayer core board directly above the filled via hole. Preferably, the other surface of the outermost conductor layer and the multilayer core board constituting the build-up wiring layer is covered with a solder resist, a conductor pad is formed on one of the outermost conductor layers exposed from an opening provided in the solder resist, and a conductive pin or a ball connected to the motherboard is formed on the conductor circuit exposed from the other surface of the multilayer core board directly above the filled via hole.
In the multilayer circuit board according to any one of the above (1) to (5), the conductive material is preferably a conductive paste formed by electrolytic treatment of a metal plating or metal particles and a thermosetting resin or a thermoplastic resin.
In the multilayer circuit board according to any one of the above (1) to (5), it is preferable that each of the circuit boards constituting the multilayer core board has a projection-like conductor electrically connected to the via hole at a position corresponding to the via hole, and the projection-like conductor is formed of a conductive paste.
Further, in the multilayer circuit board according to the above (1) to (5), it is preferable that a part of the via holes of the build-up wiring layer are positioned directly above the via holes formed in the multilayer core board and directly connected to the via holes.
Further, in the multilayer circuit boards described in the above (1) to (5), the single-sided/double-sided circuit board as a basic unit constituting the multilayer core board is preferably made of any hard material selected from a glass fiber epoxy resin, a glass fiber bismaleimide-triazine resin, a glass fiber polyphenylene ether resin, an aromatic polyamide nonwoven fiber epoxy resin and an aromatic polyamide nonwoven fiber polyimide resin, and is preferably made of a glass fiber epoxy resin having a thickness of 20 to 100 μm, and the diameter of the filled via is preferably 50 to 250 μm.
Further, the via hole of each circuit board is preferably formed in an opening formed by a carbon dioxide gas laser irradiating the surface of the glass fiber epoxy resin under the conditions of a pulse energy of 5 to 100mJ, a pulse width of 1 to 100 μ s, a pulse interval of 0.5ms or more, and the number of impacts of 1 to 50.
Brief description of the drawings
Fig. 1 is a view showing a laminated state of a single-sided circuit board constituting the present invention.
FIG. 2 is a view showing another laminated state of the single-sided circuit board of the present invention.
Fig. 3 is a view showing still another laminated state of the single-sided circuit board of the present invention.
FIG. 4 is a view showing another laminated state of the single-sided circuit board of the present invention.
Fig. 5(a) to (g) are views showing a part of the manufacturing process of the double-sided circuit board constituting the present invention.
Fig. 6(a) to (f) are views showing a part of the manufacturing process of the double-sided circuit board constituting thepresent invention.
Fig. 7 is a diagram showing an embodiment (including a single-sided circuit board and a double-sided circuit board) of a multilayer circuit board according to the present invention.
Fig. 8 is a view showing another embodiment (composed of only a single-sided circuit board) of the multilayer circuit board of the present invention.
Fig. 9 is a diagram for explaining the position of filling the via hole in the embodiment shown in fig. 8.
Fig. 10 is a diagram showing a semiconductor device of the present invention.
FIG. 11 is a view showing another embodiment of the present invention.
Fig. 12(a) to (f) are views showing a part of the manufacturing process of a multilayer circuit board according to still another embodiment of the present invention (a mode in which wires are combined on one surface of a multilayer core board).
Fig. 13(a) to (c) are views showing a part of the manufacturing process of the same multilayer circuit board.
Fig. 14(a) and (b) are views showing a part of the manufacturing process of the same multilayer circuit board.
Fig. 15(a) to (f) are views showing a part of the manufacturing process of a multilayer circuit board according to another embodiment of the present invention (forming build-up wiring on both surfaces of a multilayer core board).
Fig. 16(a) to (c) are views showing a part of the manufacturing process of the same multilayer circuit board.
Fig. 17(a) and (b) are views showing a part of the manufacturing process of the same multilayer circuit board.
Fig. 18 is a view showing another embodiment in which a BGA or PGA is arranged in addition tothe embodiment shown in fig. 17 (b).
Best mode for carrying out the invention
(1) The invention is characterized in that: a multilayer board obtained by laminating a plurality of single-sided or double-sided circuit boards each having a conductor circuit on one surface or both surfaces of an insulating hard substrate and a via hole formed by filling a conductive substance into an opening penetrating the insulating hard substrate and extending to the conductor circuit, as a constituent unit, or, if necessary, a circuit board having no conductor circuit having a via hole filled with a conductive substance into an opening, and a circuit board laminated via an adhesive layer, and then heating and pressurizing the laminated board, and using the multilayer board as a package substrate.
Namely, it is characterized in that: in a plurality of circuit boards laminated and press-molded together, a conductive flange is formed on the surface of one circuit board located on the outermost side, which is located directly above a via hole to be connected to a connection terminal of an electronic component and is electrically connected to the via hole, and a conductive Pin (PGA) or a Ball (BGA) is arranged on the surface of the other circuit board located on the outermost side, which is located directly above a via hole to be connected to a connection hole or a connection pad on a mother board and is electrically connected to the via hole.
① when the multilayer board is constituted by, for example, 4 single-sided circuit boards A to D, the structure is such that, for example, as shown in FIG. 1, conductor circuits are exposed on the surface of one circuit board A located on the outermost side, and protruded conductors connected to vias are exposed on the surface of the other circuit board D located on the outermost side, and that, as shown in FIG. 2, conductor circuits are exposed on the surfaces of the outermost circuit boards A and D.
② when the multilayer board is configured by using 3 single-sided circuit boards A, B, C and 1 double-sided circuit board E, the structure is such as shown in fig. 3, for example, and conductor circuits are exposed on the surfaces of outermost circuit boards A, C.
③ when the multilayer circuit board is configured by using 3 single-sided circuit boards A, B, C and 1 circuit board F having no conductor circuit, the structure is such that, for example, as shown in fig. 4, the protruded conductors connected to the vias are exposed on the surface of the outermost circuit board A, F.
A multilayer board other than the combinations ① to ③ described above may be formed, in which a conductor pad is formed in a portion located directly above a via hole of a conductor circuit of an outermost circuit board of the multilayer board, and a conductor pad extending in a substantially circular shape is formed on a surface of an insulating base material after the exposed portion of a protruding conductor exposed from a surface of the outermost circuit board is melted by heating and pressing, thereby forming a multilayer circuit board.
In the combination shown in fig. 1, it is preferable to provide a solder paste in an appropriate amount so as to form a solder bump to be connected to an electronic component including a semiconductor chip such as an LSI on a conductor circuit exposed from the surface of the uppermost circuit board, and to arrange a T-shaped nail or a solder ball to be connected to a connector or a connection pad on a motherboard on a conductor pad formed by a protruded conductor at a via hole position of the lowermost circuit board.
Further, a solder bump may be formed on a conductor pad formed of a projection-like conductor at a position of a via hole of the lowermost circuit board connected to a T-shaped nail or a solder ball by supplying an appropriate solder to the conductor circuit exposed from the surface of the outermost circuit board.
In any of the above-described combined structures, the solder bump is formed on the conductor land of the partial conductor circuit formed on the outermost one of the circuit boards or on the conductor land formed by the protruded conductor directly above the via hole, and the T-shaped nail or the solder ball is disposed on the conductor land formed by the protruded conductor directly above the via hole exposed from the surface of the outermost other of the circuit boards or on the partial conductor circuit and the formed conductor land.
In another embodiment, a solder resist layer is provided on the surface of one circuit board located on the outermost side to cover the conductor circuit, a conductive flange is formed directly above the via hole to be connected to the conductor layer/via hole exposed from the opening formed in the solder resist layer, or a solder resist layer is provided on the surface of the other circuit board located on the outermost side to cover the conductor circuit, a conductive pin or ball is formed directly above the via hole, and the conductive pin or ball is connected to the conductor layer/via hole exposed from the opening formed in the solder resist layer.
According to such a configuration, since the filled vias are provided in the multilayer circuit board at a high density and the conductive bumps, the conductive pins, or the conductive balls are arranged directly above the vias exposed from the surface of the outermost circuit board among the vias having such a high density, the wiring layer in the multilayer circuit board is connected to the electronic component including the semiconductor chip such as LSI and the motherboard via the conductive bumps, the conductive pins, or the conductive balls at the shortest wiring length, and high-density wiring can be realized.
Further, since the multilayer circuit board of the present invention is a structure in which a single-sided or double-sided circuit board as a substrate is formed of the same material and these are laminated, cracks or peeling from the interface as a starting point due to thermal expansion hardly occur, and therefore, the reliability of the temperature cycle test can be improved.
In addition, in the embodiment in which the multilayer circuit board is configured by using only the single-sided circuit board, there is an advantage that the warpage is less likely to occur regardless of the presence or absence of the wiring formation.
Further, in the above embodiment, since the conductive bump, the conductive nail, or the ball is formed directly above the via hole exposed from the surface of the outermost circuit board of the multilayer circuit board, it is not necessary to form a solder resist layer as in the conventional art. This is because the insulating layer of the circuit board located at the outermost side can function as a solder resist layer.
(2) Furthermore, the present invention is characterized in that: in a multilayer board formed of laminated multilayer circuit boards, a conductive flange is formed on the surface of one circuit board located on the outermost side, the conductive flange being located directly above a via hole and electrically connected to the via hole, and an opening of the other circuit board located on the outermost side is not filled with a conductive material, and a conductive pin or ball is provided to electrically connect to the conductor circuit.
According to such a structure, one circuit board located at the outermost side of the single-sided circuit boards constituting the multilayer board functions as a reinforcing plate not filled with via holes. This is because the via hole is smaller than the via land of the inner layer, and the periphery of the via land is pressed by the insulating layer of the outermost circuit board when the via hole is formed. Further, since the conductive pins or balls are disposed in the openings provided in the circuit board to be electrically connected to the conductor circuits, a solder resist layer is not necessary.
(3) The invention is characterized in that: a semiconductor device in which an electronic component such as an LSI chip is electrically connected to a conductive bump formed on the outermost circuit board of the multilayer circuit board described in the above (1) or (2).
With this configuration, since the flatness of the conductive flange can be maintained, no contact failure or poor contact between the flange and the electronic component occurs.
In the above semiconductor device, it is preferable that the reinforcing member is disposed on the circuit board on which the electronic mail is mounted in a peripheral portion surrounding the electronic component, and the chip capacitor is directly connected to the via hole formed in the outermost circuit board facing the circuit board on which the electronic component is mounted, at a position facing the mounting position of the electronic component.
With this configuration, the distance between the electronic element such as an LSI and the chip capacitor can be minimized, and the loop inductance between the two can be reduced.
(4) Further, the present invention is a semiconductor device including a multilayer board formed by laminating a plurality of single-sided circuit boards each having filled vias formed by electrolytic plating and pressurizing the laminated boards, and an electronic element such as an LSI chip electrically connected to a circuit board located on the outermost side of the multilayer board, wherein:
a conductive flange is formed on the surface of one of the outermost circuit boards directly above the via hole and electrically connected to the via hole, and an electronic component is electrically connected to the conductive flange via a solder ball.
With this configuration, the distance between the electronic element such as an LSI and the chip capacitor can be minimized, and the loop inductance between the two can be reduced.
In the above semiconductor device, it is preferable that a reinforcing member is bonded and fixed to a peripheral portion of the circuit board on which the electronic component is mounted, in order to prevent the entire chassis from being lifted due to a difference in thermal expansion coefficient between the respective materials constituting the circuit board.
The reinforcing member is preferably formed of a glass resin composite material such as BT, FR4, and FR5, or a metal material such as copper, and is preferably provided so as to surround the electronic component mounted on the circuit board.
(5) The multilayer circuit board of the present invention is characterized in that: a multilayer board is formed by laminating a plurality of such circuit boards and pressing them together, with the multilayer board as a core, and a build-up wiring layer is formed on one or both surfaces of the multilayer core board.
One embodiment of the multilayer core board having the build-up wiring layers formed on both surfaces thereof has a structure in which: an interlayer resin insulating layer and a conductor circuit are alternately laminated on both surfaces of a multilayer core board, the conductor circuits are electrically connected to each other through via holes, conductor pads are formed on at least a part of the surface of one of the outermost conductor circuits of a build-up wiring layer, conductive bumps such as solder bumps are formed on the conductor pads to be connected to connection terminals, conductive nails or balls of an electronic component, and conductor pads are formed on at least a part of the surface of the other outermost conductor circuit to be connected to connection holes (connectors) or connection pads on a mother board.
In the above-described embodiment, the multilayer circuit board for a package substrate suitable for mounting an electronic component can be formed by providing a solder resist layer to cover the outermost conductor circuit of the build-up wiring layer, forming pads on a part of the conductor circuit exposed through the opening formed in the solder resist layer, and disposing conductive bumps, conductive nails, or balls on the conductor pads.
In the above-described embodiment, the solder resist layer is provided to cover the outermost conductor circuit of the build-up wiring layer, and the solder pads are formed on the part of the conductor circuit exposed from the openings formed in the solder resist layer, whereby the multilayer circuit board can be suitably used as a multilayer circuit board for a motherboard. In such an embodiment, it is preferable that a connector is provided on the conductor pad for electrical connection with the package substrate if necessary.
Similarly, the structure of an embodiment in which the build-up wiring layer is formed on one surface of the multilayer core board is: a conductive land is formed on at least a part of the surface of one of the conductor circuits located on the outermost side of the build-up wiring layer, a conductive bump such as a solder bump is formed on the conductive land to be connected to a connection terminal, a conductive nail or a ball of an electronic component, anda conductive land is formed on at least a part of the surface of the conductor circuit on the side of the multilayer core board where the build-up wiring layer is not formed, and the conductive nail or the ball is arranged on the conductive land to be connected to a connection hole (connector) or a connection pad on the motherboard.
With the structure according to each embodiment, since it is not necessary to provide a through hole in the multilayer core board, the degree of freedom in arranging the bonding pad such as a land is improved. As a result, the filled vias can be provided at a high density, and the high density vias can ensure sufficient connection between the outer buildup wiring layer and the conductor circuits in the multilayer core board, thereby realizing high-density wiring. In addition, high density routing may also be achieved within the multilayer core board.
Further, since vias are provided at a high density in the build-up wiring layer, and in such high-density vias, conductive bumps, conductive nails, or conductive balls are arranged on the conductor pads exposed from the openings formed in the outermost interlayer resin insulation layers, the build-up wiring layer in the multilayer circuit board can be connected to an electronic component or a motherboard including a semiconductor chip such as an LSI with the shortest wiring length by such conductive bumps, conductive nails, or conductive balls, and high-density mounting of high-density wiring and electronic components can be realized.
In the multilayer circuit board and the semiconductor device according to the above (1) to (5), the insulating base material used for the double-sided/single-sided circuit board constituting the multilayer board is not a pre-mold in a semi-cured state but a hard insulating base material made of a completely cured resin material, and by using such a material, when the copper foil is pressed against the insulating base material by heating and pressing, the final thickness of the insulating base material does not fluctuate by the pressing, and therefore, positional displacement of the via hole can be suppressed to the minimum, and the diameter of the via hole land can be reduced. Therefore, the wiring interval can be made small, and the wiring density can be improved. Further, since the thickness of the base material can be kept substantially constant, the laser irradiation conditions can be easily set when forming the opening for filling via hole formation by laser processing.
As such an insulating resin matrix, a hard matrix selected from a glass fiber epoxy resin, a glass fiber bismaleimide-triazine resin, a glass fiber polyphenylene ether resin, an aromatic polyamide nonwoven fiber epoxy resin and an aromatic polyamide nonwoven fiber polyimide resin can be used, and a glass fiber epoxy resin matrix is preferably used.
The thickness of the insulating base material is preferably 20 to 600 μm. The reason for this is to ensure insulation. If the thickness is less than 20 μm, the strength is lowered and the workability is difficult, and the reliability of the electrical insulation is low, and if it exceeds 600 μm, the formation of fine openings for via formation is difficult, and the thickness of the base plate itself is increased.
The via hole formed in the glass epoxy resin substrate having a thickness within the above range is preferably formed by a carbon dioxide gas laser irradiated under conditions of a pulse energy of 0.5 to 100mJ, a pulse width of 1 to 100. mu.s, a pulse interval of 0.5ms or more, and a number of impacts of 1 to 50. The pore diameter is preferably in the range of 50 to 250 μm. This is because it is difficult to fill the opening with a conductive material with a thickness of less than 50 μm, and the connection reliability is low, and when it exceeds 250 μm, it is difficult to achieve the high density.
Before forming the opening by such a carbon dioxide gas laser, it is preferable that a resin film is bonded to the conductor circuit forming surface and the opposite surface of the insulating base material, and laser light is irradiated onto the resin film.
The resin film functions as a protective film when the opening for via hole formation is cleaned and the treated opening is filled with a metal plating by electrolytic plating, and also functions as a printing mask for forming a projecting conductor directly above the metal plating layer of the via hole.
The resin film is preferably formed of a PET film having a thickness of the adhesive layer of 1 to 20 μm and a thickness of the film itself of 10 to 50 μm.
This is because the height of the projecting conductor described later depends on the thickness of the PET film, and if the thickness is less than 50 μm, the projecting conductor is too low to easily cause a contact failure, whereas if it exceeds 50 μm, the projecting conductor is too wide at the contact interface to form a fine pattern.
As the conductive material filled in the opening penetrating the insulating base material, a conductive paste or a metal plating formed by electrolytic plating is preferably used.
In order to simplify the filling process, reduce the manufacturing cost, and improve the yield, it is preferable to fill the conductive paste, but in view of connection reliability, metal plating formed by electrolytic plating treatment, for example, metal plating such as tin, silver, solder, copper/tin, copper/silver, and the like is preferable, and electrolytic copper plating is most preferable.
In the multilayer circuit board as a package substrate according to the embodiment of the present invention and the semiconductordevice using the same, the distance between adjacent vias is the smallest between the outermost circuit boards on which electronic components such as LSI chips are mounted and the outermost circuit board connected to the motherboard, that is, the arrangement density of the vias formed on each circuit board to be stacked is preferably smaller from the circuit board on which electronic components such as LSI chips are mounted to the circuit board connected to the motherboard.
The conductor circuit formed on one or both surfaces of the insulating base material is preferably formed by heating and pressing a copper foil having a thickness of 5 to 18 μm with a resin adhesive layer kept in a semi-cured state, and then performing an appropriate etching treatment.
Such heating and pressing are performed under appropriate temperature and pressure conditions, preferably under reduced pressure, and only the resin adhesive layer in a semi-cured state is cured, whereby the copper foil and the insulating base material can be firmly bonded, and therefore, the manufacturing time can be shortened as compared with a conventional circuit board using a prepreg.
The circuit board having such conductor circuits formed on both surfaces of the insulating base material can be used as a core of a multilayer board, and a via land which is a part of the conductor circuit is preferably formed on a surface of the substrate corresponding to each via in a diameter range of 50 to 250 μm.
Further, a single-sided circuit board in which a conductor circuit is formed on one surface of an insulating base material can be used as a laminated circuit board as in the case of a double-sided circuit board, and can be formed as a multilayer board in which only a single-sided circuit board is laminated.
In such a single-sided circuit board, it is preferable to form a bump-like conductor directly above the filled via hole.
The projecting conductor is preferably formed of a conductive paste or a low-melting metal, and the conductive paste or the low-melting metal is thermally deformed in the step of laminating the circuit boards together and heating and pressing the circuit boards, so that the variation in thickness of the conductive material and the metal plating layer filled in the via hole can be reduced. Therefore, a contact failure can be prevented, and a multilayer circuit board with high contact reliability can be obtained.
The protruding conductor and the conductive material filled in the via hole, for example, a conductive paste, are made of the same material and formed by the same filling step.
In the outermost circuit board of the multilayer board formed by the above-described lamination and heating and pressing, the conductive flange formed directly above the via hole is formed in a lattice shape or a matrix shape slightly shifted from the lattice shape, for example, on the surface of the circuit board on which the electronic component such as LSI is mounted.
In the outermost circuit board, the conductive pins or conductive balls formed directly above the vias on the surface of the circuit board connected to the motherboard are formed in a lattice shape or a matrix shape slightly shifted from the lattice shape, for example, like the conductive bumps.
The multilayer circuit board and the semiconductor device using the same of the present invention will be specifically described below with reference to the drawings.
(A) Formation of circuit board for build-up
(1) In the production of the multilayer circuit board of the present invention, a substrate having a copper foil attached to one surface of an insulating base material 10 is used as a starting material for a circuit board constituting the base.
The insulating substrate 10 may be a hard laminate substrate selected from glass fiber epoxy resin, glass fiber bismaleimide-triazine resin, glass fiber polyphenylene ether resin, aromatic polyamide non-woven fiber epoxy resin and aromatic polyamide non-woven fiber polyimide resin, and preferably is glass fiber epoxy resin.
The thickness of the insulating base material 10 is preferably 20 to 600 μm. The reason for this is that if the thickness is less than 20 μm, the strength is reduced and the workability is difficult, and the reliability of the electrical insulation is low, and if it exceeds 600 μm, it is difficult to form fine vias and fill conductive paste, and the bottom plate itself becomes thick.
The thickness of the copper foil 12 is preferably 5 to 18 μm. The reason for this is that when forming a via hole forming opening in an insulating base material by laser processing as described later, it is easy to penetrate the opening if the thickness is too thin, and it is difficult to form a conductor circuit pattern having a fine line width by etching if the thickness is too thick.
As the insulating base material 10 and the copper foil 12, a single-sided copper-clad laminate obtained by laminating a prepreg made of a B-stage (semi-cured state) glass cloth impregnated with an epoxy resin and a copper foil and then heating and pressing the laminate is preferably used. The reason for this is that the copper foil 12 has no errors in the positions of the wiring pattern and the via hole in the post-etching treatment as described later, and has high positioning accuracy.
(2) Next, when a circuit board having conductor circuits formed on both surfaces is manufactured, a protective film 14 is attached to the surface of the insulating base 10 opposite to the surface to which the copper foil 12 is attached (see fig. 5 (a)).
The protective film 14 is used as a printing mask for a conductive paste for forming a projecting conductor described later, and for example, a polyethylene terephthalate (PET) film having an adhesive layer provided on the surface thereof can be used.
The PET film 14 is a film having an adhesive layer with a thickness of 1 to 20 μm and a film thickness of 10 to 50 μm.
(3) Next, the PET film 14 attached to the insulating base 10 is irradiated with carbon dioxide laser light, and penetrates the PET film 4 to form openings 16 from the surface of the insulating base 10 to the copper foil 12 (or the conductor circuit pattern) (see fig. 5 (b)).
The laser processing is performed by a pulse oscillation type carbon dioxide gas laser processing apparatus, and the processing conditions are preferably as follows: the pulse energy is 0.5-100 mJ, the pulse width is 1-100 mus, the pulse interval is more than 0.5ms, and the impact frequency is in the range of 1-50.
The diameter of the via hole formed under such processing conditions is preferably 50 to 250 μm.
(4) The resin residue remaining on the side surfaces and the bottom surface of the opening 16 formed in the step (3) is removed by a cleaning process.
The cleaning treatment is performed by oxygen plasma discharge treatment, corona discharge treatment, ultraviolet laser treatment, excimer laser treatment, or the like. In particular, from the viewpoint of securing connection reliability, it is preferable to perform a cleaning process by irradiating the inside of the opening with an ultraviolet laser or excimer laser.
When the cleaning treatment is performed by, for example, ultraviolet laser irradiation using YAG3 subharmonic, the laser irradiation conditions are preferably: the oscillation frequency is 3-15 KHz, the pulse energy is 0.1-5 mJ, and the impact frequency is 5-30.
(5) Next, the substrate subjected to the cleaning process is subjected to electrolytic copper plating using the copper foil 12 as a plating guide under the following conditions, and the opening 16 is filled with an electrolytic copper plating 18 to form a filled via hole 20 (see fig. 5 (c)). This plating process fills the electrolytic copper plating 18 with a small gap left above the opening 16, and the gap is filled with a conductive paste 22 described later.
[ electrolytic copper plating aqueous solution]
CuSO4·5H2O 65g/l
Leveling agent (HL manufactured by ATOTEK) 20ml/l
Sulfuric acid 220g/l
Polishing agent (UV manufactured by ATOTEK) 0.5ml/l
Chloride ion 40ppm
[ electrolytic plating conditions]
Blowing agent 3.0 l/min
Current density 0.5A/dm2
Set current value of 0.18A
Plating time 130 minutes
(6) The gap or recess of the opening 18 not filled with the electrolytic copper plating 20 in (5) above is filled with a conductive paste 22, and a conductor portion 24 (hereinafter referred to as "projecting conductor") projecting only by the thickness of the protective film 14 is formed from the surface of the insulating base material 10 as a mask for printing the protective film 14 (see fig. 5 (d)).
(7) Next, adhesive layer 26 is formed on the surfaceof insulating base 10 including projected conductor 24 (see fig. 5 (e)). The adhesive 26 is a semi-cured, i.e., B-staged adhesive, and is used for bonding a copper foil on which a conductor circuit pattern is to be formed, and for example, an epoxy resin varnish is used, and the layer thickness thereof is preferably in the range of 15 to 50 μm.
(8) In the step (7), the surface of the insulating base material 10 of the adhesive layer 26 is provided, and the copper foil 28 is pressed by heating and pressing to cure the adhesive layer 26 (see fig. 5 (f)).
At this time, the copper foil 28 is bonded to the insulating base 10 with the cured adhesive 26, and the protruded conductor 24 and the copper foil 28 are electrically connected. The thickness of the copper foil 28 is preferably 5 to 18 μm.
(9) Next, an etching resist is attached to each of the upper surfaces of the copper foils 12 and 28 attached to both surfaces of the insulating base 10, and is covered with a mask having a predetermined circuit pattern, followed by etching treatment to form conductor circuits 30 and 32 (including via lands) (see fig. 5 g).
In this processing step, first, a photosensitive dry film resist is applied to the surfaces of the copper foils 12 and 28, then, exposure and development are performed along a predetermined circuit pattern to form an etching resist, and the metal layer of the portion where the etching resist is not formed is etched to form the conductor circuit patterns 30 and 32 including via lands.
The etching solution is preferably at least one aqueous solution selected from aqueous solutions of sulfuric acid-hydrogen peroxide, persulfate, copper chloride and ferric chloride.
As a pretreatment for forming the conductor circuits 30 and 32 by etching the copper foils 12 and 28, the copper foils may be etched in advance over the entire surface thereof to reduce the thickness thereof to 1 to 10 μm, preferably 2 to 8 μm, for easy formation of fine patterns.
The via land as a part of the conductor circuit has an inner diameter substantially equal to the diameter of the via hole, and an outer diameter preferably within a range of 50 to 250 μm.
(10) Next, if necessary, the surfaces of the conductor circuits 30 and 32 formed in the above-described step (8) are roughened (the rough layer is not shown), and a double-sided circuit board 34 is formed.
The roughening treatment is used to improve adhesion to the adhesive layer and to prevent peeling when the layer is multilayered.
Examples of the roughening treatment include soft etching, oxidation-reduction, formation of a needle-like alloy plating composed of copper, nickel and phosphorus (Ebara-Yujilite, manufactured by INTERPLATE), and roughening of the surface with an etching solution known as "MecEtchbond" from Mec.
In this embodiment, the roughened layer is preferably formed using an etching solution, and for example, the roughened layer can be formed by etching the surface of the conductive circuit using an etching solution formed from a mixed aqueous solution of a copper complex and an organic acid. The etchant dissolves the conductor circuit pattern under an aerobic condition such as spraying or foaming, and the following chemical reaction is presumed to proceed.
In the formula, A represents a complexing agent (which functions as a chelate), and n represents a coordination number.
As shown in the above formula, the generated cuprous complex is melted by the action of acid and combined with oxygen to become a copper complex, which then participates in the oxidation of copper. The copper complex used in the present invention may be an azole copper complex. The etching solution containing the organic acid-copper complex can be prepared by dissolving an azole copper complex and an organic acid (optionally, a halogen ion) in water.
Such an etching solution can be formed, for example, from an aqueous solution obtained by mixing 10 parts by weight of an imidazole copper complex, 7 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride.
The double-sided circuit board constituting the multilayer circuit board of the present invention is produced by the steps (1) to (10) described above.
(11) Next, in manufacturing a single-sided circuit board in which the front and back surfaces of such a double-sided circuit board are laminated, first, an etching protective film is attached to the upper surface of the copper foil 12 (see fig. 6(a)) attached to one surface of the insulating base material 10, and after covering with a mask having a predetermined circuit pattern, etching is performed to form a conductor circuit 40 (including a via land) (see fig. 6 (b)).
In this processing step, first, a photosensitive dry film resist is pasted on the surface of the copper foil 12, then, exposure and development processing are performed along a predetermined circuit pattern to form an etching resist, and the metal layer of a portion where the etching resist is not formed is etched to form the conductor circuit pattern 40 including the via land.
The etching solution is preferably at least one aqueous solution selected from aqueous solutions of sulfuric acid-hydrogen peroxide, persulfate, copper chloride and ferric chloride.
As a pretreatment for forming the conductor circuit 40 by etching the copper foil 12, the copperfoil may be etched in advance over the entire surface thereof so that the thickness of the copper foil is reduced to 1 to 10 μm, preferably 2 to 8 μm, in order to facilitate formation of a fine pattern.
(12) After the conductor circuit 40 is formed on one surface of the insulating base 10, the treatment is performed in the above-described steps (2) to (6), and then the PET film 14 is peeled off from the surface of the insulating base 10 (see fig. 6(c) to 6 (e)).
The height of the protruding conductor 44 (shown by reference numeral 44 for distinguishing from the protruding conductor 24 of the double-sided circuit board) formed in the step (6) protruding from the insulating base material 10 is substantially equal to the thickness of the protective film 14, and preferably in the range of 5 to 30 μm.
This is because: if the height is less than 5 μm, poor contact is likely to occur, and if it exceeds 30 μm, the resistance value becomes high, and if the projected conductor 24 is thermally deformed in the heating and pressing step, the projected conductor is too wide along the surface of the insulating substrate, and thus a fine pattern cannot be formed.
It is preferable that the projecting conductor 44 is subjected to a predetermined shaping process. This is because the projecting conductor 44 is hard even in a semi-hardened state, and there is a possibility that electrical contact may occur with a conductor circuit (conductor pad) of another circuit board to be laminated before the adhesive layer is softened in the lamination pressurization stage.
Since the contact area of the protruding conductor 44 is increased by the deformation during heating and pressing, the on-resistance can be reduced, and the variation in height of the protruding conductor 44 can be corrected.
(13) Next, resin adhesive 46 is applied to the surface of protruding conductor 44 including insulating base 10 (see fig. 6 (f)).
Such a resin adhesive can be formed as an adhesive layer made of an uncured resin in a dry state, for example, by coating the entire surface of the projected conductor 44 including the insulating base 10 or the surface not including the projected conductor 44. The adhesive layer is preferably subjected to a predetermined treatment for easy processing, and the thickness thereof is preferably within a range of 5 to 50 μm.
The adhesive layer 46 is preferably formed of an organic adhesive, and the organic adhesive is preferably at least 1 resin selected from the group consisting of an epoxy resin, a polyimide resin, a thermosetting polyphenylene ether (PPE), a composite resin of an epoxy resin and a thermoplastic resin, a composite resin of an epoxy resin and a silicone resin, and a BT resin.
The coating method of the uncured resin of the organic adhesive may use Curtain (Curtain) coating, spin coating, roll coating, spray coating, screen printing, and the like. Further, the adhesive layer may be formed by laminating adhesive sheets.
The single-sided circuit board 50 has a conductor circuit 40 on one surface of an insulating base 10, a projecting conductor 44 formed by exposing a part of conductive paste on the other surface, and an adhesive layer 46 on the surface of the insulating base 10 including the projecting conductor 44, and a plurality of such single-sided circuit boards are laminated and bonded to each other or to a prefabricated double-sided circuit board 34 to form a multilayer board 60.
(B) Production of multilayer boards
The integrated multilayer circuit board 60 (see fig. 7) is formed by once press molding of a 4-layer board, which is formed by laminating 3 single-sided circuit boards 50, 52 and 54 on both sides of the double-sided circuit board 34 manufactured in the above-described processing steps (a), at a heating temperature of 150 to 200 ℃ and a pressing force of 1M to 4 MPa.
Under the above conditions, the adhesive layer 46 of each single-sided circuit board is cured by simultaneous pressurization and heating, and thereby the adjacent single-sided circuit boards are firmly bonded to each other. Further, as the heating and pressurizing, it is preferable to use vacuum hot pressing.
In the above embodiment, a 4-layer multilayer board is formed using a 1-layer circuit board and a 3-layer circuit board, but a multilayer board having more than 5 or 6 layers can also be applied.
(C) Arrangement of conductive flange, conductive nail and conductive ball
In the multilayer circuit board formed in each processing step (B), a conductive pad is provided on the outermost circuit board, and an electronic component such as an LSI is directly mounted thereon, and a conductive pin or a conductive ball is provided on the outermost circuit board so as to be directly connected to a connection terminal (connector) or a conductive ball on a motherboard, thereby forming a package board.
For example, a multilayer board 60 shown in fig. 7 has a structure in which the conductor circuits 40 of the outermost circuit boards 50 and 54 are exposed from the outside, and in this multilayer board, an appropriate solder pad portion is provided on each conductor circuit 40 directly above the via hole, and an appropriate solder body is supplied to these solder pad portions to form a conductive bump 62, or a conductive nail 64 or a conductive ball 66.
Further, it is preferable to use a tin/lead solder (melting point 183 ℃) or a tin/silver solder (melting point 220 ℃) having a low melting point as the solder body for forming the conductive flange 62, and a tin/antimony solder, a tin/silver solder or a tin/silver/copper solder having a high melting point of 230 ℃ to 270 ℃ as the solder body for connecting the conductive pin 64 or the conductive ball 66.
In addition, when a multilayer board 80 in which 4 sheets of single-sided circuit boards 70, 72, 74 and 76 as shown in fig. 8 are laminated is used as a single-piece multilayer board by primary press molding under appropriate heating and pressing conditions, the protruded conductor directly under the via hole of one circuit board 70 located on the outermost side is melted to form a substantially circular conductor land on the surface of the insulating base material 10, and the conductor land is formed in the other circuit board 70 in a portion directly above the via hole of the conductor circuit 40.
In the case of the multilayer board 80, the circuit board 70 at the lowermost layer is connected to the conductive nails 64 or the conductive balls 66 at the conductive pads immediately below the via holes, and further connected to the connection terminals or the solder balls of the motherboard (not shown), and the circuit board 76 at the uppermost layer is connected to the conductive pads formed at a part of the conductive circuit 40, with the conductive bumps 62 formed thereon, and is connected to the solder balls 84 of the electronic component 82 such as LSI.
As shown by the dotted line in fig. 8, a solder resist 83 may be formed on the surfaces of the outermost circuit boards 70 and 76. At this time, a solder resist composition is applied, and after the coating is dried, a photolithographic mask having an opening is placed on the coating, and an opening exposing a solder pad portion is formed in the conductor circuit 40 by exposure and development, and the conductive bump 62, the conductive nail 64, or the conductive ball 66 is provided on the exposed solder pad portion.
In the above embodiment, the semiconductor device is constituted by the multilayer board 80 including the conductive flange, the conductive nail, and the conductive ball, and the electronic component 82 mounted on the multilayer board 80, and the semiconductor device may be constituted by the multilayer board 80 including such an electronic component and the motherboard on which the multilayer board is mounted as a whole.
Fig. 10 shows another semiconductor device, in which a chip capacitor 86 is connected and fixed to one circuit board 70 located on the outermost side of a multilayer board 80, and a reinforcing member 88 for preventing warpage is fixed along the outer periphery of the other circuit board 76.
In such a semiconductor device, the chip capacitor 86 is formed of a high dielectric constant material such as ceramic or barium titanate, and is electrically connected to a via hole located directly below the mounted electronic component, thereby reducing the loop inductance.
The reinforcing member 88 may be made of a glass epoxy composite material such as BT, FR4, and FR5, or a metal material such as copper, and prevents warping due to a difference in thermal expansion amount between the materials constituting the circuit board.
As shown in fig. 11, the outermost one of the circuit boards constituting the multilayer board 80 has a flange 62 formed on the conductor pad formed on the conductor circuit 40, and the other circuit board (here, the lowermost circuit board 70) is connected to the conductor pad formed on the conductor circuit 40 exposed from the opening 16 without filling the opening 16 provided in the insulating base material 10 with an electrolytic copper plating layer.
In this configuration, since the conductive pins 64 are surrounded by the insulating base member 10, it is not necessary to provide a solder resist.
In the above embodiment, it is preferable that a metal layer made of 'nickel-gold' is formed on each solder pad portion, and the thickness of the nickel layer is 1 to 7 μm and the thickness of the gold layer is 0.01 to 0.06 μm. This is because if the nickel layer is too thick, the resistance value increases, and if it is too thin, peeling is likely to occur. On the other hand, if the gold layer is too thick, the cost is high, and if it is too thin, the adhesion effect with the solder body is reduced.
A solder body is supplied to a metal layer made of nickel-gold provided on such a solder land portion, and a conductive bump is formed by melting and solidifying the solder body, or a conductive nail or a conductive ball is bonded to the solder land portion, thereby forming a multilayer circuit board.
As a method of supplying the solder body, a solder copying method or a printing method may be used.
Here, the solder transfer method is a method in which a solder foil is bonded to a preform, the solder foil is etched to leave only a portion corresponding to an opening, a solder pattern is formed as a solder carrier film, a solder having a size corresponding to the opening of a solder resist of a substrate is applied to the solder carrier film, the solder pattern is laminated to contact a pad, and the solder pattern is heated and transferred.
On the other hand, the printing method is a method in which a printing mask (metal mask) having openings at positions corresponding to pads is placed on a substrate, a solder paste is printed, and then heat treatment is performed, and tin-silver, tin-indium, tin-zinc, tin-bismuth alloy, or the like can be used as solder.
(D1) Formation of single-sidedbuild-up wiring layers
An embodiment in which a buildup wiring layer is formed on one surface of the multilayer board 60 formed by the steps (a) and (B) will be described. The illustration of the double-sided or single-sided circuit board constituting the multilayer board 60 is omitted entirely for the sake of simplicity (see fig. 12 (a)). (1) A roughened layer made of copper-nickel-phosphorus is formed on the surface of the conductor circuit 40 on one surface of the multilayer board 60 (see fig. 12 (b)).
The roughened layer 62 is formed by electroless plating. The electroless plating aqueous solution preferably has a composition in which the concentrations of copper ions, nickel ions and hypophosphorous acid ions are 2.2X 10-2～4.1×10-2mol/l、2.2×10-3～4.1×10-3mol/l、0.20～0.25mol/l。
Since the crystal structure of the deposited film in this range is needle-like, the fixing effect is excellent. The electroless plating aqueous solution may contain a complexing agent or an additive in addition to the compound.
As a method for forming the roughened layer, there is a method of forming a roughened surface by plating treatment with a copper-nickel-phosphorus needle alloy, oxidation-reduction treatment, or treatment of etching the copper surface along grain boundaries, as described above.
(2) Next, interlayer resin insulation layer 64 is formed on multilayer board 60 having rough layer 62 formed in (1) above (fig. 12 c).
The interlayer resin insulation layer 64 may be formed by applying a liquid resin having a viscosity adjusted in advance by curtain coating, roll coating, printing, or the like, by attaching a semi-cured B-stage resin film, or by pressing or heating the resin film.
As the resin for forming the interlayer insulating resin layer, at least one resin selected from the group consisting of a thermosetting resin, a thermoplastic resin, a photosensitive resin (ultraviolet curable resin, etc.), a resin obtained by acrylating a partially thermosetting resin, a resin composite of a thermosetting resin and a thermoplastic resin, and a resin composite of a photosensitive resin and a thermoplastic resin is preferably used. In addition, a curing agent, a reaction accelerator, a photoreaction recombination agent, an additive, a solvent, and the like may be contained.
As the thermosetting resin, epoxy resin, phenol resin, polyimide resin, bismaleimide resin, polyphenylene resin, polyolefin resin, fluorine resin, and the like can be used.
Examples of the epoxy resin include novolac type epoxy resins such as phenol novolac type and cresol novolac type, and alicyclic epoxy resins converted into dicyclopentadiene.
When the photosensitive resin is an acrylic resin or a thermosetting resin, methacrylic acid, acrylic acid or the like is reacted with a thermosetting group of the thermosetting resin to cause an acrylation reaction.
As the thermoplastic resin, phenoxy resin, Polyethersulfone (PES), Polysulfone (PSF), polyphenylene sulfide (PPS), polyphenylene ether sulfone (PPES), polyphenylene ether (PPE), Polyetherimide (PI), or the like can be used.
The resin composite may be a combination of a thermosetting resin and a thermoplastic resin, or a combination of a photosensitive resin and a thermoplastic resin.
As the combination of the thermosetting resin and the thermoplastic resin, there are combinations of a phenol resin and a polyether sulfone resin, a polyimide resin and a polysulfonic resin, an epoxy resin and a polyether sulfone resin, and an epoxy resin and a phenoxy resin.
As the combination of the photosensitive resin and the thermoplastic resin, there are a combination of an epoxy resin obtained by methacrylating a part of epoxy groups, a polyether sulfone resin, an acrylic resin and a phenoxy resin. The mixing ratio of the resin composite may be: the thermosetting resin (photosensitive resin)/thermoplastic resin is 95/5-50/50. This is because a high toughness value can be secured without impairing heat resistance.
The interlayer resin insulating layer may have a structure of 2 or more layers. That is, the resin layer may be composed of 2 different resin layers. For example, the filler component may be reduced to improve the insulation property, and the soluble filler may be immersed in an acid or an oxidizing agent in the upper layer to improve the adhesion of the electroless plating film. The thickness of the formed resin layer is preferably 20 to 70 μm. Particularly, it is more preferable that the thickness is 25 to 50 μm, because both the insulation property and the adhesion property of the plating film can be easily solved.
The resin film is formed by dispersing particles soluble in an acid or an oxidizing agent (hereinafter referred to as soluble particles) in a sparingly soluble resin (hereinafter referred to as a sparingly soluble resin). Furthermore, the definition of the term 'poorly soluble' as used herein is: when immersed in a solution formed from the same acid or oxidizing agent for the same time, a substance having a relatively high dissolution rate is referred to as "soluble" and a substance having a relatively low dissolution rate is referred to as "poorly soluble" for convenience.
Examples of the soluble particles include soluble resin particles to an acid or an oxidizing agent (hereinafter referred to as soluble resin particles), soluble inorganic particles to an acid or an oxidizing agent (hereinafter referred to as soluble inorganic particles), and soluble metal particles to an acid or an oxidizing agent (hereinafter referred to as soluble metal particles). These soluble particles may be used alone, or 2 or more kinds may be used in combination.
The shape of the soluble particles is not particularly limited, and examples thereof include a spherical shape and a crushed shape. In addition, the soluble particles preferably have the same shape. This is because a roughened surface having irregularities of uniform thickness can be formed.
The soluble particles preferably have an average particle diameter of 0.1 to 10 μm. In the range of particle size, 2 or more kinds of particles having different particle sizes may be contained. That is, soluble particles having an average particle diameter of 0.1 to 0.5 μm, soluble particles having an average particle diameter of 1 to 3 μm, and the like are contained. Therefore, a relatively complicated roughened surface can be formed, and the adhesion with the conductor circuit is good. In the present invention, the particle size of the soluble particle means the length of the longest part of the soluble particle.
The soluble resin particles are not particularly limited as long as they are dissolved at a higher rate than the poorly soluble resin when immersed in a solution of an acid or an oxidizing agent.
Specific examples of the soluble resin particles include particles made of an epoxy resin, a phenol resin, a polyimide resin, a polyphenylene resin, a polyolefin resin, a fluororesin, or the like, and may be made of any of these resins or a mixture of 2 or more resins.
As the soluble resin particles, resin particles made of rubber may be used. Examples of the rubber include polybutadiene rubber, various modified polybutadiene rubbers such as epoxy-modified polybutadiene rubber, urethane-modified polybutadiene rubber, and (meth) acrylonitrile-butadiene rubber containing a carboxyl group. By using these rubbers, the soluble particles are easily dissolved in an acid or an oxidizing agent. That is, when the soluble particles are dissolved using an acid, an acid other than a strong acid may be dissolved, and when the soluble particles are dissolved using an oxidizing agent, permanganic acid having a weak oxidizing power may be dissolved. Further, when chromic acid is used, it can be dissolved at a low concentration. Therefore, the acid and the oxidizing agent do not remain on the surface of the resin, and as described later, when a catalyst such as palladium chloride is added after the roughened surface is formed, there is no problem that the catalyst is not added or the catalyst is oxidized.
Examples of the soluble inorganic particles include particles formed of at least one compound selected from an aluminum compound, a calcium compound, a potassium compound, a magnesium compound, and a silicon compound.
Examples of the aluminum compound include alumina and aluminum hydroxide, examples of the calcium compound include calcium carbonate and calcium hydrogen hydride, examples of the potassium compound include potassium carbonate, examples of the magnesium compound include magnesium oxide, dolomite and basic magnesium carbonate, and examples of the silicon compound include silica and zeolite. These may be used alone or in combination of 2 or more.
Examples of the soluble metal particles include particles formed of at least one metal selected from copper, nickel, iron, zinc, lead, gold, silver, aluminum, magnesium, calcium, and silicon. In order to ensure insulation, the surface layer of these soluble metal particles may be coated with a resin or the like.
When 2 or more kinds of the above soluble particles are mixed and used, a combination of the 2 kinds of the soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. This is because: since the resin film has poor conductivity, the insulating property of the resin film can be secured, thermal expansion with the hardly soluble resin can be easily adjusted, and the interlayer resin insulating layer formed of the resin film is not cracked and is not peeled off from the conductor circuit.
When the roughened surface is formed on the interlayer resin insulating layer using an acid or an oxidizing agent, the poorly soluble resin is not particularly limited as long as it can retain the shape of the roughened surface, and examples thereof include thermosetting resins, thermoplastic resins, and composites thereof. Further, these resins may be photosensitive resins to which photosensitivity is imparted. By using a photosensitive resin, an opening for via hole can be formed in the interlayer resin insulating layer by exposure and development treatment.
Among them, a resin containing a thermosetting resin is preferable. Therefore, the shape of the roughened surface can be maintained even after the plating solution or various heat treatments.
Specific examples of the poorly soluble resin include epoxy resins, phenol resins, polyimide resins, polyphenylene resins, polyolefin resins, and fluorine resins. These resins may be used alone or in combination of 2 or more.
Further, an epoxy resin having 2 or more epoxy groups is preferable. Since the roughened surface can be formed and the heat resistance is good, the stress concentration of the metal layer does not occur even under the conditions of thermal cycle, and the metal layer is less likely to be peeled off.
Examples of the epoxy resin include cresol novolac type epoxy resins, bisphenol a type epoxy resins, bisphenol F type epoxy resins, phenol novolac type epoxy resins, alkylphenol novolac type epoxy resins, bisphenol F type epoxy resins, naphthalene type epoxy resins, dicyclopentadiene type epoxy resins, epoxy resins obtained by condensation products of phenols and aromatic aldehydes having a phenolic hydroxyl group, triglycidyl isocyanurate, and alicyclic epoxy resins. These may be used alone or in combination of 2 or more. This provides an epoxy resin having excellent heat resistance.
In the resin used in the present invention, it is preferable that the soluble particles are substantially uniformly dispersed in the poorly soluble resin because: the roughened surface can be formed to have irregularities of uniform thickness, and the adhesion of the metal layer of the conductor circuit formed thereon can be ensured even when a via hole or a through hole is formed in the resin film. In addition, a resin film containing soluble particles only in the surface layer portion where the roughened surface is formed may be used. Thus, the portions other than the surface portion of the resin film are not exposed to an acid or an oxidizing agent, and therefore, the insulating property between the conductor circuits can be ensured through the interlayer resin insulating layer.
In the resin film, the amount of the soluble particles dispersed in the hardly soluble resin is preferably 3 to 40% by weight of the resin film. If the amount of the soluble particles is less than 3%, a roughened surface having desired irregularities may not be formed, and if it exceeds 40%, the soluble particles may be dissolved into the deep part of the resin film when dissolved with an acid or an oxidizing agent, so that the interlayer resin insulating layer formed via the resin film may not maintain the insulation between the conductor circuits, and a short circuit may occur.
The resin film preferably contains a curing agent and other components in addition to the soluble particles and the poorly soluble resin.
Examples of the curing agent include imidazole-based curing agents, amine-based curing agents, guanidine-based curing agents, epoxy compounds of these curing agents, curing agents obtained by microencapsulating these curing agents, and organophosphine-based compounds such as triphenyl phosphine phosphite and tetraphenyl phosphonium tetraphenyl borate.
The content of the hardener is preferably 0.05 to 10% by weight of the resin film. If the content is less than 0.05%, the resin film is insufficiently cured, so that the acid or the oxidizing agent penetrates into the resin film to a high degree, which deteriorates the insulating property of the resin film. On the other hand, if the amount exceeds 10%, the resin composition is denatured by an excessive amount of the curing agent component, resulting in a decrease in reliability.
Examples of the other component include fillers such as inorganic compounds and resins that do not affect the formation of a roughened surface. Examples of the inorganic compound include silicon oxide, aluminum oxide, and dolomite, and examples of the resin include polyimide resin, polyacrylic resin, polyamideimide resin, polyphenylene resin, melamine resin (melanin), and olefin resin. By including these fillers, the conformability of thermal expansion coefficient, heat resistance, chemical resistance, and the like can be improved, and the performance of the printed wiring board can be improved.
The resin film may contain a solvent. Examples of the solvent include ketones such as acetone, methyl ethyl ketone and cyclohexanone, ethyl acetate, butyl acetate, cellosolve acetate, and aromatic hydrocarbons such as toluene and xylene. These may be used alone or in combination of 2 or more.
In particular, in the present invention, as an interlayer resin insulating material for forming the via hole 70 described later, an adhesive for electroless plating using a composite of a thermosetting resin and a thermoplastic resin as a resin binder is preferably used. The resin film in a semi-cured state may be laminated and then used.
(3) After the electroless plating adhesive formed in (2) is dried, an opening 65 for via formation is provided (fig. 12 d).
In the case of a photosensitive resin, the opening 65 for forming a via hole is provided in the adhesive layer 64 by performing thermal curing after exposure and development, and in the case of a thermosetting resin, the opening is formed by performing laser processing after thermal curing.
(4) The epoxy resin particles existing on the surface of the cured adhesive layer 64 are decomposed or dissolved by an acid or an oxidizing agent, and the surface of the adhesive layer is roughened to have a pre-process roughened surface 66 (fig. 12 (e)).
The acid is an organic acid such as phosphoric acid, hydrochloric acid, sulfuric acid, formic acid, acetic acid, or the like, but an organic acid is preferably used. This is because the metal conductor layer exposed from the via hole is less likely to be corroded in the roughening treatment.
On the other hand, as the oxidizing agent, chromic acid, permanganic acid (potassium permanganate, etc.) is preferably used.
(5) Next, catalyst nuclei are provided to the roughened layer 66 on the surface of the adhesive layer 64.
It is preferable to use noble metal ions, noble metal colloids, or the like for the administration of the catalyst core, and palladium chloride or palladium colloids are generally used. Further, it is preferable to perform a heat treatment for fixing the catalyst core. Palladium is preferred as such a catalyst core.
(6) Further, electroless plating is performed on the surface of the adhesive layer 64 (for electroless plating), thereby forming an electroless plating film 67 on the entire roughened surface (fig. 12 (f)). In this case, the thickness of the electroless plating film 67 is preferably in the range of 0.1 to 5 μm, more preferably 0.5 to 3 μm.
Next, a plating resist 68 is formed on the electroless plating film 67 (fig. 13 (a)). As the composition of the plating resist, a composition comprising an acrylic ester of a cresol novolak type epoxy resin or a phenol novolak type epoxy resin and an imidazole hardener is preferably used, but other commercially available dry films may be used.
(7) Further, the portion of the electroless plating film 67 where the plating resist is not formed is subjected to electrolytic plating to form a conductor layer on which an upper conductor circuit 72 is to be formed, and the electrolytic plating film 69 is filled in the opening 62 to form a via hole 70 (fig. 12 (b)).
In this case, the thickness of the electrolytic plating film 69 exposed from the outside of the opening 5 is preferably 5 to 30 μm. Here, it is preferable to use electrolytic copper plating as the electrolytic plating.
(8) After the plating resist 68 is removed, the electroless plating film under the plating resist is dissolved and removed using a mixed solution of sulfuric acid and hydrogen peroxide or an etchant such as sodium superphosphate or ammonium superphosphate to form the isolated upper conductor circuit 72 and the filled via 70.
(9) Next, a roughened layer 74 is formed on the surface of the upper conductor circuit 72.
As a method of forming the roughened layer, there are etching treatment, polishing treatment, oxidation-reduction treatment, and plating treatment.
Among these treatments, the oxidation bath for the redox treatment consisted of NaOH (20g/l), NaClO2(50g/l)、NaPO4(15.0g/l) and a reduction bath consisting of NaOH (2.7g/l) and NaBH4(1.0 g/l).
Further, a roughened layer formed of a copper-nickel alloy layer is deposited by an electroless plating process.
As an electroless plating solution for the alloy, it is preferable to use a plating bath comprising 1 to 40g/l of copper sulfate, 0.1 to 6.0g/l of nickel sulfate, 10 to 20g/l of citric acid, 10 to 100g/l of hypophosphite, 10 to 40g/l of boric acid, and 0.01 to 10g/l of a surfactant.
Further, the surface of the roughened layer is covered with a metal or a regular metal layer having an ionization tendency of titanium or less larger than that of copper.
When the metal is tin, tin borofluoride-thiourea or tin chloride-thiourea solution is used. In this case, a Cu-Sn substitution reaction is used to form a Sn layer of about 0.1 to 2 μm. In the case of a noble metal, a method such as sputtering or vapor deposition can be used.
(10) Next, an electroless plating adhesive layer 76 is formed as an interlayer resin insulating layer on the substrate.
(11) Further, the above-described steps (3) to (9) are repeated, another via hole (not shown) is provided directly above the via hole 70, the upper layer conductor circuit 82 is provided outside the upper layer conductor circuit 82 (see fig. 13 c), and the surface of the upper layer conductor circuit 82 and the surface including the inner wall of the via hole (not shown) are roughened to form a roughened layer 84.
(12) Next, a solder resist composition is applied to cover the outermost surface of the build-up wiring layer thus obtained, and after the coating film is dried, a photomask for drawing an opening is placed on the coating film, and exposure and development are performed, whereby an opening 91 is formed in the conductor layer so as to expose a conductor portion (including a conductor pad and a via) to be a solder pad (see fig. 14 (a)).
Here, the diameter of the exposed opening 91 may be larger than the diameter of the conductor portion to be the solder pad, or the conductor portion may be completely exposed. On the contrary, the aperture of the opening 91 may be smaller than the diameter of the conductor portion to be the solder pad, and the periphery of the conductor portion may be covered with the solder resist 90. In this case, the solder resist 90 can suppress the portion to be the solder pad, and finally can prevent the solder pad from peeling.
(13) Further, a metal layer made of nickel-gold is formed on the conductor portion exposed from the opening 91 of the solder resist 90, and a solder pad is formed.
The nickel layer 92 is preferably 1 to 7 μm, and the gold layer is preferably 0.01 to 0.06. mu.m. This is because: if the nickel layer 92 is too thick, the resistance value increases, and if it is too thin, peeling tends to occur. On the other hand, if the gold layer 94 is too thick, the cost increases, and if it is too thin, the adhesion effect with the solder body decreases.
(14) Further, a multilayer circuit board is manufactured by supplying a solder body to the conductor circuit (solder pad) exposed from an opening 91 (an opening located above) formed in one of the outermost solder resist layers of the build-up wiring layer formed on one surface of the multilayer board to form a solder flange 96, and supplying a solder body to the conductor circuit (solder pad) exposed from the surface on the side where the build-up wiring layer of the multilayer board is not formed to form a T-shaped nail 98 or a solder ball 100 (see fig. 14 (b)).
As a method of supplying the solder body, a solder copying method or a printing method can be used.
Here, the solder transfer method is a method of bonding a solder foil to a preform, etching the solder foil to leave only a portion corresponding to an opening portion, forming a solder pattern as a solder-bearing film, applying a flux to the opening portion of a solder resist film of a substrate, laminating the solder-bearing film, bringing the solder pattern into contact with a land, heating the solder pattern, and transferring the solder pattern. On the other hand, the printing method is a method in which a printing mask (metal mask) having through holes formed in positions corresponding to pads is placed on a substrate, and a solder paste is printed and then subjected to a heating process. The solder may be tin-silver, tin-indium, tin-zinc, tin-bismuth, or the like.
Further, as the solder body forming the conductive flange 96, tin/lead solder (melting point 183 ℃) or tin/silver solder (melting point 220 ℃) having a low melting point is preferably used, and as the solder body connecting the conductive nail 98 and the conductive ball 100, tin/antimony solder, tin/silver solder and tin/silver/copper solder having a high melting point of 230 ℃ to 270 ℃ are preferably used.
(D2) Formation of two-sided build-up wiring layers
In the embodiment in which build-up wiring layers are formed on both surfaces of the multilayer core board 60 formed in the above-described steps (a) and (B), after the processes in the single-sided build-up wiring layer forming steps (1) to (12) described above (D1) (see fig. 17(a)), the solder pads 95 including the nickel layer 92 and the gold layer 94 are formed on a part of the outermost conductor circuits 82 of the build-up wiring layers, whereby a multilayer circuit board suitable foruse as a motherboard can be manufactured (see fig. 17 (B)).
Further, a multilayer circuit board suitable for use as a package substrate on which electronic components can be mounted at high density can be manufactured by supplying solder to the solder pad 95 formed on the outermost conductor circuit 82 constituting one of the two-sided build-up wiring layers to form the solder bump 96, and supplying solder to the solder pad 95 formed on the outermost conductor circuit 82 constituting the other build-up wiring layer to form the T-peg 98 or the solder ball 100 (see fig. 18).
Next, examples are explained.
[ examples]A method for producing a compound
(example 1)
(1) First, a double-sided circuit board constituting a multilayer board is manufactured. The circuit board uses a single-sided copper-clad laminate obtained by laminating a prepreg made of a B-stage glass cloth impregnated with an epoxy resin and a copper foil and then heating and pressing the laminate as a starting material.
The insulating base material 10 was 75 μm thick, the copper foil 12 was 12 μm thick, the laminate plate had adhesive layers of 10 μm thick on the copper foil forming surface and the reverse surface, and the laminate film itself was a PET film 14 of 12 μm thick.
(2) Next, carbon dioxide laser irradiation is performed on the PET film 14 to form a via hole forming opening 16 extending through the PET film 14 and the insulating base material 10 to the copper foil 12, and further, ultraviolet laser irradiation is performed to remove the inside of the opening 16.
In this embodiment, the formation of the via hole opening was carried out by irradiating a glass cloth epoxy resin substrate having a substrate thickness of 75 μm, in which a PETfilm having a thickness of 22 μm as a whole was laminated on a resin surface, with a laser beam from the PET film side by a mask image method using a high peak short pulse oscillation type carbon dioxide gas laser processing machine made by Mitsubishi motor, and a via hole opening having a diameter of 150 μm was formed at a speed of 100 holes.
Further, the ultraviolet laser irradiation apparatus using YAG3 subharmonic for the cleaning treatment uses GT605LDX manufactured by mitsubishi electric corporation, and the laser irradiation conditions for the cleaning treatment are as follows: the oscillation frequency was 5kHz, the pulse energy was 0.8mJ, and the number of impacts was 10.
(3) The substrate after the cleaning process is subjected to electrolytic copper plating using the copper foil 12 as a plating guide, leaving a slight gap above the opening 16, and the opening 16 is filled with an electrolytic copper plating 18 to form a via hole 20.
(4) Further, the conductive paste 22 is filled in the copper plating layer 18 filling the opening 16 using the PET film 14 as a printing mask, and a projecting conductor 24 projecting from the surface of the insulating base material 10 by approximately the thickness of the PET film 14 is formed.
(5) Next, after peeling the PET film 14 from the surface of the insulating base material 10, the entire surface on the side of the projected conductor 24 was coated with an epoxy adhesive and dried at100 ℃ for 30 minutes to form an adhesive layer 26 having a thickness of 20 μm.
(6) Heating at 180 deg.C for 70 min under 2MPa and vacuum degree of 2.5 × 103Under Pa, a copper foil having a thickness of 12 μm was hot-pressed on the adhesive layer 26 formed in (5).
(7) Then, the copper foils 12 and 28 on both sides of the substrate are subjected to an appropriateetching process to form conductor circuits 30 and 32 (including via lands), thereby producing a double-sided circuit board 34.
(8) Next, a single-sided circuit board for build-up is produced. This circuit board is a single-sided copper-clad laminate as a starting material, like the double-sided circuit board 34.
First, the copper foil on the insulating base 10 is etched as appropriate to form the conductor circuit 40, and the PET film 14 is laminated on the surface of the insulating base 10 opposite to the conductor circuit 40.
(9) Then, the conductor circuit 40 is formed on one surface of the insulating base 10 by the processing in the above-described steps (2) to (5), the electrolytic copper plating 18 is filled in the opening from the other surface of the insulating base 10 to the conductor circuit 40, the projecting conductor 44 is formed on the electrolytic copper plating 18, and the epoxy resin adhesive 46 is applied to the surface of the insulating base 10 including the projecting conductor 44.
This epoxy resin adhesive was subjected to a predetermined setting treatment to form an adhesive layer for multilayering, and a single-sided circuit board 50 having a thickness of 3 rd was produced.
(10) The multilayer board 60 is produced by stacking 1 double-sided circuit board 34 and 3 single-sided circuit boards 50, 52, 54 formed by the above processes (1) to (9) at predetermined positions as shown in fig. 3, laminating them at 180 ℃ by vacuum thermocompression, and then pressing them together.
(11) In the outermost circuit board constituting the multilayer circuit board 60, the T-nails 64 and the solder balls 66 are connected to the conductor circuit 40 of one circuit board 50 (lower substrate) by using tin/antimony solder having a melting temperature of about 230 ℃, and a tin/lead solder having a melting temperature of about 183 ℃ is supplied to the conductor circuit 40 of the other circuit board 52 (upper substrate) to form a solder flange 62, thereby producing a multilayer circuit board, and the electronic component 82 is placed on the upper circuit board of the multilayer circuit board, and is softened around the melting point of the tin/lead solder, and the solder balls 84 of the electronic component 82 are melted and fixed to the solder flange 62, thereby producing a semiconductor device including the multilayer circuit board and the electronic component.
(example 2)
A multilayer board and a semiconductor device were manufactured in the same manner as in embodiment 1 except that T-nails or solder balls were bonded to solder bumps formed on the solder bumps formed by thermally pressing the protruded conductors exposed from the outside of the other circuit board, while the conductor circuit (conductor pad) of the outermost one of the circuit boards was formed as a multilayer board by laminating 4 layers of single-sided circuit boards at predetermined positions shown in fig. 1 and thermally pressing them together.
(example 3)
As shown in fig. 2, a multilayer circuit board and a semiconductor device were manufactured in the same manner as in embodiment 1 except that one circuit board located on the outermost side among the 4-layer single-sided circuit boards had a solder bump formed on a solder land on which a conductor circuit was formed, and the other circuit board located on the outermost side was connected to a T-nail by supplying a solder to a hanzi pad formed of a conductor circuit exposed from an opening provided in an insulating base material without filling an electrolytic copper plating layer.
(example 4)
As shown in fig. 2, a multilayer circuit board and a semiconductor device were manufactured in the same manner as in embodiment 3, except that a solder resist was provided on the outermost front and rear circuit boards, and a solder bump was formed on the solder pad exposed from the opening formed in the solder resist.
(embodiment 5)
As shown in fig. 1, a multilayer circuit board and a semiconductor device were manufactured in the same manner as in embodiment 3, except that a solder resist was provided on the outermost front and rear circuit boards, and a solder bump was formed on a solder pad exposed from an opening formed in the solder resist.
(embodiment 6)
(1) A multilayer core board having a land diameter of 250 μm, a via hole diameter of 150 μm, a conductor layer thickness of 12 μm, and an insulating layer thickness of 75 μm was produced by processing in the steps (1) to (10) of example 1.
(2) Next, the multilayer core board 60 (see fig. 15(a)) having the conductor circuits 40 formed on both surfaces thereof was immersed in an electroless plating solution having a pH of 9 and composed of 8g/l copper sulfate, 0.6g/l nickel sulfate, 15g/l citric acid, 29g/l sodium hypophosphite, 31g/l boric acid, and 0.1g/l surfactant, and a roughened layer 62 composed of 3 μm copper-nickel-phosphorus was formed on the surface of the conductor circuit 40. Next, the substrate was washed with water and immersed in an electroless tin-substituted plating bath containing 0.1mol/l tin borofluoride-1.0 mol/l thiourea solution at 50 ℃ for 1 hour to form a 0.3 μm tin layer on the surface of the roughened layer 63 (see FIG. 15(b), the tin layer is not shown)
(3) The following compositions ① to ③ were mixed and stirred to prepare an adhesive for electroless plating.
① A25% acrylic compound (solid content 80%)of a cresol novolak type epoxy resin (molecular weight 2500, made by Nippon chemical Co., Ltd.), 4% by weight of a photosensitive monomer (ALLONIX M315, made by Toyo Seiya Co., Ltd.), 0.5% by weight of an antifoaming agent (S-65, made by SANNOPCO Co., Ltd.) and 3.6% by weight of NMP were mixed with stirring.
② polyether sulfone (PES) 8 weight parts and epoxy resin particles 7.245 weight parts and having an average particle diameter of 0.5 μm (POLYMERPOL, manufactured by Sanyo chemical Co., Ltd.) were mixed, and NMP 20 weight parts was added thereto and stirred and mixed.
③ A2 part by weight imidazole hardener (2E 4MZ-CN, manufactured by Siguo), a 2 part by weight photoinitiator (IRGACURE I-907, manufactured by Chiba geigie), a 0.2 part by weight photosensitizer (DETX-S, manufactured by Nippon Chemicals) and a 1.5 part by weight NMP were mixed together with stirring.
(4) The adhesive for electroless plating prepared in the above (3) was applied to the substrate 60 subjected to the above (2) (see FIG. 15(c)), and a photomask having a black circle of 85 μm diameter was adhered and printed on both surfaces of the substrate 60 on which the adhesive layer was formed after drying, and the resultant was usedUltra-high pressure mercury lamp at 500mJ/cm2Exposure is performed. The via opening 65 of diameter 85 μm was formed on the adhesive layer by spraying and developing it using a DMDG (diethylene glycol dimethyl ether) solution. Further, the discharge lamp was operated at 500mJ/cm using an extra-high pressure mercury lamp2The substrate was exposed to light at100 ℃ for 1 hour, and then subjected to heat treatment at 150 ℃ for 5 hours to form an interlayer insulating material layer 64 (adhesive layer) having a thickness of 35 μm and having openings with a dimensional accuracy equivalent to the high accuracy of the photomask (fig. 15 (d)). Further, a part of the tin plating layer is exposed on the opening 65 where the via hole is formed.
(5) The substrate having the via hole forming opening 65 formed therein is immersed in chromic acid for 20 minutes to melt and remove epoxy resin particles present on the surface of the adhesive layer, and the surface of the adhesive layer 64 is roughened to a depth of about 1 to 5 μm Rmax to form a roughened surface 66, and then immersed in a neutral solution (manufactured by Siplay corporation) and washed with water.
(6) By adding a palladium catalyst (made by ATOTEK) to the roughened layer 66 (roughened depth 3.5 μm) on the adhesive layer surface, catalyst nuclei are provided on the adhesive layer 64 and the surface of the via hole forming opening 65.
(7) The substrate was immersed in an electroless copper plating bath having the following composition to form an electroless copper plating film 67 having a thickness of 0.6 μm over the entire roughened surface (see fig. 15 (f)). At this time, since the electroless copper plating film 67 is thin, irregularities of the roughened surface 66 of the adhesive layer 64 are observed on the surface of the film.
[ electroless plating aqueous solution]
NiSO40.003mol/l
Tartaric acid 0.20mol/l
Copper sulfate 0.03mol/l
HCHO 0.05mol/l
NaOH 0.10mol/l
α, α' -bipyridine 40mg/l
Polyethylene glycol (PEG) 0.1g/l
[ electroless plating conditions]
Liquid temperature of 33 deg.C
(8) A commercially available photosensitive dry film was attached to the electroless copper plating film 67 formed in the above (7), and the resultant film was covered with a mask at a thickness of 100mJ/cm2The film was exposed to light and developed with 0.8% sodium carbonate to form a plating resist 68 having a thickness of 15 μm (see FIG. 16 (a)).
(9) Next, the portion where the plating resist was not formed was subjected to electrolytic plating under the following conditions to form an electrolytic plating film 69 having a thickness of 20 μm, and a conductor layer to be formed with the upper conductor circuit 72 was provided, and the opening portion was filled with the plating film 69 to form a via hole 70 (see fig. 16B).
[ electrolytic plating aqueous solution]
CuSO4·5H2O 60g/l
Leveling agent (HL, made by ATOTEK) 40ml/l
190g/l sulfuric acid
Gloss agent (UL, manufactured by ATOTEK) 0.5ml/l
Chloride ion 40ppm
[ electrolytic plating conditions]
Foaming at 3.0 l/min
Current density 0.5A/dm2
Set current value of 0.18A
Plating time 130 minutes
(10) After the plating resist 68 is peeled off and removed, the electroless plating film 67 under the plating film is dissolved and removed by using a corrosive solution such as a mixture of sulfuric acid and hydrogen peroxide, sodium superphosphate, ammonium superphosphate, or the like, to form an upper conductor circuit 72 having a thickness of 20 μm and an L/S of 25 μm/25 μm formed of the electroless plating film 67 and an electrolytic copper plating film. At this time, the via surfaceis flat, and the conductor circuit surface and the via surface are on the same level.
(11) As in the case of (2) above, the roughened layer 84 is formed on the substrate, and the steps (3) to (10) are repeated to form the upper interlayer resin insulation layer 76 and the conductor circuit 82 (including the via 80), and to form the buildup wiring layers on both surfaces of the multilayer board 60.
Here, although roughened layer 84 made of copper-nickel is provided on the surface of conductor circuit 82, no replacement plating layer is formed on the surface of roughened layer 84.
(12) On the other hand, 46.67 parts by weight of a photosensitive oligomer (molecular weight 4000) obtained by acrylating 50% epoxy group of a cresol novolak type epoxy resin (manufactured by chemical Co., Ltd.) dissolved in 60% by weight of DMDG, 14.121 parts by weight of a bisphenol A type epoxy resin (EPICOAT 1001 manufactured by YUKA SHELL, manufactured by chemical Co., Ltd.), 1.6 parts by weight of an imidazole curing agent (manufactured by chemical Co., Ltd., 2E4MZ-CN), 1.5 parts by weight of a polyvalent acrylic monomer (manufactured by chemical Co., Ltd., R604) as a photosensitive monomer, 30 parts by weight of the same polyvalent acrylic monomer (manufactured by Co., Ltd., DPE6A), 0.36 parts by weight of a leveling agent (manufactured by chemical Co., Ltd., POLYFLOW No.75) formed of an acrylate polymer were mixed, and 20 parts by weight of benzophenone (manufactured by Kenyaku chemical Co., Ltd.) and 0.2 parts by weight of an EAB (manufactured by chemical Co., EAB ケ) as a photo sensitizer were added to the mixture, further, DMDG (diethylene glycol dimethyl ether) was added in an amount of 10 parts by weight to obtain a solder resist composition having a viscosity adjusted to 1.4. + -. 0.3 pas at 25 ℃.
The viscosity was measured by using a type B viscometer (Tokyo counter, model DVL-B), and at 60rpm, a rotor No.4 was used, and at 6rpm, a rotor No.3 was used.
(13) The solder resist composition obtained in (12) above was coated to a thickness of 20 μm on both sides of the build-up wiring layer obtained in (11) above. Then, after drying at 70 ℃ for 30 minutes, a 5mm thick soda lime glass plate with a chromium layer painted with a circular pattern (mask pattern) of a solder resist opening was brought into close contact with the solder resist on the side where the chromium layer was formed, and the thickness was 1000mJ/cm2Is exposed to light and subjected to DMTG development treatment. Further, the heat treatment was carried out under the conditions of 80 ℃ for 1 hour, 100 ℃ for 1 hour, 120 ℃ for 1 hour, and 150 ℃ for 3 hours, to form a solder resist layer 90 (20 μm thick) having an opening (200 μm in diameter) in the solder pad portion.
(14) Next, the substrate on which the solder resist layer 90 was formed was immersed for 20 minutes in an electroless nickel plating solution having a pH of 5 containing 30g/l of nickel chloride, 10g/l of sodium hypophosphite, and 10g/l of sodium chromate, to form a nickel plating layer 92 having a thickness of 5 μm in the opening. Further, the substrate was immersed in an electroless gold plating solution containing 2g/l of gold potassium cyanide, 75g/l of ammonia chloride, 50g/l of sodium chromate, and 10g/l of sodium hypophosphite at 93 ℃ for 23 seconds to form a 0.03 μm gold plating layer 94 on the nickel plating layer 92.
Thus, a solder land 95 including the nickel plating layer 92 and the gold plating layer 94 is formed on the upper layer conductor circuit 82, and a multilayer circuit board suitable for a 3-layer single-sided motherboard and a 6-layer double-sided motherboard is manufactured (see fig. 17 (b)).
In the multilayer circuit board manufactured in this way, the vialands of the multilayer core board can be formed in a circular shape, and the land indirection can be about 600 μm, so that the vias can be densely formed, and the density of the vias can be easily increased. Further, since the number of via holes in the multilayer core board can be increased, electrical connection between the conductor circuit in the multilayer core board and the conductor circuit in the build-up wiring layer can be sufficiently ensured.
Further, the solder pads 95 provided on the outermost side of the build-up wiring layer are connected to conductive balls (solder balls) of a package substrate on which electronic components including semiconductor chips such as LSI are mounted, and therefore, the mounting of the package substrate is facilitated.
(example 7)
A solder bump 96 was formed on a solder land 95 formed on one of the outermost upper conductor circuits 82 of the multilayer circuit board manufactured in example 6, and a T-shaped nail 98 and a solder ball 100 were formed on a solder land 95 formed on the other outermost upper conductor circuit 82, thereby manufacturing a multilayer circuit board suitable for a package substrate (see fig. 18).
In the multilayer circuit board manufactured in this way, the electronic components such as LSI chips are connected to the solder bumps 96 disposed on the gold plating layers 94 (solder pads) exposed from the openings of the solder resist layers 90 provided above the build-up wiring layers, and the electronic components are connected to the connection terminals or the like on the motherboard via the conductive nails 98 or the conductive balls 100 disposed on the gold plating layers 94 (solder pads) exposed from the openings of the solder resist layers 90 provided below the build-up wiring layers.
(example 8)
Amultilayer circuit board was produced in the same manner as in example 6, except that the non-through hole for via formation in the double-sided circuit board and the single-sided circuit board constituting the multilayer board was filled with a conductive paste to form a via, and the via was filled with a conductive paste in the same step as the via formation to form a protruded conductor.
(example 9)
A multilayer circuit board was produced in the same manner as in example 6, except that an interlayer resin insulating layer was formed by hot pressing an epoxy resin film having a thickness of 20 μm, a via hole forming opening having a diameter of 60 μm was formed by irradiating carbon dioxide gas laser, and the surface of the interlayer resin insulating layer including the inner wall of the opening was roughened with a permanganic acid solution.
The epoxy resin film is preferably a resin composite with a phenoxy resin, and contains particles for forming a roughened layer.
(example 10)
A multilayer circuit board was produced in the same manner as in example 9, except that the through-holes for via formation in the double-sided circuit board and the single-sided circuit board constituting the multilayer core board were filled with a conductive paste to form via holes, and the via holes were filled with a conductive paste in the same step as the via hole formation to form projecting conductors.
(example 11)
A multilayer circuit board was produced in the same manner as in example 6 except that an interlayer resin insulating layer was formed by hot pressing a 20 μm thick polyolefin resin film, a via hole forming opening having a diameter of 60 μm was formed by irradiating a carbon dioxide laser beam, and then a copper sputtered film or a copper-nickelsputtered film having a thickness of 0.1 μm was formed on the surface of the interlayer resin insulating layer including the inner wall surface of the opening by a sputtering method without roughening treatment, instead of forming an electroless plating film.
(example 12)
A multilayer circuit board was produced in the same manner as in example 11 except that the through-holes for via formation in the double-sided circuit board and the single-sided circuit board constituting the multilayer core board were filled with a conductive paste to form via holes, and the via holes were filled with a conductive paste in the same step as the via hole formation to form projecting conductors.
(example 13)
(1) The processing was performed in the steps (1) to (10) of example 1 to produce a multilayer core board 60 having an L/S of 75 μm/75 μm, a land diameter of 250 μm, a via hole diameter of 150 μm, a conductor layer thickness of 12 μm, and an insulating layer thickness of 75 μm.
(2) Next, the processes of (2) to (14) of example 6 were performed on one surface of the multilayer core board 60 (see fig. 12(a)) having the conductor circuits 40 formed on both surfaces thereof, so that a build-up wiring layer was formed on one surface of the multilayer core board 60, and solder pads 95 including the nickel plating layer 92 and the gold plating layer 94 were formed, and the solder pads 95 were exposed from the openings 91 covering the solder resist 90 on the upper conductor circuit 82.
(3) A solder bump 96 is formed on the solder land 95, and a T-shaped nail 98 or a solder ball 100 is arranged on the conductor circuit 40 of the multilayer board 60 on which the build-up wiring layer is not formed, thereby producing a single-sided 3-layer multilayer circuit board suitable for a package substrate (see fig. 14 (b)).
(example 14)
A multilayer circuit board was produced in the same manner as in example 13, except that the non-through hole for via formation in the double-sided circuit board and the single-sided circuit board constituting the multilayer board was filled with a conductive paste to form a via, and the via was filled with a conductive paste in the same step as the via formation to form a bump conductor.
(example 15)
A multilayer circuit board was produced in the same manner as in example 13, except that an interlayer resin insulating layer was formed by hot pressing an epoxy resin film having a thickness of 20 μm, a via hole forming opening having a diameter of 60 μm was formed by irradiating a carbon dioxide gas laser beam, and the surface of the interlayer resin insulating layer including the inner wall surface of the opening was roughened with a permanganic acid solution.
The epoxy resin film is preferably a resin composite with a phenoxy resin, and contains particles for forming a roughened layer.
(example 16)
A multilayer circuit board was produced in the same manner as in example 15 except that the through-holes for via formation in the double-sided circuit board and the single-sided circuit board constituting the multilayer core board were filled with a conductive paste to form vias, and the vias were filled with a conductive paste in the same step as the formation of the vias to form projecting conductors.
(example 17)
A multilayer circuit board was produced in the same manner as in example 13 except that an interlayer resin insulating layer was formed by hot pressing a 20 μm thick polyolefin resin thin film, a via hole forming opening having a diameter of 60 μm was formed by irradiating a carbon dioxide laser beam, and a copper sputtered film or a copper-nickel sputtered film having a thickness of 0.1 μm was formed on the surface of the interlayer resin insulating layer including the inner wall surface of the opening by a sputtering method without roughening treatment, instead of forming an electroless plating film.
(example 18)
A multilayer circuit board was produced in the same manner as in example 17 except that the through-holes for via formation in the double-sided circuit board and the single-sided circuit board constituting the multilayer core board were filled with a conductive paste to form via holes, and the via holes were filled with a conductive paste in the same step as the via hole formation to form projecting conductors.
Comparative example
(1) An insulating substrate comprising a copper clad laminate having a thickness of 0.8 μm on both sides was used as a core substrate, a through hole having a diameter of 300 μm was drilled in the core substrate by a drill, and then electroless plating and electrolytic plating were performed to form a conductor layer including the through hole, a roughened layer was provided on the entire surface of the conductor layer including the through hole, and a non-conductive filling material for filling the through hole was filled in the through hole and dried to harden the same.
(2) Next, the filling material exposed from the through hole is removed and planarized, and the surface is subjected to electroless plating and electrolytic plating to form a thick plating layer, thereby forming a conductor circuit and a portion to be a conductor layer covering the filling material filling the through hole.
(3) An etching resist layer is formed on the surface of a substrate where a conductor circuit and a conductor layer coveringa filler for filling a via hole are formed, a plating film in a portion where the etching resist layer is not formed is removed by etching, and the etching resist layer is further removed by peeling, thereby forming an isolated conductor circuit and a conductor layer covering a filler.
Further, a multilayer circuit board was produced in the same steps as in (2) to (14) of example 4.
In examples 1 to 5, the results of examining the wiring length, the number of land formations and the total land area from an electronic component such as an LSI chip to a solder bump, BGA (ball grid array) or PGA (pin grid array) revealed that: compared with the prior printed circuit board, the wiring length is 8/10-1/2, the number of formed welding areas is 1.5-2.0 times, the total area of the welding areas is 2/3-8/10, high-density wiring can be realized, and the insulativity of the packaging bottom plate can be further improved in embodiment 4 and embodiment 5.
In examples 6 to 18, the wiring length from an electronic component such as an LSI chip to a solder bump, BGA (ball grid array) or PGA (pin grid array), and the number of solder land formation at the core were examined, and as a resultShows that: compared with the comparative example, the wiring length can be shortened by 10 to 25%, and the unit area (cm)2) The number of the formed core welding areas can be increased by 10-30%, and no bad influence on the electrical characteristics and the reliability is found.
Possibility of industrial utilization
As described above, according to the multilayer circuit board of the present invention, the single-sided or double-sided circuit board having the conductor circuit on one side or both sides of the hard insulating base material and having the via hole formed by filling the fine opening formed by irradiating the laser beam from the side opposite to the conductor circuit forming side with the conductive material is used as a basic configuration, and the multilayer board formed by appropriately combining and laminating them and thermally pressing them together can greatly improve the wiring density in the substrate, and can sufficiently ensure the electrical connection between the circuit boards by filling the via hole unlike the conventional through hole, and therefore, can be suitably used as a package substrate for mounting an electronic component such as an LSI chip.
Furthermore, a multilayer circuit board having such a multilayer board as a core and built-up wiring layers provided on one or both surfaces of the multilayer core board can be used not only as a package substrate but also as a motherboard for mounting the package substrate.
The structure in which the conductive flange is formed on one circuit board on the outermost side of the multilayer circuit board and the conductive nail or the conductive ball is arranged on the other circuit board on the outermost side is suitable for the package substrate, and the conductive flange, the conductive nail or the conductive ball for electrically connecting the electronic component and the motherboard can be arranged at high density, so that high-density wiring and high-density mounting of the electronic component can be realized. Further, since the stress is also relaxed, the wiring is prevented from being warped and the T-pin and the conductive bump can be ensured to be flat.

Claims (21)

1. A multilayer circuit board formed by laminating a plurality of circuit boards each having a conductor circuit on one or both surfaces of an insulating hard substrate and having a via hole formed by filling a conductive material into an opening penetrating the insulating hard substrate and extending to the conductor circuit with an adhesive and thermally pressing the laminated circuit boards together, characterized in that:
in the laminated circuit boards, a conductive flange is formed on the surface of one circuit board located on the outermost side, the conductive flange being located directly above the via hole and electrically connected to the via hole, and a conductive pin or a conductive ball is arranged on the surface of the other circuit board located on the outermost side, the conductive pin or the conductive ball being located directly above the via hole and electrically connected to the via hole.
2. A multilayer circuit board formed by laminating a plurality of circuit boards each having a conductor circuit on one surface of an insulating hard substrate and having a via hole formed by filling a conductive material into an opening penetrating the insulating hard substrate and extending to the conductor circuit, and a single-sided circuit board each having a conductor circuit on one surface of an insulating hard substrate and having an opening penetrating the insulating hard substrate and extending to the conductor circuit, together by an adhesive, and thermally pressing the laminated circuit boards together, characterized in that:
in the laminated circuit boards, a conductive flange is formed on the surface of one circuit board located on the outermost side, the conductive flange being located directly above the via hole and electrically connected to the via hole, and a conductive pin or ball electrically connected to a conductor circuit of the circuit board is arranged in an opening of the other circuit board located on the outermost side.
3. The multilayer circuit board of claim 1, wherein: a solder resist layeris provided on the surface of one circuit board located on the outermost side of the plurality of circuit boards to cover the conductor circuit, a conductive flange is formed directly above the via hole to be connected to the conductor layer or via hole exposed from the opening formed in the solder resist layer, a solder resist layer is also provided on the surface of the other circuit board located on the outermost side to cover the conductor circuit, and a conductive pin or conductive ball is provided directly above the via hole to be connected to the conductor layer or via hole exposed from the opening formed in the solder resist layer.
4. The multilayer circuit board according to claim 1 or 2, wherein: the conductive material filled in the via hole of each circuit board constituting the multilayer circuit board is a metal plating layer formed by electrolytic treatment, and a protruded conductor electrically connected to the metal plating layer is formed.
5. The multilayer circuit board of claim 4, wherein: the protruding conductor is formed of a conductive paste.
6. The multilayer circuit board according to claim 1 or 2, wherein: the conductive material filled in the via hole of each circuit board constituting the multilayer circuit board is a conductive paste formed of metal particles, a thermosetting or thermoplastic resin.
7. The multilayer circuit board according to claim 1 or 2, wherein: the distance between the adjacent via holes formed in the circuit boards is gradually increased from the one circuit board to the other circuit board.
8. A semiconductor device, characterized in that:the multilayer circuit board of claim 1 or 2, and an electronic component electrically connected to a conductive land formed on the outermost one of the multilayer circuit boards.
9. The semiconductor device according to claim 8, wherein: a reinforcing member is disposed in a peripheral portion of an outermost circuit board on which the electronic component is mounted, and a capacitor chip is electrically connected to a surface of another outermost circuit board facing the outermost circuit board.
10. A semiconductor device comprising a multilayer circuit board and an electronic component such as an LSI chip electrically connected to a circuit board located on the outermost side of the multilayer circuit board, wherein the multilayer circuit board is formed by laminating a plurality of circuit boards, each having a conductor circuit on one or both surfaces of an insulating hard substrate, a via hole formed by filling a plating material into an opening penetrating the insulating hard substrate and extending to the conductor circuit, and a projecting conductor electrically connected to the via hole corresponding to the position of the via hole, and thermally pressing the laminated circuit boards together, characterized in that:
a conductive flange which is located right above the via hole and is electrically connected to the via hole is formed on the surface of the outermost one of the circuit boards, and the electronic component is electrically connected to the conductive flange,
the capacitor chip is electrically connected to a via hole directly below the electronic component on the outermost surface of the circuit board opposite to the circuit board on which the electronic component is mounted.
11. The semiconductor device according to claim 10, wherein: a reinforcing member is bonded and fixed to a peripheral portion of a circuit board on which the electronic component is mounted.
12. A multilayer circuit board in which interlayer resin insulating layers and conductor layers are alternately laminated on one surface or both surfaces of a multilayer core board having a conductor circuit in an inner layer, and a build-up wiring layer connected by via holes is formed between the conductor layers, characterized in that:
the multilayer core board is formed by laminating a plurality of circuit boards, each having a conductor circuit on both or one surface of an insulating hard substrate and a via hole formed by filling a conductive material into a hole penetrating the insulating hard substrate and extending to the conductor circuit, with an adhesive and thermally pressing the laminated circuit boards together.
13. The multilayer circuit board according to claim 12, wherein the build-up wiring layers are formed on both surfaces of the multilayer core board, and wherein: a solder bump is provided on the surface of one outermost conductor layer constituting the build-up wiring layer, and a conductive pin or ball is provided on the surface of the other outermost conductor layer constituting the build-up wiring layer.
14. The multilayer circuit board according to claim 12, wherein the build-up wiring layers are formed on both surfaces of the multilayer core board, and wherein: the outermost conductor layer of the build-up wiring layer is covered with a solder resist layer, and a conductor pad or a connection terminal is formed from at least a part of the outermost conductor layer exposed at an opening provided in the solder resist layer.
15. The multilayer circuit board of claim 12, wherein: the conductive material is a metal plating layer formed by electrolytic treatment, and a protruded conductor electrically connected to the metal plating layer is formed.
16. The multilayer circuit board of claim 15, wherein: the protruding conductor is formed of a conductive paste.
17. The multilayer circuit board of claim 12, wherein: the conductive material is a conductive paste formed of metal particles and a thermosetting or thermoplastic resin.
18. The multilayer circuit board of claim 12, wherein: and a part of the via hole of the build-up wiring layer is positioned right above the via hole formed in the multilayer core board and is directly connected to the via hole.
19. The multilayer circuit board of claim 12, wherein: the insulating base material of each circuit board constituting the multilayer core board is made of any hard material selected from a group consisting of a glass fiber epoxy resin, a glass fiber bismaleimide-triazine resin, a glass fiber polyphenylene ether resin, an aromatic polyamide non-woven fiber epoxy resin and an aromatic polyamide non-woven fiber polyimide resin.
20. The multilayer circuit board of claim 19, wherein: the insulating base material of each circuit board constituting the multilayer core board is formed of a glass fiber epoxy resin having a thickness of 20 to 100 μm, and the diameter of the filled via hole is 50 to 250 μm.
21. The multilayercircuit board of claim 20, wherein: the via hole of each circuit board constituting the multilayer core board is formed in an opening formed by a carbon dioxide gas laser irradiating the surface of the glass fiber epoxy resin under the conditions of a pulse energy of 5 to 100mJ, a pulse width of 1 to 100 mus, a pulse interval of 0.5ms or more, and the number of impacts of 1 to 50.
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JP2000245648A JP2001217356A (en) 1999-11-26 2000-08-14 Multilayer circuit board and semiconductor device
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JP2000245649A JP4592889B2 (en) 1999-11-26 2000-08-14 Multilayer circuit board
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Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100346678C (en) * 2002-05-30 2007-10-31 株式会社电装 Enhancement of current-carrying capacity of a multilayer circuit board
CN100420096C (en) * 2003-05-21 2008-09-17 安普泰科电子有限公司 Electric connection structure, connector and electric connecting system
CN1577811B (en) * 2003-07-25 2010-04-28 台湾积体电路制造股份有限公司 Semiconductor package seal ring structure and producing method thereof and semiconductor package structure
US7871925B2 (en) 2006-09-30 2011-01-18 Hynix Semiconductor Inc. Stack package and method for manufacturing the same
CN101147433B (en) * 2005-03-24 2011-06-22 摩托罗拉移动公司 Multilayer circuit board with embedded components and method of manufacture
CN101449630B (en) * 2006-04-19 2012-02-15 动态细节有限公司 Printed circuit boards with stacked micros vias
CN102656955A (en) * 2009-07-31 2012-09-05 Ati科技无限责任公司 A method of manufacturing substrates having asymmetric buildup layers
CN101552092B (en) * 2003-04-25 2012-11-28 梅特格拉斯公司 Inductor, method for constructing amorphous metal magnetic component and production process
CN102905465A (en) * 2011-07-26 2013-01-30 鸿富锦精密工业（深圳）有限公司 Double-sided circuit board structure
CN103429011A (en) * 2012-05-24 2013-12-04 光颉科技股份有限公司 Conduction process method of substrate
CN105357911A (en) * 2015-12-16 2016-02-24 拓卡奔马机电科技有限公司 Novel electric connection structure of adapter coupling box of cloth paving machine
CN107734856A (en) * 2017-11-15 2018-02-23 泰州市博泰电子有限公司 A kind of preparation method of high-voltage wiring harness block terminal pcb board
CN108022732A (en) * 2016-10-28 2018-05-11 三星电机株式会社 Inductor, main body and the method for manufacturing inductor
CN111741592A (en) * 2020-06-17 2020-10-02 珠海越亚半导体股份有限公司 Multilayer substrate and manufacturing method thereof
CN112703272A (en) * 2018-03-05 2021-04-23 卡特拉姆有限责任公司 Catalytic laminate with conductive traces formed during lamination
TWI803174B (en) * 2022-01-27 2023-05-21 福懋科技股份有限公司 Ball pad applied for ball grid array package substrate and the forming method thereof
TWI809055B (en) * 2019-03-13 2023-07-21 美商凱特聯有限責任公司 Catalytic laminate with conductive traces formed during lamination

Families Citing this family (175)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1583407B1 (en) * 1998-02-26 2007-05-30 Ibiden Co., Ltd. Multilayer printed wiring board with filled viaholes
TW512653B (en) 1999-11-26 2002-12-01 Ibiden Co Ltd Multilayer circuit board and semiconductor device
TW526693B (en) * 2000-06-15 2003-04-01 Murata Manufacturing Co Multilayer circuit component and method for manufacturing the same
US6930256B1 (en) 2002-05-01 2005-08-16 Amkor Technology, Inc. Integrated circuit substrate having laser-embedded conductive patterns and method therefor
JP3729092B2 (en) * 2001-06-19 2005-12-21 ソニー株式会社 Conductive bonding material, multilayer printed wiring board, and method for manufacturing multilayer printed wiring board
KR100384769B1 (en) * 2001-06-21 2003-05-23 (주)포커스전자 The method and closed circuit board which has test zone hole which is formed on the printing circuit board for which printing circuit board which can be used as testing machine for semiconductor
KR100416141B1 (en) * 2001-06-22 2004-01-31 삼성에스디아이 주식회사 Method of manufacturing for field emission display having carbon-based emitter
CN1264391C (en) * 2001-06-27 2006-07-12 日本特殊陶业株式会社 Wiring substrate manufacture
JP2003017862A (en) * 2001-07-02 2003-01-17 Nitto Denko Corp Manufacturing method of multilayer interconnection board
JP2003023250A (en) 2001-07-06 2003-01-24 Denso Corp Multilayered substrate and its manufacturing method
JP3615727B2 (en) * 2001-10-31 2005-02-02 新光電気工業株式会社 Package for semiconductor devices
US7202556B2 (en) 2001-12-20 2007-04-10 Micron Technology, Inc. Semiconductor package having substrate with multi-layer metal bumps
MY140754A (en) * 2001-12-25 2010-01-15 Hitachi Chemical Co Ltd Connection board, and multi-layer wiring board, substrate for semiconductor package and semiconductor package using connection board, and manufacturing method thereof
US7038142B2 (en) * 2002-01-24 2006-05-02 Fujitsu Limited Circuit board and method for fabricating the same, and electronic device
US7049528B2 (en) * 2002-02-06 2006-05-23 Ibiden Co., Ltd. Semiconductor chip mounting wiring board, manufacturing method for same, and semiconductor module
US6690580B1 (en) * 2002-03-07 2004-02-10 Amd, Inc. Integrated circuit structure with dielectric islands in metallized regions
JP2003264253A (en) * 2002-03-12 2003-09-19 Shinko Electric Ind Co Ltd Semiconductor device and method of manufacturing the same
JP4024563B2 (en) * 2002-03-15 2007-12-19 株式会社日立製作所 Semiconductor device
US20080043447A1 (en) * 2002-05-01 2008-02-21 Amkor Technology, Inc. Semiconductor package having laser-embedded terminals
US9691635B1 (en) 2002-05-01 2017-06-27 Amkor Technology, Inc. Buildup dielectric layer having metallization pattern semiconductor package fabrication method
US7399661B2 (en) * 2002-05-01 2008-07-15 Amkor Technology, Inc. Method for making an integrated circuit substrate having embedded back-side access conductors and vias
US7548430B1 (en) 2002-05-01 2009-06-16 Amkor Technology, Inc. Buildup dielectric and metallization process and semiconductor package
US7670962B2 (en) 2002-05-01 2010-03-02 Amkor Technology, Inc. Substrate having stiffener fabrication method
JP2004039867A (en) * 2002-07-03 2004-02-05 Sony Corp Multilayer wiring circuit module and its manufacturing method
DE10235332A1 (en) * 2002-08-01 2004-02-19 Infineon Technologies Ag Multiple layer switch support used in flip-chip technology comprises a semiconductor chip and/or a discrete component, a rewiring layer, an insulating layer with through-structures, and outer contact surfaces
US6762367B2 (en) * 2002-09-17 2004-07-13 International Business Machines Corporation Electronic package having high density signal wires with low resistance
US20040104463A1 (en) * 2002-09-27 2004-06-03 Gorrell Robin E. Crack resistant interconnect module
TW587322B (en) * 2002-12-31 2004-05-11 Phoenix Prec Technology Corp Substrate with stacked via and fine circuit thereon, and method for fabricating the same
EP1601017A4 (en) * 2003-02-26 2009-04-29 Ibiden Co Ltd Multilayer printed wiring board
US6806563B2 (en) * 2003-03-20 2004-10-19 International Business Machines Corporation Composite capacitor and stiffener for chip carrier
JP4029759B2 (en) 2003-04-04 2008-01-09 株式会社デンソー Multilayer circuit board and manufacturing method thereof
JP4203435B2 (en) * 2003-05-16 2009-01-07 日本特殊陶業株式会社 Multilayer resin wiring board
JP2004356569A (en) * 2003-05-30 2004-12-16 Shinko Electric Ind Co Ltd Package for semiconductor device
TWI220304B (en) * 2003-06-20 2004-08-11 Advanced Semiconductor Eng Flip-chip package substrate and flip-chip bonding process thereof
US8238696B2 (en) 2003-08-21 2012-08-07 Microsoft Corporation Systems and methods for the implementation of a digital images schema for organizing units of information manageable by a hardware/software interface system
US7401104B2 (en) * 2003-08-21 2008-07-15 Microsoft Corporation Systems and methods for synchronizing computer systems through an intermediary file system share or device
US8166101B2 (en) 2003-08-21 2012-04-24 Microsoft Corporation Systems and methods for the implementation of a synchronization schemas for units of information manageable by a hardware/software interface system
US20050041405A1 (en) * 2003-08-22 2005-02-24 Intel Corporation Stacked via structure that includes a skip via
JP4397653B2 (en) * 2003-08-26 2010-01-13 日東電工株式会社 Adhesive sheet for semiconductor device manufacturing
FI20031341A (en) * 2003-09-18 2005-03-19 Imbera Electronics Oy Method for manufacturing an electronic module
KR100567087B1 (en) 2003-10-20 2006-03-31 삼성전기주식회사 Method for fabricating the multi layer printed circuit board in parallel with improved interconnection
US7143022B1 (en) 2003-12-30 2006-11-28 Hewlett-Packard Development Company, L.P. System and method for integrating subcircuit models in an integrated power grid analysis environment
WO2005086552A1 (en) * 2004-03-03 2005-09-15 Shinko Electric Industries Co., Ltd. Circuit board manufacturing method and circuit board
US11081370B2 (en) 2004-03-23 2021-08-03 Amkor Technology Singapore Holding Pte. Ltd. Methods of manufacturing an encapsulated semiconductor device
US10811277B2 (en) 2004-03-23 2020-10-20 Amkor Technology, Inc. Encapsulated semiconductor package
DE112005000014T5 (en) * 2004-04-06 2006-05-18 Murata Manufacturing Co., Ltd., Nagaokakyo Inner conductor connection structure and multi-layer substrate
US7778962B2 (en) * 2004-04-30 2010-08-17 Microsoft Corporation Client store synchronization through intermediary store change packets
FI117814B (en) 2004-06-15 2007-02-28 Imbera Electronics Oy A method for manufacturing an electronic module
WO2006001358A1 (en) * 2004-06-28 2006-01-05 Tdk Corporation Method for manufacturing multilayer electronic component
US7335979B2 (en) * 2004-06-28 2008-02-26 Intel Corporation Device and method for tilted land grid array interconnects on a coreless substrate package
US7220132B2 (en) * 2004-06-28 2007-05-22 Intel Corporation Tilted land grid array package and socket, systems, and methods
US7365007B2 (en) * 2004-06-30 2008-04-29 Intel Corporation Interconnects with direct metalization and conductive polymer
JP2006019636A (en) * 2004-07-05 2006-01-19 Renesas Technology Corp Semiconductor apparatus
KR100632560B1 (en) * 2004-08-05 2006-10-09 삼성전기주식회사 Parallel printed circuit board manufacturing method
FR2875995B1 (en) * 2004-09-24 2014-10-24 Oberthur Card Syst Sa METHOD FOR MOUNTING AN ELECTRONIC COMPONENT ON A SUPPORT, PREFERABLY MOU, AND ELECTRONIC ENTITY THUS OBTAINED, SUCH AS A PASSPORT
TWI301656B (en) * 2004-11-26 2008-10-01 Via Tech Inc Circuit board and process thereof
KR100626618B1 (en) * 2004-12-10 2006-09-25 삼성전자주식회사 Semiconductor chip stack package and related fabrication method
JP4319976B2 (en) * 2004-12-27 2009-08-26 日本シイエムケイ株式会社 Multilayer printed wiring board and manufacturing method thereof
US7394159B2 (en) * 2005-02-23 2008-07-01 Intel Corporation Delamination reduction between vias and conductive pads
JP2006245076A (en) * 2005-03-01 2006-09-14 Matsushita Electric Ind Co Ltd Semiconductor device
JP4545022B2 (en) * 2005-03-10 2010-09-15 三洋電機株式会社 Circuit device and manufacturing method thereof
US8826531B1 (en) 2005-04-05 2014-09-09 Amkor Technology, Inc. Method for making an integrated circuit substrate having laminated laser-embedded circuit layers
JP4790297B2 (en) * 2005-04-06 2011-10-12 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
JP4534062B2 (en) 2005-04-19 2010-09-01 ルネサスエレクトロニクス株式会社 Semiconductor device
JP4093425B2 (en) 2005-04-26 2008-06-04 Ｔｄｋ株式会社 Manufacturing method of laminated substrate
JP4341588B2 (en) * 2005-06-09 2009-10-07 株式会社デンソー Multilayer substrate and manufacturing method thereof
FI122128B (en) 2005-06-16 2011-08-31 Imbera Electronics Oy Process for manufacturing circuit board design
WO2006134220A1 (en) 2005-06-16 2006-12-21 Imbera Electronics Oy Method for manufacturing a circuit board structure, and a circuit board structure
FI119714B (en) 2005-06-16 2009-02-13 Imbera Electronics Oy Circuit board structure and method for manufacturing a circuit board structure
US7834273B2 (en) 2005-07-07 2010-11-16 Ibiden Co., Ltd. Multilayer printed wiring board
US7759582B2 (en) * 2005-07-07 2010-07-20 Ibiden Co., Ltd. Multilayer printed wiring board
JP2007059485A (en) * 2005-08-22 2007-03-08 Rohm Co Ltd Semiconductor device, substrate and method of manufacturing semiconductor device
JP2007076327A (en) * 2005-09-16 2007-03-29 Fujifilm Corp Electrical connection structure, liquid ejection head, manufacturing method for liquid ejection head, and image forming apparatus
WO2007052396A1 (en) * 2005-10-31 2007-05-10 Sharp Kabushiki Kaisha Multilayer wiring board and method for manufacturing multilayer wiring board
KR100712549B1 (en) * 2006-01-31 2007-05-02 삼성전자주식회사 Multi stack package with package lid
JP5105042B2 (en) * 2006-03-23 2012-12-19 イビデン株式会社 Multilayer printed wiring board
US9615463B2 (en) * 2006-09-22 2017-04-04 Oscar Khaselev Method for producing a high-aspect ratio conductive pattern on a substrate
JP4719657B2 (en) * 2006-09-28 2011-07-06 富士通株式会社 Placement model creation device, placement model creation method, and placement model creation program
US7589398B1 (en) 2006-10-04 2009-09-15 Amkor Technology, Inc. Embedded metal features structure
JPWO2008053833A1 (en) * 2006-11-03 2010-02-25 イビデン株式会社 Multilayer printed wiring board
JP2010515281A (en) * 2007-01-02 2010-05-06 オルメット サーキッツ、インコーポレイテッド Method for making high density multilayer printed wiring board from parallel processed circuits and filled vias
US7608538B2 (en) 2007-01-05 2009-10-27 International Business Machines Corporation Formation of vertical devices by electroplating
US7752752B1 (en) 2007-01-09 2010-07-13 Amkor Technology, Inc. Method of fabricating an embedded circuit pattern
ITRM20070189A1 (en) * 2007-04-04 2008-10-05 Uni Degli Studi Magna Graecia Di Catanzaro DEPOSITION OF POROUS LAYERED MATERIALS ON LAYER SUPPORTS SO OBTAINED AND DEVICES THAT INCLUDE THEM
US7969005B2 (en) * 2007-04-27 2011-06-28 Sanyo Electric Co., Ltd. Packaging board, rewiring, roughened conductor for semiconductor module of a portable device, and manufacturing method therefor
US20080304267A1 (en) * 2007-06-07 2008-12-11 Lin Yu-Ho Stationary led lamp
FI20070904A0 (en) * 2007-06-07 2007-11-26 Focoil Oy Procedure for making circuit boards
KR100832651B1 (en) * 2007-06-20 2008-05-27 삼성전기주식회사 Printed circuit board
TWI455672B (en) * 2007-07-06 2014-10-01 Murata Manufacturing Co A method for forming a hole for connecting a conductor for a layer, a method for manufacturing a resin substrate and a component-mounted substrate, and a method of manufacturing a resin substrate and a component
KR100841987B1 (en) * 2007-07-10 2008-06-27 삼성전기주식회사 Fabricating method for multilayer printed circuit board
US20110036617A1 (en) * 2007-08-03 2011-02-17 Leonid Kokurin Compensating Conductive Circuit
JP2009049051A (en) * 2007-08-14 2009-03-05 Elpida Memory Inc Bonding method of semiconductor substrate and laminate manufactured thereby
JP2009099589A (en) * 2007-10-12 2009-05-07 Elpida Memory Inc Wafer or circuit board and its connection structure
KR20090042574A (en) * 2007-10-26 2009-04-30 삼성전자주식회사 Semiconductor module and electronic device
KR100998303B1 (en) * 2007-12-13 2010-12-03 삼성에스디아이 주식회사 Protection circuit assembly and battery pack using the same
KR20090067249A (en) * 2007-12-21 2009-06-25 삼성전기주식회사 Printed circuit board and manufacturing method thereof
JP5295596B2 (en) * 2008-03-19 2013-09-18 新光電気工業株式会社 Multilayer wiring board and manufacturing method thereof
JP5290017B2 (en) * 2008-03-28 2013-09-18 日本特殊陶業株式会社 Multilayer wiring board and manufacturing method thereof
US8110752B2 (en) * 2008-04-08 2012-02-07 Ibiden Co., Ltd. Wiring substrate and method for manufacturing the same
JP5191283B2 (en) * 2008-06-06 2013-05-08 セイコープレシジョン株式会社 Welding machine and multilayer printed wiring board manufacturing method
KR20100033012A (en) 2008-09-19 2010-03-29 주식회사 하이닉스반도체 Semiconductor package and stacked semiconductor package having the same
EP2209358A4 (en) 2008-09-30 2012-07-04 Ibiden Co Ltd Multilayer printed wiring board and method for manufacturing multilayer printed wiring board
KR20100062550A (en) * 2008-12-02 2010-06-10 삼성전기주식회사 A package substrate including solder resist layers having pattern and a fabricating method the same
KR101006603B1 (en) * 2009-01-09 2011-01-07 삼성전기주식회사 A printed circuit board and a fabricating method the same
US8872329B1 (en) 2009-01-09 2014-10-28 Amkor Technology, Inc. Extended landing pad substrate package structure and method
JP2010186848A (en) * 2009-02-12 2010-08-26 Fujitsu Ltd Method of manufacturing electronic component unit
US8179639B2 (en) * 2009-03-02 2012-05-15 Seagate Technology Llc Head gimbal assembly without bus traces for plating
US8531015B2 (en) * 2009-03-26 2013-09-10 Stats Chippac, Ltd. Semiconductor device and method of forming a thin wafer without a carrier
US9930775B2 (en) * 2009-06-02 2018-03-27 Hsio Technologies, Llc Copper pillar full metal via electrical circuit structure
JP5561279B2 (en) 2009-09-02 2014-07-30 パナソニック株式会社 Printed wiring board, build-up multilayer substrate and manufacturing method thereof
KR101101432B1 (en) * 2009-09-08 2012-01-02 앰코 테크놀로지 코리아 주식회사 Fabrication method of semiconductor device and semiconductor device using the same
JP5367523B2 (en) * 2009-09-25 2013-12-11 新光電気工業株式会社 Wiring board and method of manufacturing wiring board
JP2011096900A (en) * 2009-10-30 2011-05-12 Fujitsu Ltd Electric conductor and printed wiring board, and method of manufacturing the electric conductor and the printed wiring board
US20110110061A1 (en) * 2009-11-12 2011-05-12 Leung Andrew Kw Circuit Board with Offset Via
CN102484952A (en) * 2009-11-18 2012-05-30 株式会社藤仓 Partially multilayer wiring board and method for producing same
US8207453B2 (en) 2009-12-17 2012-06-26 Intel Corporation Glass core substrate for integrated circuit devices and methods of making the same
US9420707B2 (en) * 2009-12-17 2016-08-16 Intel Corporation Substrate for integrated circuit devices including multi-layer glass core and methods of making the same
US8609995B2 (en) * 2010-07-22 2013-12-17 Ngk Spark Plug Co., Ltd. Multilayer wiring board and manufacturing method thereof
JP2012084799A (en) 2010-10-14 2012-04-26 Panasonic Corp Electronic circuit
US8698303B2 (en) * 2010-11-23 2014-04-15 Ibiden Co., Ltd. Substrate for mounting semiconductor, semiconductor device and method for manufacturing semiconductor device
US9077344B2 (en) * 2010-12-07 2015-07-07 Atmel Corporation Substrate for electrical component and method
JP5848110B2 (en) * 2011-02-15 2016-01-27 日本特殊陶業株式会社 Manufacturing method of multilayer wiring board
CN102595799B (en) * 2011-12-30 2015-03-25 柏承科技(昆山)股份有限公司 Manufacturing method of high-density interconnected printed circuit board
US8921703B2 (en) * 2012-02-17 2014-12-30 Htc Corporation Circuit board, structural unit thereof and manufacturing method thereof
US9445496B2 (en) 2012-03-07 2016-09-13 Intel Corporation Glass clad microelectronic substrate
CN102625604B (en) * 2012-03-20 2014-10-01 柏承科技(昆山)股份有限公司 Manufacturing method for high-density interconnection printed board
CN103687306A (en) * 2012-09-05 2014-03-26 北大方正集团有限公司 Printed circuit board and manufacturing method thereof
US9001520B2 (en) 2012-09-24 2015-04-07 Intel Corporation Microelectronic structures having laminated or embedded glass routing structures for high density packaging
JP2014150091A (en) * 2013-01-31 2014-08-21 Kyocer Slc Technologies Corp Wiring board, and method of manufacturing the same
US9929038B2 (en) * 2013-03-07 2018-03-27 Analog Devices Global Insulating structure, a method of forming an insulating structure, and a chip scale isolator including such an insulating structure
FR3007403B1 (en) * 2013-06-20 2016-08-05 Commissariat Energie Atomique METHOD FOR PRODUCING A MECHANICALLY AUTONOMOUS MICROELECTRONIC DEVICE
JP6266907B2 (en) * 2013-07-03 2018-01-24 新光電気工業株式会社 Wiring board and method of manufacturing wiring board
US10231333B1 (en) 2013-08-27 2019-03-12 Flextronics Ap, Llc. Copper interconnect for PTH components assembly
US20150101846A1 (en) * 2013-10-14 2015-04-16 Samsung Electro-Mechanics Co., Ltd. Printed circuit board and method of manufacturing the same
KR102172314B1 (en) * 2013-11-12 2020-10-30 삼성전자주식회사 Semiconductor device
KR20150062558A (en) * 2013-11-29 2015-06-08 삼성전기주식회사 Printed circuit board and Manufacture method using thereof
TWI482541B (en) * 2013-12-10 2015-04-21 Subtron Technology Co Ltd Circuit board and manufacturing method thereof
KR102008491B1 (en) * 2013-12-31 2019-08-07 코오롱인더스트리 주식회사 Photosensitive resin composition for organic insulator
JP6375121B2 (en) * 2014-02-27 2018-08-15 新光電気工業株式会社 WIRING BOARD, SEMICONDUCTOR DEVICE, AND WIRING BOARD MANUFACTURING METHOD
JP2015170770A (en) * 2014-03-07 2015-09-28 イビデン株式会社 Printed wiring board
JP6128046B2 (en) * 2014-03-31 2017-05-17 ソニー株式会社 Mounting board and electronic equipment
US9920893B2 (en) * 2014-06-18 2018-03-20 General Led Opco, Llc Busline LED module
JP5797309B1 (en) * 2014-07-22 2015-10-21 株式会社フジクラ Printed wiring board
KR102268385B1 (en) * 2014-08-14 2021-06-23 삼성전기주식회사 Printed circuit board and method of manufacturing the same
US9673287B2 (en) * 2014-12-15 2017-06-06 Infineon Technologies Americas Corp. Reliable and robust electrical contact
DE102015101440B4 (en) * 2015-02-02 2021-05-06 Infineon Technologies Ag Semiconductor component with a chip arranged below the package and method for mounting the same on an application board
US10154583B1 (en) 2015-03-27 2018-12-11 Flex Ltd Mechanical strain reduction on flexible and rigid-flexible circuits
US10455708B2 (en) * 2015-06-29 2019-10-22 Samsung Electro-Mechanics Co., Ltd. Multilayered substrate and method for manufacturing the same
US10466118B1 (en) 2015-08-28 2019-11-05 Multek Technologies, Ltd. Stretchable flexible durable pressure sensor
US9941565B2 (en) 2015-10-23 2018-04-10 Analog Devices Global Isolator and method of forming an isolator
US10204732B2 (en) 2015-10-23 2019-02-12 Analog Devices Global Dielectric stack, an isolator device and method of forming an isolator device
CN105899003B (en) * 2015-11-06 2019-11-26 武汉光谷创元电子有限公司 Single layer board, multilayer circuit board and their manufacturing method
US9883582B2 (en) * 2015-11-20 2018-01-30 Hamilton Sundstrand Corporation Circuit boards and circuit board assemblies
JP6691835B2 (en) * 2016-06-17 2020-05-13 株式会社アムコー・テクノロジー・ジャパン Method for manufacturing semiconductor package
JP6759784B2 (en) * 2016-07-12 2020-09-23 三菱電機株式会社 Semiconductor module
CN108538799B (en) 2017-03-02 2024-02-27 弗莱克斯有限公司 Interconnect component and interconnect assembly
US10446515B2 (en) * 2017-03-06 2019-10-15 Advanced Semiconductor Engineering, Inc. Semiconductor substrate and semiconductor packaging device, and method for forming the same
US10381296B2 (en) 2017-03-06 2019-08-13 Advanced Semiconductor Engineering, Inc. Semiconductor device package and a method of manufacturing the same
US10535845B1 (en) 2017-07-14 2020-01-14 Flex Ltd. Flexible and stretchable chain battery
KR20190012485A (en) * 2017-07-27 2019-02-11 삼성전기주식회사 Printed circuit board and method of fabricating the same
KR102483613B1 (en) * 2017-10-20 2023-01-02 삼성전기주식회사 Printed circuit board
KR102442386B1 (en) * 2017-10-20 2022-09-14 삼성전기주식회사 Printed circuit board
US10426029B1 (en) * 2018-01-18 2019-09-24 Flex Ltd. Micro-pad array to thread flexible attachment
US10687421B1 (en) 2018-04-04 2020-06-16 Flex Ltd. Fabric with woven wire braid
TWI655739B (en) * 2018-04-19 2019-04-01 南亞電路板股份有限公司 Package structure and forming method thereof
US10575381B1 (en) 2018-06-01 2020-02-25 Flex Ltd. Electroluminescent display on smart textile and interconnect methods
US10667398B1 (en) * 2018-09-26 2020-05-26 United States Of America As Represented By The Administrator Of Nasa Dual dynamic random (DDR) access memory interface design for aerospace printed circuit boards
KR102551909B1 (en) * 2018-10-16 2023-07-04 삼성전자주식회사 Semiconductor package and method for fabricating the same
US11039540B2 (en) * 2019-01-01 2021-06-15 Catlam, Llc Multi-layer circuit board with traces thicker than a circuit board layer
JP7031955B2 (en) * 2019-09-10 2022-03-08 Ｆｉｃｔ株式会社 Circuit board manufacturing method
CN110689820A (en) * 2019-10-09 2020-01-14 深圳市科伦特电子有限公司 LED lamp panel and manufacturing process
US11528806B2 (en) * 2020-02-22 2022-12-13 Kla Corporation Electromagnet coils made from flexible circuits
WO2022202322A1 (en) * 2021-03-26 2022-09-29 株式会社村田製作所 Wiring substrate, layered substrate, and method for manufacturing wiring substrate
KR20220160967A (en) * 2021-05-28 2022-12-06 (주)티에스이 multi-layer printed circuit board made of different materials and manufacturing method of the same
JPWO2023175965A1 (en) * 2022-03-18 2023-09-21

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3471631A (en) * 1968-04-03 1969-10-07 Us Air Force Fabrication of microminiature multilayer circuit boards
US4349862A (en) * 1980-08-11 1982-09-14 International Business Machines Corporation Capacitive chip carrier and multilayer ceramic capacitors
JPH02168662A (en) * 1988-09-07 1990-06-28 Hitachi Ltd Chip carrier
JPH0719964B2 (en) * 1990-08-08 1995-03-06 日本電気株式会社 Silver-based wiring ceramic substrate
JP2996510B2 (en) * 1990-11-30 2000-01-11 株式会社日立製作所 Electronic circuit board
US5374469A (en) * 1991-09-19 1994-12-20 Nitto Denko Corporation Flexible printed substrate
JP2658672B2 (en) * 1991-10-11 1997-09-30 日本電気株式会社 I / O pin repair structure and repair method
JP3059568B2 (en) 1992-01-23 2000-07-04 古河電気工業株式会社 Method of manufacturing multilayer printed circuit board
JPH0828580B2 (en) * 1993-04-21 1996-03-21 日本電気株式会社 Wiring board structure and manufacturing method thereof
EP0651602B1 (en) * 1993-10-29 1999-04-07 Matsushita Electric Industrial Co., Ltd. Conductive paste compound for via hole filling, printed circuit board which uses the conductive paste, and method of manufacturing the same
JP3512225B2 (en) 1994-02-28 2004-03-29 株式会社日立製作所 Method for manufacturing multilayer wiring board
JP3199592B2 (en) * 1995-01-27 2001-08-20 株式会社日立製作所 Multilayer printed circuit board
JPH0917828A (en) * 1995-04-28 1997-01-17 Asahi Denka Kenkyusho:Kk Circuit board
JPH09116273A (en) * 1995-08-11 1997-05-02 Shinko Electric Ind Co Ltd Multilayered circuit board and its manufacture
JP3197213B2 (en) * 1996-05-29 2001-08-13 松下電器産業株式会社 Printed wiring board and method of manufacturing the same
US6217987B1 (en) * 1996-11-20 2001-04-17 Ibiden Co. Ltd. Solder resist composition and printed circuit boards
DE69730629T2 (en) * 1996-12-26 2005-02-03 Matsushita Electric Industrial Co., Ltd., Kadoma Printed circuit board and electronic component
US5798563A (en) * 1997-01-28 1998-08-25 International Business Machines Corporation Polytetrafluoroethylene thin film chip carrier
JPH1154934A (en) 1997-06-06 1999-02-26 Ibiden Co Ltd Multilayered printed wiring board and its manufacture
JPH1154926A (en) * 1997-06-06 1999-02-26 Ibiden Co Ltd One-sided circuit board and its manufacture
US5798567A (en) * 1997-08-21 1998-08-25 Hewlett-Packard Company Ball grid array integrated circuit package which employs a flip chip integrated circuit and decoupling capacitors
JPH11214846A (en) * 1998-01-28 1999-08-06 Ibiden Co Ltd Multilayer printed wiring board
JP4159136B2 (en) * 1998-04-16 2008-10-01 イビデン株式会社 Multilayer printed wiring board
JP2000003980A (en) * 1998-04-17 2000-01-07 Sumitomo Metal Electronics Devices Inc Semiconductor mounting circuit board and its manufacture
US6139777A (en) * 1998-05-08 2000-10-31 Matsushita Electric Industrial Co., Ltd. Conductive paste for filling via-hole, double-sided and multilayer printed circuit boards using the same, and method for producing the same
JP4124297B2 (en) * 1998-09-16 2008-07-23 大日本印刷株式会社 Multilayer wiring board and manufacturing method thereof
TW512653B (en) 1999-11-26 2002-12-01 Ibiden Co Ltd Multilayer circuit board and semiconductor device

Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100346678C (en) * 2002-05-30 2007-10-31 株式会社电装 Enhancement of current-carrying capacity of a multilayer circuit board
CN101552092B (en) * 2003-04-25 2012-11-28 梅特格拉斯公司 Inductor, method for constructing amorphous metal magnetic component and production process
CN100420096C (en) * 2003-05-21 2008-09-17 安普泰科电子有限公司 Electric connection structure, connector and electric connecting system
CN1577811B (en) * 2003-07-25 2010-04-28 台湾积体电路制造股份有限公司 Semiconductor package seal ring structure and producing method thereof and semiconductor package structure
CN101147433B (en) * 2005-03-24 2011-06-22 摩托罗拉移动公司 Multilayer circuit board with embedded components and method of manufacture
CN102655716B (en) * 2006-04-19 2017-07-04 动态细节有限公司 Printed circuit board (PCB) with stacked micros vias and preparation method thereof
CN101449630B (en) * 2006-04-19 2012-02-15 动态细节有限公司 Printed circuit boards with stacked micros vias
CN102655716A (en) * 2006-04-19 2012-09-05 动态细节有限公司 Printed circuit boards with stacked micros vias
US7871925B2 (en) 2006-09-30 2011-01-18 Hynix Semiconductor Inc. Stack package and method for manufacturing the same
CN102656955B (en) * 2009-07-31 2015-04-15 Ati科技无限责任公司 A method of manufacturing substrates having asymmetric buildup layers
CN102656955A (en) * 2009-07-31 2012-09-05 Ati科技无限责任公司 A method of manufacturing substrates having asymmetric buildup layers
CN102905465A (en) * 2011-07-26 2013-01-30 鸿富锦精密工业（深圳）有限公司 Double-sided circuit board structure
CN103429011A (en) * 2012-05-24 2013-12-04 光颉科技股份有限公司 Conduction process method of substrate
CN103429011B (en) * 2012-05-24 2016-06-01 光颉科技股份有限公司 Conduction process method of substrate
CN105357911A (en) * 2015-12-16 2016-02-24 拓卡奔马机电科技有限公司 Novel electric connection structure of adapter coupling box of cloth paving machine
CN105357911B (en) * 2015-12-16 2019-04-02 拓卡奔马机电科技有限公司 A kind of connecting structure for electrical equipment that layout machine interconnecting device is novel
CN108022732A (en) * 2016-10-28 2018-05-11 三星电机株式会社 Inductor, main body and the method for manufacturing inductor
US10811182B2 (en) 2016-10-28 2020-10-20 Samsung Electro-Mechanics Co., Ltd. Inductor and method of manufacturing the same
CN107734856A (en) * 2017-11-15 2018-02-23 泰州市博泰电子有限公司 A kind of preparation method of high-voltage wiring harness block terminal pcb board
CN112703272A (en) * 2018-03-05 2021-04-23 卡特拉姆有限责任公司 Catalytic laminate with conductive traces formed during lamination
CN112703272B (en) * 2018-03-05 2023-08-22 卡特拉姆有限责任公司 Catalytic laminate with conductive traces formed during lamination
TWI809055B (en) * 2019-03-13 2023-07-21 美商凱特聯有限責任公司 Catalytic laminate with conductive traces formed during lamination
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CN1319157C (en) 2007-05-30
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