CN1336689A - 小电感的电路结构 - Google Patents

小电感的电路结构 Download PDF

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CN1336689A
CN1336689A CN01125041A CN01125041A CN1336689A CN 1336689 A CN1336689 A CN 1336689A CN 01125041 A CN01125041 A CN 01125041A CN 01125041 A CN01125041 A CN 01125041A CN 1336689 A CN1336689 A CN 1336689A
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substrate
connecting line
power
power transistor
circuit structure
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CN100397769C (zh
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保罗·毛利克
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SEMICRON ELECTRONIC CO Ltd
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Abstract

本发明涉及一种具有小的寄生电感的电路结构,它由其上具有相互绝缘的金属连接线的一个陶瓷衬底,衬底上分别由多个并联的第一(13)和第二功率晶体管(19)构成的串行连接的第一和第二功率开关,以及直流－和交流－连接线组成,它在结构上也适合于压力接触结构。正－(12),负－(10)及交流连接线(11)的流过电流的桥形接片(23)如此安置在第一和第二功率晶体管之间,它们一直抵达衬底平面,并且与它仅由一绝缘层隔离。这样最小化电流环流面积,从而减小电路结构的寄生电感。此半导体功率模块在连接线区域及衬底区域的寄生电感总和达到1nH数量级或更小。

Description

小电感的电路结构
技术领域
本发明涉及一种电路结构，尤其是功率级整流器的结构，电路结构也适合于压力接触安装。功率级整流器最好应用快速和低损耗开关的半导体开关。因此特别合适的电路结构是MOSFET或绝缘-栅-双极型晶体管(IGBT)和与其反向并联的无载工作二极管。这种电路结构和这样构成的整流器必须设计成小电感的，以避免尤其是在关断过程中所出现的电压峰。这意味着中间电路中连接线上和衬底表面上的杂散电感都必须很小。20nH范围内的杂散电感在低压-MOSFET情况下已经会导致出现可能使半导体开关损坏的电压峰。
背景技术
现有技术对单个开关和功率半导体模块采取单独的结构上的措施来减小寄生电感，这些措施如EP0277546，DE3937045或EP0609528所公开的。
在EP0277546中描述了对单个开关减小在直流馈线中的寄生电感的一种方法。其中两根直流馈线紧挨着并且至少部分相互并行排列。这样在馈线紧挨着排列的区域内产生小的电流环流面积，从而这些馈线段有小的电感。
在DE3937045中描述了对一个半桥减小在直流馈线中的寄生电感的一种方法。其中两根直流馈线紧挨着处于正-和负馈线之间的交流馈线，并且至少部分相互并行排列。这同样在馈线紧挨着排列的区域内产生小的电流环流面积，从而这些馈线段有相对小的电感。
在EP0609528中也说明了对单个开关减小在并行和紧挨着的直流馈线中的寄生电感的一种方法。此外在这里半导体元件对称地排列在衬底上。
现有技术包括采用压力接触工艺(Druckkontakttechnik)的功率半导体膜块，如DE19630173及DE59306387所述。这种功率半导体模块由其上涂覆有接触面的陶瓷衬底组成，半导体元件排列在衬底上。这些半导体元件通过焊接与接触面连接，并且与其它半导体元件或其它的与第一个接触面绝缘的、位于衬底上的第二个接触面有焊接连接。这里印刷连接有两种不同的连接方式。一方面连接导线电连接到衬底的相应接触面上，另一方面热连接衬底或整个模块到一个散热器上。在这种连接中例如利用由塑料构成的压力传递元件，它施加一个由外作用于模块上的压力于连接元件和/或衬底上，以形成可靠的电接触和热接触。
所有现有技术中可获得低电感电路结构的发明的共同之处在于，它们仅仅在整个系统中间电路-交流整流器的部分区域中获得寄生电感的某种程度上的减小。这样可取得的整个系统的总电感值目前在最好情况下大于20nH。
在EP0277546中构成单个开关的多个晶体管相互紧挨着，此外电流可在不同的，首先是不同长度的路径上流过电路结构。由此导致不同的电流环流面积，从而对于不同的导电路径有不同的电感。具有这种单个开关的半桥结构由于其所必需的外部连接而绝不能实现低电感。这导致总性能上整个系统中间电路-交流整流器的寄生电感的有限降低。这样仍然不能实现减小寄生电感的全部要求。
在DE3937045中减小寄生电感的目的由于两个基本原因而没有达到。首先因为交流连接线排列在两根直流连接线之间，直流连接线相互间不能以最小间距排列。这样在直流连接线区域内的电流环流面积不是最小，从而在此区域内电感也不是最小。其次，第一和第二个功率开关的功率晶体管相隔较远地安装，这也增大了寄生电感。
发明内容
本发明的目的在于，不仅在连接导线的区域内，而且也在安装在电绝缘的衬底上的半导体元件的区域内进一步减小电路结构的寄生电感，使得此结构的总电感为1nH的数量级或者比现有技术至少低一个数量级。
上述任务的解决方案是，通过以下措施整体上减小中间电路从正端到负端的全部电路结构的电流环流面积：
·第一和第二功率开关紧挨着排列在衬底上。
·第一和第二功率开关串联放置并从而尽可能短地相互连接。
·构成第一和第二功率开关的功率晶体管以及可能有的无载工作二极管也紧挨着串联放置。
·正-和负-端的连接线为带状结构。
·正-和负-端的连接线在其行程中直至衬底附近都是并行排列。
·正-和负-端的连接线仅通过一个绝缘层来分开而紧挨着。
·两个直流连接中的至少一个的连接带的一段靠着衬底并行于它安放，并尽可能在功率晶体管上方有最小间距。
·并行于衬底安放的至少一个直流连接的段具有桥形接片(Steg)。这些桥形接片在功率开关的功率晶体管之间的区域中向下一直抵达底板，并且相互仅由一个必要的绝缘层隔离。
·采用上述结构也可使用桥形接片作为衬底至散热器的印刷连接。这样它至少可部分代替现有技术中的压力元件。
通过上述这些措施，不仅在衬底平面上，而且在所有垂直于它的，由连接导线确定的面上都使电感极小化。
附图说明
下面借助图1至7所示实施例详细说明本发明。实施例的相应结构如权利要求1至7所述。附图中：
图1简要示出现有技术对应的半桥以及其电流环流区域。
图2示出具有多个功率晶体管的图1所示半桥，以及此结构的最大电流环流区域。
图3示出现有技术中的衬底和一个半桥的功率晶体管的结构，  以及在此结构中的最大电流环流区域。
图4示出本发明电路结构的一个视图。
图5示出现有技术连接线的电流环流区域。
图6示出本发明电路结构的电流环流区域。
图7示出本发明电路结构的三维视图。
实施例详细描述
图1简要示出一个半桥。现有技术下典型结构由一个包括电容器1，正和负连接2、3，以及功率开关4的中间电路组成。功率开关可用MOSFET或IGBT实现。在用IGBT实现的情况下必需附加无载工作二极管5。交流连接用6示出。箭头7表示在开通过程中从正端到负端的电流流向，斜线区表示这情况下电流环流面积8。电流环流面积的大小是对产生的寄生电感的直接量度，该面积形象地构成一个一圈的线圈的横截面。
图2示出在第一和第二功率开关分别由多个并联的功率晶体管实现的情况下图1所示电路结构的实现情况。在此情况下斜线区8表示最大的电流环流面积。可见，此面积和由此产生的相应电感对各个功率晶体管是不相同的。
图3示出现有技术中一个半桥的衬底的实现。为清楚起见，辅助连接，如栅极，基极或辅助极未示出。在陶瓷衬底9上排列有用于正连接11，负连接10及交流连接12的敷铜面。在正连接敷铜面上有作为第一功率开关的第一功率晶体管13和无载工作二极管14，功率晶体管的发射极用焊线15与交流连接的敷铜面12连接。在此敷铜面上排列着第二功率晶体管及相应的无载工作二极管。此第二功率晶体管借助于焊线与负连接敷铜面连接。引入中间电路的正连接线17，负连接线16和交流连接线18同样设置在与其极性对应的敷铜面上。现有技术中典型的这种结构已经是正和负连接线紧挨着排列了，至少在衬底上直至一个小的间距。箭头7在这里也表示最大的电流环流面积。此面积确定该电路结构的寄生电感。采用这种电路结构，衬底面上典型的电感达到20至50nH的范围内。
图4示出本发明电路结构的一个视图，其中连接线是结构的集成组成部分，以在衬底区域内得到最小的电感。此图中同样为了清楚起见没有示出必要的辅助连接。在衬底9上按照现有技术排列有用于正连接12，负连接10和交流连接11的敷铜面。本发明的思路在于以下两个特征的组合。
为了极小化寄生电感，首先第一功率晶体管13(例如MOSFET)必须尽可能紧挨第二功率晶体管19，并且第一和第二功率晶体管串联排列。
第二，正连接线20和负连接线21连接线以带状结构引入电流，为了说明清楚，这两根连接线被分成几段(参见图6)。
段“A”从中间电路连接抵达衬底表面附近，段“B”走向并行于衬底表面，此外段“C”连接于并行走向的段并且典型地垂直连接到衬底表面上相应的敷铜面上。两根直流连接线中至少一根是如此结构的。段B具有决定本发明思路的特征，它不仅仅呈带状并行于衬底表面安置，而且在串联排列的第一和第二功率晶体管之间的区域内至少有一个并行走向的桥形接片。此桥形接片一直抵达衬底表面上，并且与相应另一个导线的敷铜面仅通过一个薄绝缘层隔离。
正连接线20在段“A”并行于负连接线21排列，并且在此段中相互通过一个绝缘层隔离。段“B”仅示出桥形接片23，带状走在桥形接片上面并连接桥形接片的部分图中未示出。并行的桥形接片在衬底表面的斜线区中并通过一个薄绝缘层与那里的负连接10和交流连接11的敷铜面隔离。在平面示出的区域内桥形接片实在地或可拆卸地与敷铜面连接。类似地这也适用于交流连接线。这里箭头7同样表示最大的电流环流面积。在衬底平面上的电流环流面积被这种结构极小化了。此外，由于这种结构的对称性，对所有功率晶体管有相等的电流负载和相等的寄生电感。
这种电路结构中在衬底平面上的电感达到1nH的数量级和更小。
交流连接线22以与正连接线20相同的方式实现，  即带状地用桥形接片抵达DCB-陶瓷。
图5示出现有技术中的一个由连接导线确定的垂直于衬底9的平面。在此衬底9上排列有用于正连接12，  负连接10和交流连接11的敷铜面。在正-连接敷铜面上有第一功率晶体管13。第二功率晶体管19在交流连接敷铜面11上。第一功率晶体管13的发射极用焊线15与交流连接敷铜面11连接。第二功率晶体管的发射极同样借助于焊线15与负-连接敷铜面10连接。在此平面上被电流环流的面积24在正连接线之下一直延伸到衬底的表面，并且在直至其焊接连线的范围内。
图6示出本发明在由连接线确定的垂直于衬底9的平面。连接线的三段“A”，“B”和“C”在此图中被示出。通过本发明一直抵达衬底上表面的桥形接片23，在正连接线带状部分之下的这个区域不再被电流环绕。现在至敷铜面12的电流直接在衬底表面上流过，其它至负连接线的电流在衬底以及在具有通过它的焊接连接的段中流过。这样得到三个有意义的电流环流面积：负和正连接线之间的区域26以及向上被焊线限制，向下被本发明桥形接片23的下侧所限制的两个区域25。与图5对比可以看出明显减小了电流环流面积，从而减小了本发明电路结构的寄生电感。为了得到足够低电感的电路结构，中间电路电容必须直接安放在直流导线上。
图7示出本发明想法的一个三维视图。这里分别示出了第一功率晶体管13和第二功率晶体管19。此图中没有示出所有辅助连接以及连接线的带状部分，这一部分在衬底上面桥形接片之上，并且仅在必要时被断开，以引入辅助连接用的连接线。正连接线12，负连接线10和交流连接线11的桥形接片23除了使得在连接线中的电感最小之外还可作为压力元件用于压力接触连接结构，每一根上述连接线具有经过桥形接片直接与为其设置的敷铜面的连接，并且在压力接触结构中不仅用于连接的电接触，而且也用作衬底在散热器上的热印刷接触。热印刷接触也可由一根连接线的每个桥形接片在不是为它设置的敷铜面上实现，因为它们之间仅通过一个绝缘层，典型地是一塑料薄膜，而被隔离。

Claims (5)

1.具有小的寄生电感的电路结构，它由其上具有相互绝缘的金属连接线的一个电绝缘衬底(9)，安装于衬底上的串行连接的第一和第二功率开关，以及直流-(20，21)和交流连接线(22)组成，功率开关分别由多个并联的第一(13)和第二(19)功率晶体管组成，其特征在于，各个第一(13)和第二(19)功率晶体管紧挨着并且串行排列，直流连接线(20，21)在第一段中呈带状紧挨着并行排列直到衬底表面(9)附近或与衬底接触，而且至少一根直流连接线(20)具有其上安装有桥形接片(23)的与衬底表面(9)平行的第二个带状段，其中桥形接片(23)仅通过一个绝缘层与衬底隔离，且具有至少一个与衬底表面(9)的接点(12)。
2.如权利要求1或3所述的电路结构，其特征在于，桥形接片(23)安装于功率晶体管(13、19)之间，并且至少一根直流连接线(20)被设计为压力传递元件用于建立模块的压力接触。
3.如权利要求1或4所述的电路结构，其特征在于，第一和第二功率开关由两行对称于衬底的中轴线安装的功率晶体管构成。
4.如权利要求1至5中任一项所述的电路结构，其特征在于，功率晶体管是IGBT或MOSFET。
5.如权利要求1至5中任一项所述的电路结构，其特征在于，除晶体管外还有一个或多个无载工作的二极管构成功率开关，并且它们与其对应的功率晶体管排列在一行中。
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