CN104134652A - 具有子单元的功率半导体模块及对应的系统 - Google Patents
具有子单元的功率半导体模块及对应的系统 Download PDFInfo
- Publication number
- CN104134652A CN104134652A CN201410180727.2A CN201410180727A CN104134652A CN 104134652 A CN104134652 A CN 104134652A CN 201410180727 A CN201410180727 A CN 201410180727A CN 104134652 A CN104134652 A CN 104134652A
- Authority
- CN
- China
- Prior art keywords
- power semiconductor
- subelement
- semiconductor modular
- joint element
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/40227—Connecting the strap to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/84801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Materials Engineering (AREA)
- Inverter Devices (AREA)
- Dc-Dc Converters (AREA)
Abstract
本发明涉及一种功率半导体模块,该功率半导体模块具有壳体和至少一个采用具有上部开关和下部开关的半桥拓扑形式的开关装置。在此,开关装置由多个同样采用半桥拓扑形式的、彼此相对电绝缘的子单元构成,其中,每个子单元具有分别构造为恰好一个半导体开关的上部和下部子开关。上部的和下部的子开关借助内部的负载连接元件彼此符合电路要求地连接。此外,子单元具有不同电势的负载接合元件,所述负载接合元件面式地构造并且在它们的延伸部上紧邻地布置并且因此构造成局部的堆栈。本发明还涉及一种系统。
Description
技术领域
本发明描述了一种具有多于两个子单元的功率半导体模块及对应的系统,其中,功率半导体模块以及系统具有特别小的寄生电感。
背景技术
由现有技术(例如在DE3937045A1中公开的)公知一种具有开关装置的功率半导体模块,其中该开关装置构造为一个或多个半桥电路。采用半桥拓扑形式的开关装置组成功率电子电路的基本单元。采用半桥拓扑形式的开关装置具有一个上部开关以及一个下部开关。在本领域中常见的以及在DE3937045A1中也示出的是,相应的开关构造为平行联接的多个半导体开。
功率半导体模块的上述设计方案有以下缺点:在换向时的开关操作中,由多个半导体开关的位置、以及功率半导体模块的负载接合元件的位置和设计方案决定电流环路面积,以及最终因此决定换向电感。因此,大量的半导体开关引起高换向电感。
发明内容
根据上述背景知识,本发明基于如下任务:介绍了一种内部寄生电感、尤其换向电感特别小的功率半导体模块,以及一种具有上述功率半导体模块和电容器装置的系统,其中,整个系统的寄生电感,尤其换向电感特别小。
根据本发明,该任务通过具有权利要求1中的特征的功率半导体模块以及具有权利要求10中的特征的系统来解决。优选的实施方式在从属权利要求中描述。
根据本发明的功率半导体模块构造有壳体以及至少一个采用具有上部和下部开关的半桥拓扑形式的开关装置,其中,该开关装置本身由多个同样采用半桥拓扑形式的、彼此相对电绝缘的子单元构成,其中,每个子单元具有分别构造为恰好一个半导体开关的上部和下部子开关,其中,上部的和下部的子开关借助内部的负载连接元件彼此符合电路要求(schaltungsgerecht)地连接,并且其中,子单元具有不同电势的负载接合元件,所述负载接合元件面式地构造并且在它们的延伸部上以构造成部分堆栈的方式紧邻地布置。
不言而喻的是,内部的负载连接元件是指至少一个内部的负载连接元件。
对于“半导体开关”的概念应在此处以及下文中理解为:每个子开关通过恰好一个能开关的功率半导体来构造而不是通过多个并联联接的能开关的功率半导体来构造。然而,在采用多级拓扑的开关装置中半导体开关可以构造为多个串联联接的能开关的功率半导体。
对于“局部的堆栈”的概念应在此处以及下文中理解为:负载连接元件在主要的部分之上,尤其在大于负载连接元件的延伸部的80%上彼此紧邻地布置,并且在这个系统中构造彼此相对电绝缘的堆栈。在此,单个的连接元件尤其是实施面式的。
可以是有利的但并非必须的是:每个子单元的负载接合元件都以与其它子单元的负载接合元件电绝缘的方式穿过壳体到达外部,并且在外部所述负载接合元件具有每个子单元自己的接触装置。然而,每个子单元的负载接合元件也可以在壳体内连接共同的外部的负载接合元件。
此外优选的是,相应在子单元的纵边侧上相邻的子单元彼此镜像对称地布置。由此,各个子单元的已经较小的换向电感可以在有间隔的情况下、显而易见地仅部分地消除。
在另一种有利的设计方案中,每个子单元具有一个正直流电压电势和一个负直流电压电势以及一个交流电压电势,并且这些负载电势与负载接合元件符合极性要求()地连接。在此,可以不必在局部的堆栈中将具有交流电压电势的负载接合元件布置在具有正直流电压电势的与具有负直流电压电势的负载接合元件之间,并且在此,负载接合元件分别通过电绝缘的薄膜彼此分隔开。
原则上,每个子单元可以具有自己的基底,或者至少两个或更多的子单元可以具有共同的基底。
此外,至少对于特定的应用情况可以有利的是,各子单元布置有与子开关相邻的电容器,并且该电容器联接在两个直流电压电势之间。这个电容器仅须具有小的电容量,并且应该尽可能地以直接邻近于子开关的方式布置在基底上。
尤其有利的是,较多地选择半导体开关的数量以及由此子开关的数量,与之相反,较低地选择单个半导体开关的电流承载能力。不言而喻的是,在真实的功率半导体模块下必须找到数量和多少之间的折衷。
根据本发明的系统构造有上述的功率半导体模块以及连接这个功率半导体模块的外部连接装置,其中,外部连接装置构造为彼此相互绝缘的导线元件的面式的堆栈,其中,每个导线元件与功率半导体模块的接触装置以及与电容器装置的接合装置符合极性要求地连接,或者其中,外部连接装置具有多个导线对,所述导线对分别把具有子单元的直流电压电势的接触装置与配属于电容器装置的接触装置符合极性要求地连接。
显而易见的是,在此涉及至少一个功率半导体模块以及至少一个电容器装置。
可以理解的是,为了实现改进,本发明的不同设计方案可以单独地或以任意的组合的形式实现。尤其上述提到的以及描述的特征,不仅能在给出的组合中,而且能在其它组合中或者独自地被采用,而不超出本发明的范围。
本发明的优点正是在于,通过划分成子单元以及所述子单元的并联联接,各个子单元联结得到它们的总电流。根据用于并联联接的电感的加和规则,得到小于子单元的单个电感的功率半导体模块的总电感。
附图说明
本发明其它的描述、有利的细节和特征由对在图1至图7中示出的部件或根据本发明的系统的实施例的说明得出。其中:
图1以俯视图示出子单元的第一设计方案;
图2示出沿着线A-A穿过根据图1的子单元的剖面图;
图3示出沿着线B-B穿过根据图1的子单元的剖面图;
图4以俯视图示出子单元的第二设计方案;
图5以俯视图示意性地示出根据本发明的功率半导体模块的基底平面;
图6以剖面图侧向地示出根据图5的功率半导体模块和根据本发明的系统;
图7以在壳体上的俯视图示出根据图5的功率半导体模块。
具体实施方式
图1以俯视图示出子单元30的第一设计方案。示出了在本领域中常见(fachüblich)的基底300,该基底具有在其上布置的不同电势的导体线路302。第一上部半导体开关32布置在引导正直流电压电势的第一导体线路302上并且导电连接。这个以及每个此后提到的开关32、34可以是金属氧化物场效应晶体管、反向封锁的绝缘栅双极型晶体管、或者如这里示出的具有反并联联接的二极管322、342(所谓的续流二极管)的绝缘栅双极型晶体管320、340。当四个器件棋盘交错式地布置在基底上时,在半导体开关32、34的设计方案中,作为具有反并联联接的续流二极管的绝缘栅双极型晶体管是特别优选的。在这种情况下,得到特别短的换向路径、以及因此小的电流环路面积、以及因此又是非常小的换向电感。
此外,负载接合元件50借助其附属接触脚502与导体线路302导电连接,为此,接触脚502布置在导体线路302上。开关装置的正电势配属给所述负载接合元件50。这个以及每个此后提到的具有导电连接的系统能够以在本领域中常见的方式构造为压力接触连接、钎焊连接、焊接连接、粘接连接或烧结连接。
第二下部半导体开关34布置在引导交流电压电势的第二导体线路304上并且导电连接。所述第二导体线路304借助内部负载连接元件40与第一半导体开关32的布置在背离基底侧上的接触面连接。所述内部的负载连接元件40可以构造为各自独立的金属成形体400、引线复合连接体402、或未示出的薄膜式连接体。此外,配属于负载接合元件52的接触脚522布置在导体线路304上并且导电连接。开关装置的交流电压电势配属给所述负载接合元件52。
在第二半导体开关34(确切地说其由绝缘栅双极型晶体管340和续流二极管342组成)的布置在背离基底300一侧的接触面上布置有配属于负载接合元件54的接触脚542,并且该第二半导体开关与该接触脚导电连接。开关装置的负电势配属给所述负载接合元件54。
图2示出沿着直线A-A穿过根据图1的子单元30的剖面图。再次示出了由绝缘材料体306(带有布置在其上的导体线路302、304)制成的基底300以及子单元30的负载接合元件50、52、54,在此处,负载接合元件至少区段式地组成局部的堆栈5。在此,堆栈5具有正直流电压电势、交流电压电势、负直流电压电势的顺序。然而中央的是,所有的负载接合元件50、52、54紧邻地并且在理想情况下是面式地并且以最小厚度(然而是足够的厚度以便具有所需的电流承载能力)地构造。
在此,分别配属于负载接合元件50、52的接触脚502、522较厚地构造,一方面是出于电流承载能力的原因,为了具有与相应负载接合元件的随后的延伸部相同的横截面积,另一方面是为了简化与导体线路302、304的机械式且导电的连接的构造。
在所述区域中,在其中出于绝缘的原因需要在负载接合元件50、52、54之间的附加绝缘,该附加绝缘利用绝缘的塑料材料薄膜56、58来构造。
图3示出沿着直线B-B穿过根据图1的子单元30的剖面图。同样示出了所谓的在基底上布置有导体线路302、304(其上布置有半导体开关32、34)的基底300、以及如上文所述的子单元30的负载接合元件50、52、54。重要的是,在该示图中是具有负直流电压电势的负载接合元件54,该负载接合元件54与半导体开关34的接触面直接连接。
图4以俯视图示出子单元30的第二设计方案。这个子单元以如下方式区别于根据图1的子单元:该子单元具有两个另外的导体线路308,二者都引导负的直流电压电势。因此,借助配属的接触部位两个连接与配属的负载接合元件54以布置在导体线路308上且导电的方式连接。
此外,所述导体线路308借助引线复合连接体404与下部半导体开关34的所述接触面连接,所述接触面布置在半导体开关的背离基底侧上。
在此,负载接合元件50、52、54不具有被明确构造的接触脚。确切地说,负载接合元件扁平(stumpf)地布置在配属的导体线路上并且导电连接,其中每个这样的连接可以具有多个接触部位。
此外子单元30的第二设计方案具有电容器6,该电容器电联接在两个直流电压电势之间。为此,电容器6通过另外单独的导体线路308’与负的直流电压电势连接并且通过导体线路302与正的直流电压电势连接,并且该电容器6直接布置在基底300上。
图5以俯视图示意性地示出根据本发明的功率半导体模块1的基底平面。示出了壳体2以及六个例如根据图1或图4彼此相互电绝缘的子单元30,这些子单元分别具有半桥电路。因此,在子单元30的相应的连接下,整个的功率半导体模块1具有采用半桥拓扑形式的开关装置3。为此,每个子单元30都具有自己的负载连接元件,该负载连接元件构造局部式的堆栈5。
此外,仅示意性地示出从上部向下部的子开关或从下部向上部的子开关换向的电流路径36、38。在此,根据本发明的功率半导体模块1的优点明显,也就是,非常小的电流环路面积,以及因此优点直接为与之相关的电感,在此为换向电感。其它的电流环路面积还通过负载接合元件得到,然而,在上述实施方案中这些面积和由此产生的电感相对现有技术也较小。
通过相应在子单元的纵边侧上相邻的子单元30彼此镜像对称的布置,实现换向电感的其它改进。借助在子单元30的相应角上的相应凹部示出所述对称。通过所述对称的设计方案部分地消除了相邻的子单元30的磁场。利用相邻的子单元30的数量可以继续提高上述改进。
根据本发明,具有例如120A电流负载能力的功率半导体模块1可以具有六个子单元30。于是,尽管一个子单元30的换向电感在2nH和4nH之间,但是由根据本发明的结构可以实现使得整个功率半导体模块1的换向电感小于1nH。
图6以剖面图侧向示出具有根据图5的功率半导体模块1的根据本发明的系统。再次示出了具有可以构造为冷却体的基板20的壳体2,以及示意性地示出具有半导体开关32、34的基底300。在此导体线路和内部连接元件没有详细示出。
每个子单元30的负载接合元件50、52、54从各自基底300伸出,在负载接合元件的延伸部中具有局部的堆栈5,并且从壳体2中穿过配属的空隙到达外部。在此处存在有每个子单元30自己的负载接合元件50、52、54的接触装置504、544,所述接触装置例如可以设计为压入接触件,或以其它在本领域中常见的方式来设计。
这些接触装置504、544用于尤其是与外部的连接装置8的连接,该外部连接装置本身使得功率半导体模块1或多个功率半导体模块与一个或多个电容器装置7连接。例如,这些外部连接装置8构造为具有彼此相对电绝缘的导线元件80、84的低电感的、面式母线,其中导线元件80具有正的直流电压电势并且导线元件84具有负的直流电压电势。
图7以在壳体2上侧的俯视图示出根据图5的功率半导体模块1,其中,此处示出每个子单元自己的接触装置504、524、544。
Claims (10)
1.一种功率半导体模块(1),所述功率半导体模块具有壳体(2)以及至少一个采用具有上部和下部开关的半桥拓扑形式的开关装置(3),其中,所述开关装置(3)本身由多个同样采用半桥拓扑形式的、彼此相对电绝缘的子单元(30)构成,其中,每个所述子单元(30)具有分别构造为恰好一个半导体开关的上部和下部子开关(32、34),其中,上部的和下部的子开关(32、34)借助内部的负载连接元件(40)彼此符合电路要求地连接,并且其中,所述子单元(30)具有不同电势的负载接合元件(50、52、54),所述负载接合元件面式地构造并且在它们的延伸部上以构造成部分堆栈(5)的方式紧邻地布置。
2.根据权利要求1所述的功率半导体模块,其中,每个子单元(30)的负载接合元件(50、52、54)都以与其它子单元的负载接合元件电绝缘的方式穿过壳体(3)伸向外部,并且在外部所述负载接合元件具有每个子单元(30)自己的接触装置(504、524、544)。
3.根据权利要求1所述的功率半导体模块,其中,相应在其纵边侧上相邻的子单元(30)彼此镜像对称地布置。
4.根据权利要求1所述的功率半导体模块,其中,每个子单元(30)具有正直流电压电势和负直流电压电势以及交流电压电势,并且这些负载电势与负载接合元件(50、52、54)符合极性要求地连接。
5.根据权利要求4所述的功率半导体模块,其中,在所述局部的堆栈(5)中将具有交流电压电势的所述负载接合元件(52)布置在具有正直流电压电势的与具有负直流电压电势的所述负载接合元件(50、54)之间,并且在此,负载接合元件分别通过电绝缘的薄膜(56、58)彼此分隔开。
6.根据权利要求1所述的功率半导体模块,其中,所述内部的负载连接元件(40)构造为各自独立的金属成形体(400)、引线复合连接体(402、404)或薄膜连接体。
7.根据权利要求1所述的功率半导体模块,其中,每个子单元(30)都具有自己的基底(300),或至少两个子单元(30)具有共同的基底。
8.根据权利要求2所述的功率半导体模块,其中,所述接触装置(504、524、544)构造为压入接触件。
9.根据权利要求1所述的功率半导体模块,其中,各子单元(30)布置有与所述子开关(32、34)相邻的电容器(6),并且所述电容器联接在两个直流电压电势之间。
10.一种系统(100),所述系统具有电容器装置(7)、根据上述权利要求中任意一项所述的功率半导体模块(1)、以及连接所述功率半导体模块(1)的外部连接装置(8),其中,外部连接装置(8)构造为彼此相互绝缘的导线元件(80、84)的面式的堆栈,其中,每个导线元件(80、84)与功率半导体模块(1)的接触装置(504、544)以及与电容器装置(7)的接合装置符合极性要求地连接,或者其中,外部连接装置具有多个导线对,所述导线对分别把具有子单元(30)的直流电压电势的接触装置(504、544)与电容器装置(7)的配属的接触装置符合极性要求地连接。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE201310104522 DE102013104522B3 (de) | 2013-05-03 | 2013-05-03 | Leistungshalbleitermodul mit Subeinheiten und Anordnung hiermit |
DE102013104522.7 | 2013-05-03 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104134652A true CN104134652A (zh) | 2014-11-05 |
CN104134652B CN104134652B (zh) | 2019-04-23 |
Family
ID=50879070
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410180727.2A Active CN104134652B (zh) | 2013-05-03 | 2014-04-30 | 具有子单元的功率半导体模块及对应的系统 |
Country Status (3)
Country | Link |
---|---|
KR (1) | KR20140131279A (zh) |
CN (1) | CN104134652B (zh) |
DE (1) | DE102013104522B3 (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108736739A (zh) * | 2017-04-20 | 2018-11-02 | 英飞凌科技股份有限公司 | 具有改进几何形状的堆叠连接板的功率半导体装置 |
CN111033734A (zh) * | 2017-06-06 | 2020-04-17 | 宝马股份公司 | 功率转换器模块及其制造方法 |
US11935875B2 (en) * | 2021-11-30 | 2024-03-19 | Infineon Technologies Ag | Power module layout for symmetric switching and temperature sensing |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102012218868B3 (de) * | 2012-10-17 | 2013-11-07 | Semikron Elektronik Gmbh & Co. Kg | Leistungshalbleitermodul |
DE102017117665B4 (de) * | 2017-08-03 | 2020-04-30 | Semikron Elektronik Gmbh & Co. Kg | Leistungshalbleitermodul mit einem eine bauliche Einheit bildenden elektrischen Verbindungselement und mit einem elektrischen ersten Bauelement |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1336689A (zh) * | 2000-08-01 | 2002-02-20 | 塞米克朗电子有限公司 | 小电感的电路结构 |
CN101399262A (zh) * | 2007-09-27 | 2009-04-01 | 英飞凌科技股份公司 | 功率半导体装置 |
CN101866906A (zh) * | 2009-04-16 | 2010-10-20 | 赛米控电子股份有限公司 | 用于降低功率电子系统中的干扰辐射的装置 |
CN102110680A (zh) * | 2009-10-30 | 2011-06-29 | 通用电气公司 | 具有降低电感的功率模块组件 |
CN102364345A (zh) * | 2010-06-21 | 2012-02-29 | 英飞凌科技股份有限公司 | 具有并联电阻的电路装置 |
CN102800637A (zh) * | 2011-05-24 | 2012-11-28 | 赛米控电子股份有限公司 | 具有第一和第二子系统的连接设备的功率电子系统 |
CN102956593A (zh) * | 2011-08-12 | 2013-03-06 | 赛米控电子股份有限公司 | 带有开关装置和触发装置的电力电子系统 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3937045A1 (de) * | 1989-11-07 | 1991-05-08 | Abb Ixys Semiconductor Gmbh | Leistungshalbleitermodul |
DE102005061016B4 (de) * | 2005-12-19 | 2018-12-06 | Infineon Technologies Ag | Leistungshalbleitermodul, Verfahren zu seiner Herstellung und Verwendung in einem Schaltnetzteil |
DE102012202765B3 (de) * | 2012-02-23 | 2013-04-18 | Semikron Elektronik Gmbh & Co. Kg | Halbleitermodul |
DE102012218868B3 (de) * | 2012-10-17 | 2013-11-07 | Semikron Elektronik Gmbh & Co. Kg | Leistungshalbleitermodul |
-
2013
- 2013-05-03 DE DE201310104522 patent/DE102013104522B3/de active Active
-
2014
- 2014-04-30 CN CN201410180727.2A patent/CN104134652B/zh active Active
- 2014-05-01 KR KR1020140053073A patent/KR20140131279A/ko not_active Application Discontinuation
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1336689A (zh) * | 2000-08-01 | 2002-02-20 | 塞米克朗电子有限公司 | 小电感的电路结构 |
CN101399262A (zh) * | 2007-09-27 | 2009-04-01 | 英飞凌科技股份公司 | 功率半导体装置 |
CN101866906A (zh) * | 2009-04-16 | 2010-10-20 | 赛米控电子股份有限公司 | 用于降低功率电子系统中的干扰辐射的装置 |
CN102110680A (zh) * | 2009-10-30 | 2011-06-29 | 通用电气公司 | 具有降低电感的功率模块组件 |
CN102364345A (zh) * | 2010-06-21 | 2012-02-29 | 英飞凌科技股份有限公司 | 具有并联电阻的电路装置 |
CN102800637A (zh) * | 2011-05-24 | 2012-11-28 | 赛米控电子股份有限公司 | 具有第一和第二子系统的连接设备的功率电子系统 |
CN102956593A (zh) * | 2011-08-12 | 2013-03-06 | 赛米控电子股份有限公司 | 带有开关装置和触发装置的电力电子系统 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108736739A (zh) * | 2017-04-20 | 2018-11-02 | 英飞凌科技股份有限公司 | 具有改进几何形状的堆叠连接板的功率半导体装置 |
CN108736739B (zh) * | 2017-04-20 | 2023-06-20 | 英飞凌科技股份有限公司 | 具有改进几何形状的堆叠连接板的功率半导体装置 |
CN111033734A (zh) * | 2017-06-06 | 2020-04-17 | 宝马股份公司 | 功率转换器模块及其制造方法 |
CN111033734B (zh) * | 2017-06-06 | 2023-09-15 | 宝马股份公司 | 功率转换器模块及其制造方法 |
US11935875B2 (en) * | 2021-11-30 | 2024-03-19 | Infineon Technologies Ag | Power module layout for symmetric switching and temperature sensing |
Also Published As
Publication number | Publication date |
---|---|
KR20140131279A (ko) | 2014-11-12 |
DE102013104522B3 (de) | 2014-06-26 |
CN104134652B (zh) | 2019-04-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8902612B2 (en) | Power conversion apparatus | |
CN203165891U (zh) | 半导体模块 | |
CN204516758U (zh) | 具低电感配置内部负载和辅助连接装置的功率半导体模块 | |
US9871465B2 (en) | Semiconductor device including positive, negative and intermediate potential conductor plates | |
CN102956610B (zh) | 半导体装置 | |
AU2007232027B2 (en) | Power conversion device and fabricating method for the same | |
CN206271705U (zh) | 包括多个电势面的功率电子开关器件 | |
CN102184914B (zh) | 功率半导体模块和用于运行功率半导体模块的方法 | |
CN106130363B (zh) | 电力变换装置以及铁道车辆 | |
US9391055B2 (en) | Power module having stacked substrates arranged to provide tightly-coupled source and return current paths | |
CN102915987B (zh) | 半导体装置 | |
CN104134652A (zh) | 具有子单元的功率半导体模块及对应的系统 | |
CN105742278A (zh) | 半导体装置 | |
US9130095B2 (en) | Substrate for power module having uniform parallel switching characteristic and power module including the same | |
KR101691707B1 (ko) | 스위칭소자 유닛 | |
JP2013219892A (ja) | 電力変換装置 | |
US20150326221A1 (en) | Switching element unit | |
CN109983554B (zh) | 电容器、尤其是用于多相系统的中间电路电容器 | |
CN1917203B (zh) | 具有线路元件的功率半导体模块 | |
US10347758B2 (en) | Semiconductor packaging structure and semiconductor power device thereof | |
CN104681502A (zh) | 大功率半导体装置 | |
CN105593989A (zh) | 具有缓冲器-电容器的用于变换器的半导体堆叠 | |
US9627955B2 (en) | Semiconductor module | |
CN107294357B (zh) | 三电平转换器布置和用于其的相连布置 | |
US20180351498A1 (en) | Power Module for an Electric Motor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |