CN102956610B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN102956610B
CN102956610B CN201210291561.2A CN201210291561A CN102956610B CN 102956610 B CN102956610 B CN 102956610B CN 201210291561 A CN201210291561 A CN 201210291561A CN 102956610 B CN102956610 B CN 102956610B
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carrier
sub
semiconductor
semiconductor switch
metallization layer
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CN102956610A (zh
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丹尼尔·多梅斯
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明涉及一种半导体装置，其包括电路载体、结合配线以及至少N个半桥电路。N是总计至少为1的整数。该电路载体包括第一金属层、第二金属化层、配置在第一金属层和第二金属化层之间的中间金属化层、配置在中间金属层和第二金属化层之间的第一绝缘层以及配置在第一金属层和中间金属化层之间的第二绝缘层。各半桥电路包括第一电路节点、第二电路节点和第三电路节点、可控的第一半导体开关和可控的第二半导体开关。各半桥电路的第一半导体开关和第二半导体开关配置在第一金属化层的背向第二绝缘层的一侧。结合配线在第一结合位置直接结合到中间金属化层。

Description

半导体装置
技术领域
本申请的实施方式涉及半导体装置（semiconductor arrangement，半导体配置）。
背景技术
在许多半导体装置中，两个半导体开关串联连接从而形成半桥。一个、两个、三个或更多这样的半桥能够用于电机的电源、整流器、电源转换器等中。
在半桥中，至少两个可控功率半导体开关串联连接。在两个可控功率半导体开关之间，串联连接包括电路节点。在运行期间，串联连接被连接至正和负电源电位之间的电源电压。电连接至负电源电位的功率半导体开关通常称为“低侧开关”。相应地，电连接至正电源电位的功率半导体开关通常称为“高侧开关”。在运行期间，在电路节点处的电压在基本上等于正和负电源电位的两个电位之间交替。
在许多现有的半导体装置中，金属化的陶瓷基底用以实现该装置的至少一些电连接。功率半导体开关被配置在基底的顶侧上。底侧可热并且电耦接至散热器。与绝缘陶瓷一起，金属化的陶瓷基底相对于施加到散热器的地电位形成电容。根据在电路节点处的交流电压的幅度和频率，发生对该电容连续地充电和放电的位移电流。由于在装置中不可避免的介电常数（inductivity，电容率）中的位移电流，所以通过这样的介电常数的电压降可能引起不希望有的EMI（电磁干扰）。
为了减小介电常数，陶瓷基底可设计为具有将基底的不同金属化层电互连的通孔的多层基底。这些通孔允许具有减小阻抗的短路电连接。然而，在陶瓷中具有通孔的陶瓷多层基底是相当昂贵的。
因此，需要即使在陶瓷中没有这样的通孔，也具有低介电常数的半导体装置。
发明内容
根据一个方面，一种半导体装置包括电路载体（carrier）、结合配线以及至少N个半桥电路。N是总计至少为1的整数。电路载体包括第一金属化层、第二金属化层、配置在第一金属化层和第二金属化层之间的中间金属化层、配置在中间金属化层和第二金属化层之间的第一绝缘层、以及配置在第一金属化层和中间金属化层之间的第二绝缘层。各个半桥电路包括第一电路节点、第二电路节点以及第三电路节点、可控的第一半导体开关和可控的第二半导体开关。可控的第一半导体开关具有电连接至第一电路节点的第一主接触、电连接至第三电路节点的第二主接触、以及用于控制第一主接触和第二主接触之间的电流的栅极接触。相应地，可控的第二半导体开关具有电连接至第二电路节点的第一主接触、电连接至第三电路节点的第二主接触、以及用于控制第一主接触和第二主接触之间的电流的栅极接触。各个半桥电路的第一半导体开关以及第二半导体开关被配置在第一金属化层的背向第二绝缘层的一侧上。结合配线在第一结合位置直接结合到中间金属化层。
附图说明
参考以下附图和说明能够更好地理解本申请的实施方式。附图中的部件不一定按比例，而是将重点放在示出各实施方式的原理上。此外，在图中，相似的参考标号表示相应的部分。在附图中：
图1A是由两个MOSFET的串联连接形成的半桥的电路图，其中，接收“DC+”的端子为图4和图6中的第一端子71或图5中的第二端子72，接收“DC-”的端子为图5中的第一端子71或图4和图6中的第二端子72。
图1B是由两个IBGT的串联连接形成的半桥的电路图，其中，接收“DC+”的端子为图4和图6中的第一端子71或图5中的第二端子72，接收“DC-”的端子为图5中的第一端子71或图4和图6中的第二端子72。
图2是由如图1A中所示的两个半桥形成的二相桥的电路图，其中，接收“DC+”的端子为图4和图6中的第一端子71或图5中的第二端子72，接收“DC-”的端子为图5中的第一端子71或图4和图6中的第二端子72。
图3是由如图1A中所示的三个半桥形成的三相桥的电路图，其中，接收“DC+”的端子为图4和图6中的第一端子71或图5中的第二端子72，接收“DC-”的端子为图5中的第一端子71或图4和图6中的第二端子72。
图4示出了根据第一实施方式的包括多个半桥的半导体装置的垂直截面图。
图5示出了根据第二实施方式的包括多个半桥的半导体装置的垂直截面图。
图6示出了根据第三实施方式的包括多个半桥的半导体装置的垂直截面图。
图7示出了根据第四实施方式的包括多个半桥的半导体装置的垂直截面图。
具体实施方式
在下面的详细说明中，将参考附图，这些附图构成说明书的一部分，并且通过实际应用本申请的具体实施方式来示出。在这点上，参考所述附图的方向来使用诸如“顶”、“底”、“前”、“后”、“头”、“尾”等的方向性术语。因为实施方式的部件能够以许多不同的方向放置，所以方向性术语用于说明的目的而不是限制。应理解，在不背离本申请的范围的前提下，可使用其他实施方式并且可做出结构的或逻辑的改变。因此，以下详述不应当视为具有限制的涵义，而本申请的范围通过所附的权利要求来定义。应理解，除非另有特别注明，本文描述的各种示例性实施方式的特征可相互组合。
现参考图1A，示出了具有串联连接的可控的第一半导体开关1（在第一半导体芯片中实现的“低侧开关”，LS）与可控的第二半导体开关2（在第二半导体芯片中实现的“高侧开关”，HS）的半桥I的电路图。半桥电路具有第一电路节点31、第二电路节点32和第三电路节点33。
可控的第一半导体开关1具有电连接至第一电路节点31的第一主接触11、电连接至第三电路节点33的第二主接触12、以及用于控制第一主接触11和第二主接触12之间的电流的栅极接触13。可控的第二半导体开关2具有电连接至第二电路节点32的第一主接触21、电连接至第三电路节点33的第二主接触22、以及用于控制第一主接触21和第二主接触22之间的电流的栅极接触23。
第一半导体开关1的栅极接触13可简单地用以切换在第一主接触11和第二主接触12之间的电流的接通或断开。然而，栅极接触13也可用于将第一主接触11和第二主接触12之间的电流调节至在第一半导体开关1被断开的情况下的大致0A（安培）到在第一半导体开关1被接通而产生的最大电流之间的任意值。短语“大致0A”旨在表示“0安培，除了不可避免的残余电流”。
相应地，第二半导体开关12的栅极接触23可简单地用以切换在第一主接触21和第二主接触22之间的电流的接通或断开。然而，栅极接触23也可用于将第一主接触21和第二主接触22之间的电流调节至在第二半导体开关2被断开的情况下的大致0A（安培）到在第二半导体开关2被接通而产生的最大电流之间的任意值。
在许多应用中，半桥可被提供以电力，例如，DC环节电压（DC linkvoltage）。至此，第一电路节点31能够被提供以负电源电位（DC-）并且第二电路节点32被提供以正电源电位（DC+）。为分别接收正电源电位DC+和负电源电位DC-，该配置包括第一端子71和第二端子72。应注意，在一些实施方式中，第一端子71用以接收正电源电位DC+而第二端子72用以接收负电源电位DC-，而在另一实施方式中，第一端子71用以接收负电源电位DC-，而第二端子72用以接收正电源电位DC+。
在运行期间，第一和第二半导体开关1、2交替切换接通和断开。即，在第一切换状态中，如果第一半导体开关1处于接通状态，则第二半导体开关2处于断开状态。相应地，在第二切换状态中，如果第二半导体开关2处于接通状态，则第一半导体开关1处于断开状态。当从第一切换状态切换到第二切换状态时，或相反地，从第二切换状态切换到第一切换状态时，为了避免DC+和DC-之间的短路，或在连接至第三电路节点33的负载将被断开的情况下，在第一和第二切换状态之间存在第一和第二半导体开关1、2两者均短时间断开的中间状态。因此，在半桥I的正常切换操作期间，第三电路节点33交替地分别连接至正电源电压DC+或负电源电压DC-。
在图1A的半桥I中，可控的第一和第二半导体开关1、2是MOSFET。代替或除MOSFET外，可使用如IGBT、JFET、半导体闸流管等其他任何类型的可控的第一和/或第二半导体开关1、2。第一和第二半导体开关1、2可以是相同的类型，即，两个MOSFET、两个IGBT、两个JFET等。或者，也可以串联连接任何不同类型的可控的半导体开关1和2。
此外，在可控的半导体开关1和2是场效应晶体管的情况下，可控的半导体开关1和2两者都可以都是n沟道型，或都是p沟道型。然而，也可以使用n沟道型作为第一半导体开关1，而使用p沟道型作为第二半导体开关2，或，反之亦然，使用p沟道型作为第一半导体开关1，而使用n沟道型作为第二半导体开关2。
作为半桥的进一步的示例，图1B示出了包括串联连接的两个IGBT的半桥。
图2是由连接至公共端子71、72的两个半桥I和II形成的二相桥的电路图。相应地，图3是由连接至公共端子71、72的三个半桥I、II和III形成的三相桥的电路图。在具有至少一个半桥I、II、III的任何装置中，公共端子71、72用以公共地连接所有半桥I、II、III以提供电源电位DC+和DC-。
图2的每个半桥I和II以及图3的每个半桥I、II和III可具有如图1A所示的半桥I的结构。或者，二相桥或三相桥可使用根据图1B的两个或三个半桥而不是根据图1A的半桥来形成。此外，也可使用如参考图1A和1B所描述的任何其他可控的半导体开关的任意串联连接形成的半桥。
在图1A和图1B的电路配置中，N=1。在图2的电路配置中，N=2，以及在图3的电路配置中，N=3。然而，N也可大于或等于4。通常，N是N≥1、N≥2或N≥3的整数。
如果该电路配置包括至少两个半桥I、II、III（N≥2），该电路配置的所有半桥I、II、III的第一电路节点31可彼此电连接，并且该电路配置的所有半桥I、II、III的第二电路节点32可彼此电连接。这允许该电路配置的所有半桥I、II、III连接到公共电源电位DC+和DC-。以同样的方式，通过增加一个或多个额外的半桥，可实现简单地包括四个以上这样的半桥的电路配置。每个额外的半桥可具有上述的任何半桥结构，并连接至公共的第一和第二电源端子71和72。
图4是根据第一实施方式的包括至少两个半桥I、II、III的半导体装置的垂直截面图。该装置的电路对应于参考图3所描述的电路图。该半导体装置包括电路载体5，其具有第一金属化层41、第二金属化层82、配置在第一金属化层41和第二金属化层82之间的中间金属化层81、配置在中间金属化层81和第二金属化层82之间的第一绝缘层83、以及配置在第一金属41和中间金属化层81之间的第二绝缘层43。
电路载体5包括配置在公共基底载体8上的多个子载体9。公共基底载体8包括中间金属化层81、第二金属化层82以及第一绝缘层83。中间金属化层81和第二金属化层82彼此电绝缘。中间金属化层81可以是封闭的（闭合的）、非穿孔的金属层。为了改善来自第一和第二半导体开关1、2的热耗散，散热器可附装在第二金属化层82的背向中间金属化层81的一侧。
第一绝缘层83是封闭的连续介电层并且没有导电性的通孔。子载体9被配置在中间金属化层81的背向第二金属化层82的一侧。每个子载体9包括第一金属91、电介质93、以及可选的第二金属92。每个第一金属91可具有带导线的导电体结构。所有子载体9的第一金属91共同形成第一金属化层41。相应地，所有子载体9的电介质93共同形成第二绝缘层43。
根据一个实施方式，各个半桥电路I、II、III被配置在不同个子载体9上。特别地，各个半桥电路I、II、III的第一和第二半导体开关1、2都可被配置在各半桥电路I、II、III的公共子载体9上。至此，可作为半导体芯片的第一和第二半导体开关1、2可使用连接层15（例如，焊接层、包括像银等的贵金属的熔结层、或粘合层）被焊接、熔结或者导电地粘附到各个子载体9的第一金属91。因为每个半导体芯片包括具有第一和第二主接触以及栅极接触的第一或第二半导体开关，所以每个半导体芯片需要三个接触。
具有基底基板8和一个或多个单独的子载体9的装置可通过装备具有各个第一和第二半导体芯片1、2以及可选地具有各个第二连接片（connection lug）72的各个子载体9来制造。还可选地，第一和第二半导体芯片1、2可使用类似结合配线、带、金属片等导电连接元件来导电互连。在子载体9安装在基底载体8上之前，用参考标号“7”表示的所有连接元件可以可选地安装在各个的子载体9上。在已经预装备至少一些所提到的元件后，子载体9可安装在基底载体8上。至此，例如通过焊接、熔结或者粘附，可将各个的子载体9的第二金属92接合到中间金属化层81。作为这样的连接处理的结果，各个连接层45将子载体9接合到中间金属化层81。然而，子载体9和中间金属化层81之间的连接层45是可选的。取而代之，例如通过直接铜对铜的结合，可将子载体的第二金属92直接地接合到中间金属化层81。
可选地，子载体9可首先安装到公共基底载体8，并接着使用如上说明的连接层45装备有各个元件，或者没有额外的连接层45而直接铜对铜结合。
应注意，在图4以及随后的附图中，栅极接触的电连接被藏匿了。然而，在任何实施方式中，半导体芯片的栅极接触可被配置在半导体芯片的面向电路载体5的一侧，或者背向电路载体5的一侧。在具有包括第一半导体开关1的第一半导体芯片以及具有包括第二半导体开关2的第二半导体芯片的装置中，其中第一和第二半导体开关1和2形成半桥电路I、II、III，第一和第二半导体芯片可用这样的方式被配置在电路载体5上：第一和第二半导体开关1、2两者的栅极接触13、23都被配置在第一和第二半导体芯片各自的面向电路载体5的一侧，或，可选地，可用这样的方法：第一和第二半导体开关1、2两者的栅极接触13、23都被配置在第一和第二半导体芯片各自的背向电路载体5的一侧。还有可能第一半导体开关1的栅极接触13被配置在第一半导体芯片的面向电路载体5的一侧，而第二半导体开关2的栅极接触23被配置在第二半导体芯片的背向电路载体5的一侧。反之亦然，可能第一半导体开关1的栅极接触13被配置在第一半导体芯片的背向电路载体5的一侧，而第二半导体开关2的栅极接触23被配置在第二半导体芯片的面向电路载体5的一侧。任何所述的可选方式可应用于该配置的任何半桥电路I、II、III，而与该装置的其他半桥电路的结构无关。
还需注意的是，这样的第一和第二半导体芯片中的每一个可以是具有分别被配置在各个半导体芯片1、2的相对侧上的第一和第二主接触11/12和21/22的“竖直”半导体芯片。然而，在其他实施方式中，也可使用“横向”半导体芯片。
在图4的装置中，中间金属化层81用以将正电源电压DC+分配给各个半桥电路I、II、III。为此，正电源电压DC+可经由电连接至中间金属化层81的第一连接片71来提供。至此，使用连接层75（其例如可以是焊接层、或包括像银等的贵金属的熔结层），第一连接片71可焊接或熔结到中间金属化层81。可选地，第一连接片71可直接焊接至中间金属化层81。在这种情况下，不需要连接层75。
为了将各个半桥电路I，、II、III电连接到中间金属化层81，可使用结合配线6。例如，结合配线6可由铜或铝、或至少90原子%的铜、或至少90原子%的铝来制成。
如图4中所示，这样的结合配线6可在第一结合位置61结合到中间金属化层81，并且可选地在第二结合位置62结合到其中一个子载体9的第一金属91。在第一结合位置61，结合配线6的材料与中间金属化层81的材料物理接触。相应地，在第二结合位置62，结合配线6的材料与第一金属化层41的材料物理接触。
在两个以上的子载体9的情况下，至少一个第一结合位置61可位于两个相邻的子载体9之间。两个相邻子载体9各自可彼此隔开。相应的距离是d。例如，距离d可小于或等于30mm和/或至少3mm。
在图4中说明的实施方式中，中间金属化层81电连接至第二半导体开关2的第一主接触21，即，连接至各个半桥电路I、I、III的第二电路节点32。第二半导体开关2的第一主接触21位于第二半导体开关2的面向电路载体5的一侧。
为了将单个半桥电路I、II、III连接至负电源电位DC-，设置了第二连接片72。各个第二连接片72电连接至另一个子载体9的第一半导体开关1的第一主接触11，即，连接至各个半桥电路I、II、III的第一电路节点31。至此，第二连接片72可使用连接层75（其例如可以是焊接层或包括像银等的贵金属的熔结层）而焊接或熔结到各个的子载体9的第一金属91。或者，第二连接片72可直接焊接至各个的子载体9的第一金属91。在图4中，第一半导体开关1的第一主接触11位于第一半导体开关1的背向电路载体5的一侧。为了将第二连接片72电互连至在该实施方式中是DC-的公共电源电位，设置了电连接第二连接片72的汇流线72a。
此外，对每一个半桥电路I、II、III，设置第三连接片73。每个第三连接片73电连接至另一个半桥电路I、II、III的第三电路节点33，即，电连接至另一个子载体9。至此，第三连接片73可使用连接层75（其例如可以是焊接层或包括像银等的贵金属的熔结层）而焊接或熔结到各个子载体9的第一金属91。或者，第三连接片73可直接焊接至第一金属化层41。在图4中，第一半导体开关1的第一主接触11位于第一半导体开关1的背向电路载体5的一侧。第三连接片73用作相位输出Ph。例如，相位输出Ph可连接至像电机等的负载。
根据在图5中所示的另一实施方式，中间金属化层81可选地用以将负电源电压DC-分配给各个半桥电路I、II、III。在这种情况下，负电源电压DC-可经由参考图4所述的电连接至中间金属化层81的第一连接片71来提供。为了将各个半桥电路I、II、III电连接至中间金属化层81，可使用结合配线6。如图5中所示，这样的结合配线6可在第一结合位置61结合到中间金属化层81，并且可选地在第二结合位置62结合到第一半导体开关1的背向电路载体5的一侧。
在有两个以上子载体9的情况下，至少一个第一结合位置61可位于两个相邻的子载体9之间。两个相邻的子载体9各自可彼此隔开相距距离d，该距离可与之前参考图4提到的范围相同。
为了将第二连接片72电互连至在该实施方式中是DC+的公共电源电位，设置了电连接第二连接片72的汇流线72a。
图6中所示的另一实施方式与图4的实施方式不同仅仅在于子载体9没有第二金属92（参见图4）。取而代之，各个电介质93直接结合到中间金属化层81并与中间金属化层81物理接触。正如已参考图4所述，子载体9可彼此隔开相距距离d，该距离可与之前参考图4提到的范围相同。
图5的装置可以用同样的方式修改，即，不提供第二金属92和连接层45，各个电介质93可直接结合到中间金属化层81。在图7中示出了其结果。
在任何实施方式中，特别地，在参考附图以上所述的实施方式中，第一金属化层41、第二金属化层82、中间金属化层81和可选的第二金属42可彼此独立地具有以下一个或多个特征的任意组合：
（a）至少0.1mm的厚度。
（b）小于或等于0.8mm的厚度。
（c）由铜制成或包括至少90重量%的铜、或者由铝制成或包括至少90重量%的铝的材料。
这样，在任何实施方式中，特别地，在参考附图如上所述的实施方式中，第一绝缘层83和第二绝缘层43可彼此独立地具有以下一个或多个特征的任意组合：
（a）至少0.2mm的厚度。
（b）小于或等于2mm的厚度
（c）没有导电通孔。
（d）由陶瓷制成的材料。例如，材料可包括以下的一种或多种陶瓷材料或由以下的一种或多种陶瓷材料构成：氧化铝（Al2O3，铝土）；氮化铝（AlN）；氮化硅（Si3N4）；锆石氧化物（ZrO2）；钛酸铝（Al2TiO5）；烧结碳化硅（SSiC）；反应结合碳化硅（SiSiC）。
此外，在具有一个或多个子载体9的特别的实施方式中，子载体9可以是DBC基板（DBC=直接结合铜）、AMB基板（AMB=活性金属铜焊）或DAB基板（DAB=直接铝结合）。在这样的DBC基板中，第二绝缘层43由氧化铝（Al2O3）构成。第一金属41和可选的第二金属42是在高压以及大约1064°C的高温下直接结合到第二绝缘层43的氧化铝的铜层。
相应地，基底基板8可以是DBC基板、AMB基板或DAB基板。在DBC基板的情况下，第一绝缘层83由氧化铝（Al2O3）构成，并且中间金属化层81以及第二金属化层82是在高压以及大约1064°C的高温下直接结合到第一绝缘层83的氧化铝的铜层。
在子载体9没有第二金属92的其他实施方式中，电路载体5可以是多层DBC基底，其中第一绝缘层83和第二绝缘层43由氧化铝构成、其中第一金属化层41和中间金属化层81直接铜结合到第二绝缘层43、以及其中中间金属化层81和第二金属化层82直接铜结合到第一绝缘层83。
空间相关的术语，诸如“在下面”、“以下”、“下部”、“在上方”、“上部”等用于容易描述，以说明一个元件相对于第二元件的位置。除不同于图中所示的那些方向之外，这些术语还旨在包括装置的不同方向。此外，诸如“第一”、“第二”等术语也用以描述各种元件、区域、部分等，并且也不旨在进行限制。在说明书中相似的术语指代相似的元件。
正如本文所使用的，术语“具有”、“包含”、“包括”、“含有”等是开放式的术语，其表示所述的元件或特征的存在，但不排除额外的元件或特征。除非上下文另外明确表明，冠词“一”、“一个”和“该”旨在包括复数以及单数。
通过变形和应用的以上范围，应理解，本发明不受前面的描述所限制，也不受附图所限制。相反，本发明仅由所附权利要求和它们的合法等同物来限制。

Claims (26)

1.一种半导体装置，包括：
电路载体，包括第一金属化层、第二金属化层、配置在所述第一金属化层和所述第二金属化层之间的中间金属化层、配置在所述中间金属化层和所述第二金属化层之间的第一绝缘层、以及配置在所述第一金属化层和所述中间金属化层之间的第二绝缘层；
结合配线；
至少N个半桥电路，其中，N≥1，各个半桥电路包括：
第一电路节点、第二电路节点和第三电路节点；
可控的第一半导体开关，包括电连接至所述第一电路节点的第一主接触、电连接至所述第三电路节点的第二主接触、以及用于控制该第一主接触和该第二主接触之间的电流的栅极接触；
可控的第二半导体开关，包括电连接至所述第二电路节点的第一主接触、电连接至所述第三电路节点的第二主接触、以及用于控制该第一主接触和该第二主接触之间的电流的栅极接触；
其中，
各个所述半桥电路的所述第一半导体开关和所述第二半导体开关被配置在所述第一金属化层的背向所述第二绝缘层的一侧；
所述结合配线在第一结合位置直接结合到所述中间金属化层。
2.根据权利要求1所述的半导体装置，其中，在所述第一结合位置，所述结合配线的材料与所述中间金属化层的材料物理接触。
3.根据权利要求1所述的半导体装置，其中，所述结合配线在第二结合位置直接结合到所述第一金属化层。
4.根据权利要求3所述的半导体装置，其中，在所述第二结合位置，所述结合配线的材料与所述第一金属化层的材料物理接触。
5.根据权利要求1所述的半导体装置，其中，所述结合配线在第二结合位置直接结合到所述第一半导体开关的背向所述电路载体的一侧。
6.根据权利要求1所述的半导体装置，还包括电连接至所述中间金属化层的第一连接片。
7.根据权利要求6所述的半导体装置，其中，所述第一连接片电连接至所述第一半导体开关的第一主接触，或者电连接至所述第二半导体开关的第一主接触。
8.根据权利要求6所述的半导体装置，还包括第二连接片，其中，所述第一连接片电连接至所述第一半导体开关的第一主接触，而所述第二连接片电连接至所述第二半导体开关的第一主接触。
9.根据权利要求8所述的半导体装置，其中，
所述第一连接片电连接至所述第一半导体开关的背向所述电路载体的一侧；以及
所述第二连接片电连接至所述第二半导体开关的面向所述电路载体的一侧。
10.根据权利要求6所述的半导体装置，还包括第二连接片，其中，所述第一连接片电连接至所述第二半导体开关的第一主接触，而所述第二连接片电连接至所述第一半导体开关的第一主接触。
11.根据权利要求10所述的半导体装置，其中，
所述第一连接片电连接至所述第二半导体开关的面向所述电路载体的一侧；以及
所述第二连接片电连接至所述第一半导体开关的背向所述电路载体的一侧。
12.根据权利要求1所述的半导体装置，其中
N≥2或N≥3；
各个所述半桥电路被配置在作为所述电路载体的一部分的N个子载体中的不同个子载体上；
所述N个子载体中的每个包括第一金属和电介质；
所述N个半桥电路中的每个的所述第一半导体开关和所述第二半导体开关都被配置在各个子载体的第一金属的背向所述电介质的一侧；以及
所述第一结合位置位于彼此隔开的两个相邻的子载体之间。
13.根据权利要求12所述的半导体装置，其中，所述N个半桥电路的子载体的第一金属共同形成所述第一金属化层。
14.根据权利要求12所述的半导体装置，还包括连接层，其中，
所述N个子载体中的每个包括第二金属，所述第二金属被配置在各个子载体的电介质的背向所述各个子载体的第一金属的一侧；
所述连接层被配置在所述N个半桥电路中的每个的子载体的第二金属和所述中间金属化层之间，并将所述N个子载体中的每个电连接并且机械接合到所述中间金属化层。
15.根据权利要求12所述的半导体装置，其中，所述N个子载体中的每个的电介质的材料与所述中间金属化层的材料物理接触。
16.根据权利要求12所述的半导体装置，其中，所述两个相邻的子载体之间的距离至少是3mm。
17.根据权利要求12所述的半导体装置，其中，所述两个相邻的子载体之间的距离小于或等于30mm。
18.根据权利要求1所述的半导体装置，其中，所述第一金属化层、所述第二金属化层和所述中间金属化层中的每一个具有至少0.1mm的厚度。
19.根据权利要求1所述的半导体装置，其中，所述第一金属化层、所述第二金属化层和所述中间金属化层中的每一个具有小于或等于0.8mm的厚度。
20.根据权利要求1所述的半导体装置，其中，所述第一金属化层、所述第二金属化层和所述中间金属化层中的每一个
由铜制成；或
包括至少90重量％的铜；或
由铝制成；或
包括至少90重量％的铝。
21.根据权利要求1所述的半导体装置，其中，所述第一绝缘层和所述第二绝缘层中的每个具有至少0.2mm的厚度。
22.根据权利要求1所述的半导体装置，其中，所述第一绝缘层和所述第二绝缘层中的每个具有小于或等于2mm的厚度。
23.根据权利要求1所述的半导体装置，其中，所述第一绝缘层和所述第二绝缘层中的每个由陶瓷制成。
24.根据权利要求1所述的半导体装置，其中，所述中间金属化层是封闭的、非穿孔的金属层。
25.根据权利要求12所述的半导体装置，其中，所述N个子载体的电介质都不包括将各个子载体的第一金属与所述中间金属化层电连接的通孔。
26.根据权利要求1所述的半导体装置，其中，所述第一绝缘层是无任何通孔的、封闭的、非穿孔的介电层。
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