CN1333353C - 支持不同脉冲时间存取而无须变更模式寄存器中脉冲时间设定的dram - Google Patents

支持不同脉冲时间存取而无须变更模式寄存器中脉冲时间设定的dram Download PDF

Info

Publication number
CN1333353C
CN1333353C CNB038165392A CN03816539A CN1333353C CN 1333353 C CN1333353 C CN 1333353C CN B038165392 A CNB038165392 A CN B038165392A CN 03816539 A CN03816539 A CN 03816539A CN 1333353 C CN1333353 C CN 1333353C
Authority
CN
China
Prior art keywords
pulse time
memory
memory device
access
command
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNB038165392A
Other languages
English (en)
Chinese (zh)
Other versions
CN1669012A (zh
Inventor
S·帕特尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of CN1669012A publication Critical patent/CN1669012A/zh
Application granted granted Critical
Publication of CN1333353C publication Critical patent/CN1333353C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Executing Machine-Instructions (AREA)
CNB038165392A 2002-07-11 2003-07-09 支持不同脉冲时间存取而无须变更模式寄存器中脉冲时间设定的dram Expired - Lifetime CN1333353C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/193,828 2002-07-11
US10/193,828 US6957308B1 (en) 2002-07-11 2002-07-11 DRAM supporting different burst-length accesses without changing the burst length setting in the mode register

Publications (2)

Publication Number Publication Date
CN1669012A CN1669012A (zh) 2005-09-14
CN1333353C true CN1333353C (zh) 2007-08-22

Family

ID=30114615

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB038165392A Expired - Lifetime CN1333353C (zh) 2002-07-11 2003-07-09 支持不同脉冲时间存取而无须变更模式寄存器中脉冲时间设定的dram

Country Status (9)

Country Link
US (1) US6957308B1 (enExample)
EP (1) EP1522021B1 (enExample)
JP (1) JP4507186B2 (enExample)
KR (1) KR101005114B1 (enExample)
CN (1) CN1333353C (enExample)
AU (1) AU2003258997A1 (enExample)
DE (1) DE60313323T2 (enExample)
TW (1) TWI307464B (enExample)
WO (1) WO2004008329A1 (enExample)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7475168B2 (en) * 2004-03-11 2009-01-06 Sonics, Inc. Various methods and apparatus for width and burst conversion
US7543088B2 (en) 2004-03-11 2009-06-02 Sonics, Inc. Various methods and apparatuses for width and burst conversion
US8122187B2 (en) * 2004-07-02 2012-02-21 Qualcomm Incorporated Refreshing dynamic volatile memory
US8032676B2 (en) 2004-11-02 2011-10-04 Sonics, Inc. Methods and apparatuses to manage bandwidth mismatches between a sending device and a receiving device
US7620783B2 (en) * 2005-02-14 2009-11-17 Qualcomm Incorporated Method and apparatus for obtaining memory status information cross-reference to related applications
US7640392B2 (en) * 2005-06-23 2009-12-29 Qualcomm Incorporated Non-DRAM indicator and method of accessing data not stored in DRAM array
WO2007099447A2 (en) * 2006-03-02 2007-09-07 Nokia Corporation Method and system for flexible burst length control
KR100799132B1 (ko) 2006-06-29 2008-01-29 주식회사 하이닉스반도체 초기값변경이 가능한 모드레지스터셋회로.
US9262326B2 (en) * 2006-08-14 2016-02-16 Qualcomm Incorporated Method and apparatus to enable the cooperative signaling of a shared bus interrupt in a multi-rank memory subsystem
US20080059748A1 (en) * 2006-08-31 2008-03-06 Nokia Corporation Method, mobile device, system and software for a write method with burst stop and data masks
US20080301391A1 (en) * 2007-06-01 2008-12-04 Jong-Hoon Oh Method and apparatus for modifying a burst length for semiconductor memory
KR101260313B1 (ko) * 2007-06-12 2013-05-03 삼성전자주식회사 전자장치 및 그 데이터 송수신방법과, 슬레이브 장치 및복수의 장치 간의 통신방법
US7688628B2 (en) * 2007-06-30 2010-03-30 Intel Corporation Device selection circuit and method
TWI358735B (en) * 2008-01-03 2012-02-21 Nanya Technology Corp Memory access control method
US20100325333A1 (en) * 2008-10-14 2010-12-23 Texas Instruments Incorporated Method Allowing Processor with Fewer Pins to Use SDRAM
US8266471B2 (en) * 2010-02-09 2012-09-11 Mosys, Inc. Memory device including a memory block having a fixed latency data output
US8856579B2 (en) * 2010-03-15 2014-10-07 International Business Machines Corporation Memory interface having extended strobe burst for read timing calibration
US9319880B2 (en) * 2010-09-15 2016-04-19 Intel Corporation Reformatting data to decrease bandwidth between a video encoder and a buffer
KR101873526B1 (ko) * 2011-06-09 2018-07-02 삼성전자주식회사 에러 정정회로를 구비한 온 칩 데이터 스크러빙 장치 및 방법
KR101964261B1 (ko) 2012-05-17 2019-04-01 삼성전자주식회사 자기 메모리 장치
CN105474318A (zh) 2013-07-26 2016-04-06 慧与发展有限责任合伙企业 响应于第二读取请求的第一数据
US10534540B2 (en) 2016-06-06 2020-01-14 Micron Technology, Inc. Memory protocol
US10198195B1 (en) * 2017-08-04 2019-02-05 Micron Technology, Inc. Wear leveling
US10846253B2 (en) 2017-12-21 2020-11-24 Advanced Micro Devices, Inc. Dynamic page state aware scheduling of read/write burst transactions
KR102671077B1 (ko) 2018-11-15 2024-06-03 에스케이하이닉스 주식회사 반도체장치
US11270416B2 (en) 2019-12-27 2022-03-08 Nxp Usa, Inc. System and method of using optimized descriptor coding for geometric correction to reduce memory transfer bandwidth overhead
US11687281B2 (en) * 2021-03-31 2023-06-27 Advanced Micro Devices, Inc. DRAM command streak efficiency management
US12307095B2 (en) * 2022-03-14 2025-05-20 Mediatek Inc. Electronic system and method for controlling burst length to access memory device of electronic system
US12475969B2 (en) 2022-09-14 2025-11-18 Rambus Inc. Dynamic random access memory (DRAM) device with variable burst lengths

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5754825A (en) * 1995-05-19 1998-05-19 Compaq Computer Corporation Lower address line prediction and substitution
US6226724B1 (en) * 1997-09-03 2001-05-01 Motorola, Inc. Memory controller and method for generating commands to a memory
US6393500B1 (en) * 1999-08-12 2002-05-21 Mips Technologies, Inc. Burst-configurable data bus

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7681005B1 (en) * 1996-01-11 2010-03-16 Micron Technology, Inc. Asynchronously-accessible memory device with mode selection circuitry for burst or pipelined operation
JPH10208468A (ja) * 1997-01-28 1998-08-07 Hitachi Ltd 半導体記憶装置並びに同期型半導体記憶装置
JPH11134243A (ja) * 1997-10-31 1999-05-21 Brother Ind Ltd 記憶装置の制御装置及びデータ処理システムにおける記憶装置の制御方法
JP3948141B2 (ja) * 1998-09-24 2007-07-25 富士通株式会社 半導体記憶装置及びその制御方法
US6606352B2 (en) 1999-01-15 2003-08-12 Broadcom Corporation Method and apparatus for converting between byte lengths and burdened burst lengths in a high speed modem
KR20020014563A (ko) * 2000-08-18 2002-02-25 윤종용 반도체 메모리 장치
US6549991B1 (en) * 2000-08-31 2003-04-15 Silicon Integrated Systems Corp. Pipelined SDRAM memory controller to optimize bus utilization
JP4025002B2 (ja) 2000-09-12 2007-12-19 株式会社東芝 半導体記憶装置
US6895474B2 (en) * 2002-04-29 2005-05-17 Micron Technology, Inc. Synchronous DRAM with selectable internal prefetch size

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5754825A (en) * 1995-05-19 1998-05-19 Compaq Computer Corporation Lower address line prediction and substitution
US6226724B1 (en) * 1997-09-03 2001-05-01 Motorola, Inc. Memory controller and method for generating commands to a memory
US6393500B1 (en) * 1999-08-12 2002-05-21 Mips Technologies, Inc. Burst-configurable data bus

Also Published As

Publication number Publication date
DE60313323T2 (de) 2007-12-27
TWI307464B (en) 2009-03-11
WO2004008329A1 (en) 2004-01-22
DE60313323D1 (de) 2007-05-31
CN1669012A (zh) 2005-09-14
EP1522021A1 (en) 2005-04-13
TW200401191A (en) 2004-01-16
AU2003258997A1 (en) 2004-02-02
JP4507186B2 (ja) 2010-07-21
JP2005532657A (ja) 2005-10-27
KR101005114B1 (ko) 2010-12-30
KR20050025960A (ko) 2005-03-14
US6957308B1 (en) 2005-10-18
EP1522021B1 (en) 2007-04-18

Similar Documents

Publication Publication Date Title
CN1333353C (zh) 支持不同脉冲时间存取而无须变更模式寄存器中脉冲时间设定的dram
US6981100B2 (en) Synchronous DRAM with selectable internal prefetch size
CN100386753C (zh) 脉冲串长度比预取长度短的存储器系统
US6393531B1 (en) Queue based data control mechanism for queue based memory controller
US6681301B1 (en) System for controlling multiple memory types
US6622228B2 (en) System and method of processing memory requests in a pipelined memory controller
US20090276548A1 (en) Dynamically setting burst type of a double data rate memory device
JP4199658B2 (ja) 読出及び書込動作でバースト順序が異なるアドレッシングを行うメモリデバイス
CN101398793A (zh) 存储器控制设备和半导体处理装置
JPH10207771A (ja) メモリ動作短縮方法
JP2022543819A (ja) 誤り検出および誤り訂正のための方法ならびに誤り検出および誤り訂正のための対応するシステムおよび装置
US6976122B1 (en) Dynamic idle counter threshold value for use in memory paging policy
US8024533B2 (en) Host memory interface for a parallel processor
CN1652248B (zh) 用地址信号设置运行模式的方法和存储系统
GB2430053A (en) Accessing external memory from an system on a chip integrated circuit
KR100298955B1 (ko) 데이타처리시스템
CN100377138C (zh) 地址译码的方法与系统
JP6182528B2 (ja) 構成コマンドを伝えるためのメモリシステム及び方法
KR100436098B1 (ko) 데이터프로세서,데이터처리시스템,및데이터프로세서를이용한외부장치로의액세스방법
US20080059748A1 (en) Method, mobile device, system and software for a write method with burst stop and data masks
US6385687B2 (en) Method and apparatus for simultaneously accessing the tag and data arrays of a memory device
US20070094460A1 (en) DRAM control circuit
JP2004507817A (ja) Ｄｒａｍ制御回路

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term

Granted publication date: 20070822

CX01 Expiry of patent term