KR101005114B1 - 모드 레지스터에서의 버스트 길이 설정 변화 없이 상이한버스트―길이 액세스들을 지원하는 ｄｒａｍ - Google Patents

모드 레지스터에서의 버스트 길이 설정 변화 없이 상이한버스트―길이 액세스들을 지원하는 ｄｒａｍ Download PDF

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KR101005114B1
KR101005114B1 KR1020057000475A KR20057000475A KR101005114B1 KR 101005114 B1 KR101005114 B1 KR 101005114B1 KR 1020057000475 A KR1020057000475 A KR 1020057000475A KR 20057000475 A KR20057000475 A KR 20057000475A KR 101005114 B1 KR101005114 B1 KR 101005114B1
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burst length
burst
command
memory device
memory
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KR20050025960A (ko
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파텔스웨탈
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Executing Machine-Instructions (AREA)
KR1020057000475A 2002-07-11 2003-07-09 모드 레지스터에서의 버스트 길이 설정 변화 없이 상이한버스트―길이 액세스들을 지원하는 ｄｒａｍ Expired - Lifetime KR101005114B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/193,828 2002-07-11
US10/193,828 US6957308B1 (en) 2002-07-11 2002-07-11 DRAM supporting different burst-length accesses without changing the burst length setting in the mode register

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KR20050025960A KR20050025960A (ko) 2005-03-14
KR101005114B1 true KR101005114B1 (ko) 2010-12-30

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KR1020057000475A Expired - Lifetime KR101005114B1 (ko) 2002-07-11 2003-07-09 모드 레지스터에서의 버스트 길이 설정 변화 없이 상이한버스트―길이 액세스들을 지원하는 ｄｒａｍ

Country Status (9)

Country Link
US (1) US6957308B1 (enExample)
EP (1) EP1522021B1 (enExample)
JP (1) JP4507186B2 (enExample)
KR (1) KR101005114B1 (enExample)
CN (1) CN1333353C (enExample)
AU (1) AU2003258997A1 (enExample)
DE (1) DE60313323T2 (enExample)
TW (1) TWI307464B (enExample)
WO (1) WO2004008329A1 (enExample)

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US10762935B2 (en) 2018-11-15 2020-09-01 SK Hynix Inc. Semiconductor devices

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US8122187B2 (en) * 2004-07-02 2012-02-21 Qualcomm Incorporated Refreshing dynamic volatile memory
US8032676B2 (en) 2004-11-02 2011-10-04 Sonics, Inc. Methods and apparatuses to manage bandwidth mismatches between a sending device and a receiving device
US7620783B2 (en) * 2005-02-14 2009-11-17 Qualcomm Incorporated Method and apparatus for obtaining memory status information cross-reference to related applications
US7640392B2 (en) * 2005-06-23 2009-12-29 Qualcomm Incorporated Non-DRAM indicator and method of accessing data not stored in DRAM array
WO2007099447A2 (en) * 2006-03-02 2007-09-07 Nokia Corporation Method and system for flexible burst length control
KR100799132B1 (ko) 2006-06-29 2008-01-29 주식회사 하이닉스반도체 초기값변경이 가능한 모드레지스터셋회로.
US9262326B2 (en) * 2006-08-14 2016-02-16 Qualcomm Incorporated Method and apparatus to enable the cooperative signaling of a shared bus interrupt in a multi-rank memory subsystem
US20080059748A1 (en) * 2006-08-31 2008-03-06 Nokia Corporation Method, mobile device, system and software for a write method with burst stop and data masks
US20080301391A1 (en) * 2007-06-01 2008-12-04 Jong-Hoon Oh Method and apparatus for modifying a burst length for semiconductor memory
KR101260313B1 (ko) * 2007-06-12 2013-05-03 삼성전자주식회사 전자장치 및 그 데이터 송수신방법과, 슬레이브 장치 및복수의 장치 간의 통신방법
US7688628B2 (en) * 2007-06-30 2010-03-30 Intel Corporation Device selection circuit and method
TWI358735B (en) * 2008-01-03 2012-02-21 Nanya Technology Corp Memory access control method
US20100325333A1 (en) * 2008-10-14 2010-12-23 Texas Instruments Incorporated Method Allowing Processor with Fewer Pins to Use SDRAM
US8266471B2 (en) * 2010-02-09 2012-09-11 Mosys, Inc. Memory device including a memory block having a fixed latency data output
US8856579B2 (en) * 2010-03-15 2014-10-07 International Business Machines Corporation Memory interface having extended strobe burst for read timing calibration
US9319880B2 (en) * 2010-09-15 2016-04-19 Intel Corporation Reformatting data to decrease bandwidth between a video encoder and a buffer
KR101873526B1 (ko) * 2011-06-09 2018-07-02 삼성전자주식회사 에러 정정회로를 구비한 온 칩 데이터 스크러빙 장치 및 방법
KR101964261B1 (ko) * 2012-05-17 2019-04-01 삼성전자주식회사 자기 메모리 장치
EP3025347A1 (en) 2013-07-26 2016-06-01 Hewlett Packard Enterprise Development LP First data in response to second read request
US10534540B2 (en) 2016-06-06 2020-01-14 Micron Technology, Inc. Memory protocol
US10198195B1 (en) * 2017-08-04 2019-02-05 Micron Technology, Inc. Wear leveling
US10846253B2 (en) 2017-12-21 2020-11-24 Advanced Micro Devices, Inc. Dynamic page state aware scheduling of read/write burst transactions
US11270416B2 (en) 2019-12-27 2022-03-08 Nxp Usa, Inc. System and method of using optimized descriptor coding for geometric correction to reduce memory transfer bandwidth overhead
US11687281B2 (en) * 2021-03-31 2023-06-27 Advanced Micro Devices, Inc. DRAM command streak efficiency management
US12307095B2 (en) 2022-03-14 2025-05-20 Mediatek Inc. Electronic system and method for controlling burst length to access memory device of electronic system
US12475969B2 (en) 2022-09-14 2025-11-18 Rambus Inc. Dynamic random access memory (DRAM) device with variable burst lengths

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Publication number Priority date Publication date Assignee Title
US10762935B2 (en) 2018-11-15 2020-09-01 SK Hynix Inc. Semiconductor devices

Also Published As

Publication number Publication date
EP1522021B1 (en) 2007-04-18
WO2004008329A1 (en) 2004-01-22
CN1333353C (zh) 2007-08-22
KR20050025960A (ko) 2005-03-14
JP4507186B2 (ja) 2010-07-21
DE60313323D1 (de) 2007-05-31
TW200401191A (en) 2004-01-16
AU2003258997A1 (en) 2004-02-02
EP1522021A1 (en) 2005-04-13
US6957308B1 (en) 2005-10-18
JP2005532657A (ja) 2005-10-27
TWI307464B (en) 2009-03-11
CN1669012A (zh) 2005-09-14
DE60313323T2 (de) 2007-12-27

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